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1. 发明申请

WO2011048522A3 NEIGHBORHOOD OPERATIONS FOR PARALLEL PROCESSING 审中-公开
标题翻译：并行处理的邻里操作
公开(公告)号：WO2011048522A3
公开(公告)日：2011-08-04
申请号：PCT/IB2010054526
申请日：2010-10-06
申请人： ZIKBIT LTD , AKERIB AVIDAN , EHRMAN ELI , AGAM OREN , MEYASSED MOSHE , MEIR YEHOSHUA , FUKUZO YUKIO
发明人： AKERIB AVIDAN , EHRMAN ELI , AGAM OREN , MEYASSED MOSHE , MEIR YEHOSHUA , FUKUZO YUKIO
IPC分类号： G06F13/00 , G06F13/28
CPC分类号： G11C7/1006
摘要： A memory device includes a plurality of storage units in which to store data of a bank, wherein the data has a logical order prior to storage and a physical order different than the logical order within the plurality of storage units and a within-device reordering unit to reorder the data of a bank into the logical order prior to performing on-chip processing. In another embodiment, the memory device includes an external device interface connectable to an external device communicating with the memory device, an internal processing element to process data stored on the device and multiple banks of storage. Each bank includes a plurality of storage units and each storage unit has two ports, an external port connectable to the external device interface and an internal port connected to the internal processing element.
摘要翻译：一种存储装置包括多个存储单元，用于存储存储体的数据，其中该数据具有在存储之前的逻辑顺序和与该多个存储单元内的逻辑顺序不同的物理顺序，以及一个设备内重排序单元在执行片上处理之前将存储体的数据重新排列成逻辑顺序。在另一个实施例中，存储设备包括可连接到与存储器设备通信的外部设备的外部设备接口，用于处理存储在设备上的数据和多组存储器的内部处理元件。每个存储体包括多个存储单元，每个存储单元具有两个端口，可连接到外部设备接口的外部端口和连接到内部处理元件的内部端口。

2. 发明申请

WO2010079450A3 SYSTEM, METHOD AND APPARATUS FOR MEMORY WITH SEMAPHORE CONTROLLED ACCESS OF COMPONENT RAM CELLS BY AN EXTERNAL COMPONENT 审中-公开
标题翻译：用于利用外部组件对SEMAPHORE控制存取组件RAM存储器的系统，方法和装置
公开(公告)号：WO2010079450A3
公开(公告)日：2010-09-02
申请号：PCT/IB2010050047
申请日：2010-01-07
申请人： ZIKBIT LTD , AKERIB AVIDAN , EHRMAN ELI , MEIR JOSH , MEYASSED MOSHE , ALPERN YAIR , AGAM OREN
发明人： AKERIB AVIDAN , EHRMAN ELI , MEIR JOSH , MEYASSED MOSHE , ALPERN YAIR , AGAM OREN
IPC分类号： G06F13/00
CPC分类号： G11C15/00 , G06F9/3879 , G06F15/7821 , G11C7/1006 , G11C11/005
摘要： An integrated circuit device includes a semiconductor substrate, an array of random access memory (RAM) cells, which are arranged on the substrate in first columns and are configured to store data, a computational section including associative memory cells, which are arranged on the substrate in second columns, which are in communication with the respective first columns so as to receive the data from the array of the RAM cells and to perform an associative computation on the data, and a semaphore to control an access of an external component to at least a portion of the array of RAM cells.
摘要翻译：一种集成电路器件包括半导体衬底，在第一列中布置在衬底上并且被配置为存储数据的随机存取存储器（RAM）单元的阵列，包括关联存储器单元的计算部分，其被布置在衬底上在与相应的第一列通信以便接收来自RAM单元阵列的数据并且对数据执行关联计算的第二列中，以及用于至少控制外部组件的访问的信号灯 RAM单元阵列的一部分。

3. 发明申请

WO2010079448A3 SYSTEM, METHOD AND APPARATUS FOR MEMORY WITH CONTROL LOGIC TO CONTROL ASSOCIATIVE COMPUTATIONS 审中-公开
标题翻译：具有控制逻辑以控制联想计算的存储器的系统，方法和设备
公开(公告)号：WO2010079448A3
公开(公告)日：2010-09-02
申请号：PCT/IB2010050045
申请日：2010-01-07
申请人： ZIKBIT LTD , AKERIB AVIDAN , EHRMAN ELI , MEIR JOSH , MEYASSED MOSHE , ALPERN YAIR , AGAM OREN
发明人： AKERIB AVIDAN , EHRMAN ELI , MEIR JOSH , MEYASSED MOSHE , ALPERN YAIR , AGAM OREN
IPC分类号： G06F12/00
CPC分类号： G11C15/00 , G06F9/3879 , G06F15/7821 , G11C7/1006 , G11C11/005
摘要： An integrated circuit device includes a semiconductor substrate, an array of random access memory (RAM) cells, which are arranged on the substrate in first columns and are configured to store data, a computational section including associative memory cells, which are arranged on the substrate in second columns, which are in communication with the respective first columns so as to receive the data from the array of the RAM cells and to perform an associative computation on the data, and control logic to control the associative computation.
摘要翻译：一种集成电路器件包括半导体衬底，在第一列中布置在衬底上并且被配置为存储数据的随机存取存储器（RAM）单元的阵列，包括关联存储器单元的计算部分，其被布置在衬底上在与各个第一列通信以便接收来自RAM单元阵列的数据并对数据执行关联计算的第二列中，以及控制关联计算的控制逻辑。

4. 发明申请

WO2010079451A1 MEMORY WITH SMALLER, FASTER, AND/OR LESS COMPLEX STORAGE CELLS 审中-公开
标题翻译：存储器与小型，更快速和/或更少的复杂存储单元
公开(公告)号：WO2010079451A1
公开(公告)日：2010-07-15
申请号：PCT/IB2010/050048
申请日：2010-01-07
申请人： ZIKBIT LTD. , AKERIB, Avidan , EHRMAN, Eli , MEIR, Josh , MEYASSED, Moshe , ALPERN, Yair , AGAM, Oren
发明人： AKERIB, Avidan , EHRMAN, Eli , MEIR, Josh , MEYASSED, Moshe , ALPERN, Yair , AGAM, Oren
IPC分类号： G06F12/00
CPC分类号： G11C15/00 , G06F9/3879 , G06F15/7821 , G11C7/1006 , G11C11/005
摘要： An integrated circuit device includes a semiconductor substrate, an array of random access memory (RAM) cells, which are arranged on the substrate in first columns and are configured to store data, and a computational section including associative memory cells, which are arranged on the substrate in second columns, which are in communication with the respective first columns so as to receive the data from the array of the RAM cells and to perform an associative computation on the data where the computational section includes multiple storage cells configured to store information and where the storage cells are at least one of smaller, faster and less complex than the associative memory cells.
摘要翻译：集成电路装置包括半导体衬底，随机存取存储器（RAM）单元阵列，其布置在第一列中的衬底上并被配置为存储数据;以及计算部分，包括关联存储器单元，其布置在第二列中的衬底，其与相应的第一列通信，以便从RAM单元的阵列接收数据，并且对数据执行关联计算，其中计算部分包括被配置为存储信息的多个存储单元以及其中存储单元是比关联存储器单元更小，更快和更复杂的至少一个。

5. 发明申请

WO2011007304A1 USING STORAGE CELLS TO PERFORM COMPUTATION 审中-公开
标题翻译：使用储存细胞进行计算
公开(公告)号：WO2011007304A1
公开(公告)日：2011-01-20
申请号：PCT/IB2010/053168
申请日：2010-07-11
申请人： ZIKBIT LTD. , AKERIB, Avidan , AGAM, Oren , EHRMAN, Eli , MEYASSED, Moshe
发明人： AKERIB, Avidan , AGAM, Oren , EHRMAN, Eli , MEYASSED, Moshe
IPC分类号： G06F13/00
CPC分类号： G11C29/34 , G11C15/043
摘要： An in-memory processor includes a memory array which stores data and an activation unit to activate at least two cells in a column of the memory array at generally the same time thereby to generate a Boolean function output of the data of the at least two cells. Another embodiment shows a content addressable memory (CAM) unit using memory array cells.
摘要翻译：存储器内处理器包括存储数据的存储器阵列和激活单元，用于在大致相同的时间激活存储器阵列的列中的至少两个单元，从而生成至少两个单元的数据的布尔函数输出。另一个实施例示出了使用存储器阵列单元的内容可寻址存储器（CAM）单元。

6. 发明申请

WO2009031143A2 A MEMORY-PROCESSOR SYSTEM AND METHODS USEFUL IN CONJUNCTION THEREWITH 审中-公开
标题翻译：一种内存处理器系统及其连接中有用的方法
公开(公告)号：WO2009031143A2
公开(公告)日：2009-03-12
申请号：PCT/IL2008001191
申请日：2008-09-04
申请人： ZIKBIT LTD , AKERIB AVIDAN , LAVI YOAV , EHRMAN ELI
发明人： AKERIB AVIDAN , LAVI YOAV , EHRMAN ELI
IPC分类号： G06F19/00
CPC分类号： G11C15/00 , G11C15/04
摘要： A computational system comprising a central processing unit; and an amphibian memory-processor including a population of amphibian cells each having a selectable mode of operation selected from among a memory content outputting mode of operation, a memory content inputting mode of operation and a processing mode of operation in which the cell performs a computational process, the central processing unit being operative to issue commands, each command corresponding to one of the above modes of operation and defining a subpopulation of amphibian cells including at least one amphibian cells from among the population of amphibian cells, wherein responsive to the command, each amphibian cell within the subpopulation of amphibian cells enters the corresponding mode of operation and executes the command.
摘要翻译：一种计算系统，包括中央处理单元; 以及两栖类存储器处理器，其包括从存储器内容输出操作模式，存储器内容输入操作模式和操作的处理模式中选择的具有可选操作模式的两栖动物细胞群，其中，所述小区执行计算过程中，中央处理单元可操作以发出命令，每个命令对应于上述操作模式之一，并定义包括两栖动物细胞群体中的至少一个两栖动物细胞的两栖动物细胞的亚群，其中响应于该命令，两栖动物细胞亚群内的每个两栖动物细胞都进入相应的操作模式并执行命令。

7. 发明申请

WO2010079450A2 SYSTEM, METHOD AND APPARATUS FOR MEMORY WITH SEMAPHORE CONTROLLED ACCESS OF COMPONENT RAM CELLS BY AN EXTERNAL COMPONENT 审中-公开
标题翻译：用外部元件控制分量RAM电池的存储器的系统，方法和装置
公开(公告)号：WO2010079450A2
公开(公告)日：2010-07-15
申请号：PCT/IB2010/050047
申请日：2010-01-07
申请人： ZIKBIT LTD. , AKERIB, Avidan , EHRMAN, Eli , MEIR, Josh , MEYASSED, Moshe , ALPERN, Yair , AGAM, Oren
发明人： AKERIB, Avidan , EHRMAN, Eli , MEIR, Josh , MEYASSED, Moshe , ALPERN, Yair , AGAM, Oren
IPC分类号： G11C15/00 , G11C7/00 , G06F12/02
CPC分类号： G11C15/00 , G06F9/3879 , G06F15/7821 , G11C7/1006 , G11C11/005
摘要： An integrated circuit device includes a semiconductor substrate, an array of random access memory (RAM) cells, which are arranged on the substrate in first columns and are configured to store data, a computational section including associative memory cells, which are arranged on the substrate in second columns, which are in communication with the respective first columns so as to receive the data from the array of the RAM cells and to perform an associative computation on the data, and a semaphore to control an access of an external component to at least a portion of the array of RAM cells.
摘要翻译：一种集成电路装置，包括半导体衬底，随机存取存储器（RAM）单元阵列，其布置在第一列中的衬底上并被配置为存储数据;计算部分，包括相关存储器单元，其布置在衬底上在第二列中，它们与相应的第一列通信，以便从RAM单元的阵列接收数据，并且对该数据执行关联计算，以及信号量，至少控制外部组件的访问 RAM单元阵列的一部分。

8. 发明申请

WO2010079449A1 SYSTEM, METHOD AND APPARATUS FOR MEMORY WITH GENERALLY SIMULTANEOUS ACCESS OF RAM CELLS BY EMBEDDED COMPUTATIONAL SECTION AND AN EXTERNAL COMPONENT 审中-公开
标题翻译：通过嵌入式计算部分和外部组件通常同时访问RAM电池的存储器的系统，方法和装置
公开(公告)号：WO2010079449A1
公开(公告)日：2010-07-15
申请号：PCT/IB2010/050046
申请日：2010-01-07
申请人： ZIKBIT LTD. , AKERIB, Avidan , EHRMAN, Eli , MEIR, Josh , MEYASSED, Moshe , ALPERN, Yair , AGAM, Oren
发明人： AKERIB, Avidan , EHRMAN, Eli , MEIR, Josh , MEYASSED, Moshe , ALPERN, Yair , AGAM, Oren
IPC分类号： G06F13/00
CPC分类号： G11C15/00 , G06F9/3879 , G06F15/7821 , G11C7/1006 , G11C11/005
摘要： An integrated circuit device including a semiconductor substrate, an array of random access memory (RAM) cells arranged on the substrate in first columns and configured to store data, a computational section to receive the data from the RAM cell array, and interfacing circuitry that enables generally simultaneous accesses to the RAM cell array at least by an external component and by the computational section, additionally a method for computing, including accepting and executing at least one command from a host processor to a memory device, the command including a write command to store data at a specified address in an array of random access memory cells formed on a semiconductor substrate in the memory device, responsively to the command, transferring the data into a computational section of the memory device, and performing generally simultaneous accesses to different RAM cells at least by an external component and the computational section.
摘要翻译：一种集成电路装置，包括半导体衬底，布置在第一列中的衬底上并被配置为存储数据的随机存取存储器（RAM）单元阵列，用于从RAM单元阵列接收数据的计算部分，以及使能通常至少由外部组件和计算部分同时访问RAM单元阵列，另外还包括一种用于计算的方法，包括从主机处理器接收并执行至少一个命令到存储器件，该命令包括写入命令将数据存储在形成在存储器件中的半导体衬底上的随机存取存储器单元的阵列中的指定地址处，响应于命令将数据传送到存储器件的计算部分，并且对不同的RAM单元进行大致同时的访问至少由外部组件和计算部分组成。

9. 发明申请

WO2010079448A2 SYSTEM, METHOD AND APPARATUS FOR MEMORY WITH CONTROL LOGIC TO CONTROL ASSOCIATIVE COMPUTATIONS 审中-公开
标题翻译：具有控制逻辑的存储器的系统，方法和装置来控制相关计算
公开(公告)号：WO2010079448A2
公开(公告)日：2010-07-15
申请号：PCT/IB2010/050045
申请日：2010-01-07
申请人： ZIKBIT LTD. , AKERIB, Avidan , EHRMAN, Eli , MEIR, Josh , MEYASSED, Moshe , ALPERN, Yair , AGAM, Oren
发明人： AKERIB, Avidan , EHRMAN, Eli , MEIR, Josh , MEYASSED, Moshe , ALPERN, Yair , AGAM, Oren
IPC分类号： G11C15/00 , G11C7/00 , G06F12/02
CPC分类号： G11C15/00 , G06F9/3879 , G06F15/7821 , G11C7/1006 , G11C11/005
摘要： An integrated circuit device includes a semiconductor substrate, an array of random access memory (RAM) cells, which are arranged on the substrate in first columns and are configured to store data, a computational section including associative memory cells, which are arranged on the substrate in second columns, which are in communication with the respective first columns so as to receive the data from the array of the RAM cells and to perform an associative computation on the data, and control logic to control the associative computation.
摘要翻译：一种集成电路装置，包括半导体衬底，随机存取存储器（RAM）单元阵列，其布置在第一列中的衬底上并被配置为存储数据;计算部分，包括相关存储器单元，其布置在衬底上在第二列中，它们与各自的第一列通信，以便从RAM单元的阵列接收数据，并且对数据执行关联计算，以及控制逻辑来控制关联计算。

10. 发明申请

WO2009031143A3 A MEMORY-PROCESSOR SYSTEM AND METHODS USEFUL IN CONJUNCTION THEREWITH 审中-公开
公开(公告)号：WO2009031143A3
公开(公告)日：2009-03-12
申请号：PCT/IL2008/001191
申请日：2008-09-04
申请人： ZIKBIT LTD. , AKERIB, Avidan , LAVI, Yoav , EHRMAN, Eli
发明人： AKERIB, Avidan , LAVI, Yoav , EHRMAN, Eli
IPC分类号： G06F15/00
摘要： A computational system comprising a central processing unit; and an amphibian memory-processor including a population of amphibian cells each having a selectable mode of operation selected from among a memory content outputting mode of operation, a memory content inputting mode of operation and a processing mode of operation in which the cell performs a computational process, the central processing unit being operative to issue commands, each command corresponding to one of the above modes of operation and defining a subpopulation of amphibian cells including at least one amphibian cells from among the population of amphibian cells, wherein responsive to the command, each amphibian cell within the subpopulation of amphibian cells enters the corresponding mode of operation and executes the command.

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