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1. 发明申请

WO2011048522A3 NEIGHBORHOOD OPERATIONS FOR PARALLEL PROCESSING 审中-公开
标题翻译：并行处理的邻里操作
公开(公告)号：WO2011048522A3
公开(公告)日：2011-08-04
申请号：PCT/IB2010054526
申请日：2010-10-06
申请人： ZIKBIT LTD , AKERIB AVIDAN , EHRMAN ELI , AGAM OREN , MEYASSED MOSHE , MEIR YEHOSHUA , FUKUZO YUKIO
发明人： AKERIB AVIDAN , EHRMAN ELI , AGAM OREN , MEYASSED MOSHE , MEIR YEHOSHUA , FUKUZO YUKIO
IPC分类号： G06F13/00 , G06F13/28
CPC分类号： G11C7/1006
摘要： A memory device includes a plurality of storage units in which to store data of a bank, wherein the data has a logical order prior to storage and a physical order different than the logical order within the plurality of storage units and a within-device reordering unit to reorder the data of a bank into the logical order prior to performing on-chip processing. In another embodiment, the memory device includes an external device interface connectable to an external device communicating with the memory device, an internal processing element to process data stored on the device and multiple banks of storage. Each bank includes a plurality of storage units and each storage unit has two ports, an external port connectable to the external device interface and an internal port connected to the internal processing element.
摘要翻译：一种存储装置包括多个存储单元，用于存储存储体的数据，其中该数据具有在存储之前的逻辑顺序和与该多个存储单元内的逻辑顺序不同的物理顺序，以及一个设备内重排序单元在执行片上处理之前将存储体的数据重新排列成逻辑顺序。在另一个实施例中，存储设备包括可连接到与存储器设备通信的外部设备的外部设备接口，用于处理存储在设备上的数据和多组存储器的内部处理元件。每个存储体包括多个存储单元，每个存储单元具有两个端口，可连接到外部设备接口的外部端口和连接到内部处理元件的内部端口。

2. 发明申请

WO2011048522A2 NEIGHBORHOOD OPERATIONS FOR PARALLEL PROCESSING 审中-公开
标题翻译：用于平行加工的邻域操作
公开(公告)号：WO2011048522A2
公开(公告)日：2011-04-28
申请号：PCT/IB2010/054526
申请日：2010-10-06
申请人： ZIKBIT LTD. , AKERIB, Avidan , EHRMAN, Eli , AGAM, Oren , MEYASSED, Moshe , MEIR, Yehoshua , FUKUZO, Yukio
发明人： AKERIB, Avidan , EHRMAN, Eli , AGAM, Oren , MEYASSED, Moshe , MEIR, Yehoshua , FUKUZO, Yukio
IPC分类号： H01L27/108
CPC分类号： G11C7/1006
摘要： A memory device includes a plurality of storage units in which to store data of a bank, wherein the data has a logical order prior to storage and a physical order different than the logical order within the plurality of storage units and a within-device reordering unit to reorder the data of a bank into the logical order prior to performing on-chip processing. In another embodiment, the memory device includes an external device interface connectable to an external device communicating with the memory device, an internal processing element to process data stored on the device and multiple banks of storage. Each bank includes a plurality of storage units and each storage unit has two ports, an external port connectable to the external device interface and an internal port connected to the internal processing element.
摘要翻译：一种存储器装置包括多个存储单元，在所述多个存储单元中存储存储体的数据，其中所述数据具有存储之前的逻辑顺序和与所述多个存储器内的逻辑顺序不同的物理顺序单元和设备内重新排序单元，以在执行片上处理之前将银行的数据重新排序为逻辑顺序。在另一个实施例中，存储装置包括可连接到与存储装置通信的外部装置的外部装置接口，处理存储在装置上的数据和多个存储库的内部处理元件。每个存储体包括多个存储单元，并且每个存储单元具有两个端口，可连接到外部装置接口的外部端口和连接到内部处理单元的内部端口。

3. 发明申请

WO2011048572A3 AN IN-MEMORY PROCESSOR 审中-公开
标题翻译：内存中的处理器
公开(公告)号：WO2011048572A3
公开(公告)日：2011-11-10
申请号：PCT/IB2010054780
申请日：2010-10-21
申请人： ZIKBIT LTD , AGAM OREN , MEYASSED MOSHE , FUKUZO YUKIO
发明人： AGAM OREN , MEYASSED MOSHE , FUKUZO YUKIO
IPC分类号： G06F13/00
CPC分类号： G11C7/1006
摘要： A memory device includes at least two memory banks storing data and an internal processor. The at least two memory banks are accessible by a host processor. The internal processor receives a timeslot from the host processor and processes a portion of the data from an indicated one of the at least two banks of the memory array during the timeslot while the remaining banks are available to the host processor during the timeslot. A method of operating a memory device having banks storing data includes a host processor issuing per bank timeslots to an internal processor of a memory device, the internal processor operating on an indicated bank of the memory device during the timeslot and the host processor not accessing the indicated bank during the timeslot.
摘要翻译：存储设备包括至少两个存储数据的存储体和一个内部处理器。至少两个存储体可由主机处理器访问。内部处理器从主处理器接收时隙，并且在时隙期间处理来自存储器阵列的至少两个存储体中的指示的一个存储体的数据的一部分，而其余存储体在时隙期间对主处理器可用。一种操作具有存储数据的存储体的存储装置的方法包括：主机处理器向存储装置的内部处理器发出每个存储体时隙，所述内部处理器在时隙期间在存储装置的指定存储体上操作，并且主机处理器不访问在时间段内指定的银行。

4. 发明申请

WO2011007304A1 USING STORAGE CELLS TO PERFORM COMPUTATION 审中-公开
标题翻译：使用储存细胞进行计算
公开(公告)号：WO2011007304A1
公开(公告)日：2011-01-20
申请号：PCT/IB2010/053168
申请日：2010-07-11
申请人： ZIKBIT LTD. , AKERIB, Avidan , AGAM, Oren , EHRMAN, Eli , MEYASSED, Moshe
发明人： AKERIB, Avidan , AGAM, Oren , EHRMAN, Eli , MEYASSED, Moshe
IPC分类号： G06F13/00
CPC分类号： G11C29/34 , G11C15/043
摘要： An in-memory processor includes a memory array which stores data and an activation unit to activate at least two cells in a column of the memory array at generally the same time thereby to generate a Boolean function output of the data of the at least two cells. Another embodiment shows a content addressable memory (CAM) unit using memory array cells.
摘要翻译：存储器内处理器包括存储数据的存储器阵列和激活单元，用于在大致相同的时间激活存储器阵列的列中的至少两个单元，从而生成至少两个单元的数据的布尔函数输出。另一个实施例示出了使用存储器阵列单元的内容可寻址存储器（CAM）单元。

5. 发明申请

WO2010079450A2 SYSTEM, METHOD AND APPARATUS FOR MEMORY WITH SEMAPHORE CONTROLLED ACCESS OF COMPONENT RAM CELLS BY AN EXTERNAL COMPONENT 审中-公开
标题翻译：用外部元件控制分量RAM电池的存储器的系统，方法和装置
公开(公告)号：WO2010079450A2
公开(公告)日：2010-07-15
申请号：PCT/IB2010/050047
申请日：2010-01-07
申请人： ZIKBIT LTD. , AKERIB, Avidan , EHRMAN, Eli , MEIR, Josh , MEYASSED, Moshe , ALPERN, Yair , AGAM, Oren
发明人： AKERIB, Avidan , EHRMAN, Eli , MEIR, Josh , MEYASSED, Moshe , ALPERN, Yair , AGAM, Oren
IPC分类号： G11C15/00 , G11C7/00 , G06F12/02
CPC分类号： G11C15/00 , G06F9/3879 , G06F15/7821 , G11C7/1006 , G11C11/005
摘要： An integrated circuit device includes a semiconductor substrate, an array of random access memory (RAM) cells, which are arranged on the substrate in first columns and are configured to store data, a computational section including associative memory cells, which are arranged on the substrate in second columns, which are in communication with the respective first columns so as to receive the data from the array of the RAM cells and to perform an associative computation on the data, and a semaphore to control an access of an external component to at least a portion of the array of RAM cells.
摘要翻译：一种集成电路装置，包括半导体衬底，随机存取存储器（RAM）单元阵列，其布置在第一列中的衬底上并被配置为存储数据;计算部分，包括相关存储器单元，其布置在衬底上在第二列中，它们与相应的第一列通信，以便从RAM单元的阵列接收数据，并且对该数据执行关联计算，以及信号量，至少控制外部组件的访问 RAM单元阵列的一部分。

6. 发明申请

WO2010079449A1 SYSTEM, METHOD AND APPARATUS FOR MEMORY WITH GENERALLY SIMULTANEOUS ACCESS OF RAM CELLS BY EMBEDDED COMPUTATIONAL SECTION AND AN EXTERNAL COMPONENT 审中-公开
标题翻译：通过嵌入式计算部分和外部组件通常同时访问RAM电池的存储器的系统，方法和装置
公开(公告)号：WO2010079449A1
公开(公告)日：2010-07-15
申请号：PCT/IB2010/050046
申请日：2010-01-07
申请人： ZIKBIT LTD. , AKERIB, Avidan , EHRMAN, Eli , MEIR, Josh , MEYASSED, Moshe , ALPERN, Yair , AGAM, Oren
发明人： AKERIB, Avidan , EHRMAN, Eli , MEIR, Josh , MEYASSED, Moshe , ALPERN, Yair , AGAM, Oren
IPC分类号： G06F13/00
CPC分类号： G11C15/00 , G06F9/3879 , G06F15/7821 , G11C7/1006 , G11C11/005
摘要： An integrated circuit device including a semiconductor substrate, an array of random access memory (RAM) cells arranged on the substrate in first columns and configured to store data, a computational section to receive the data from the RAM cell array, and interfacing circuitry that enables generally simultaneous accesses to the RAM cell array at least by an external component and by the computational section, additionally a method for computing, including accepting and executing at least one command from a host processor to a memory device, the command including a write command to store data at a specified address in an array of random access memory cells formed on a semiconductor substrate in the memory device, responsively to the command, transferring the data into a computational section of the memory device, and performing generally simultaneous accesses to different RAM cells at least by an external component and the computational section.
摘要翻译：一种集成电路装置，包括半导体衬底，布置在第一列中的衬底上并被配置为存储数据的随机存取存储器（RAM）单元阵列，用于从RAM单元阵列接收数据的计算部分，以及使能通常至少由外部组件和计算部分同时访问RAM单元阵列，另外还包括一种用于计算的方法，包括从主机处理器接收并执行至少一个命令到存储器件，该命令包括写入命令将数据存储在形成在存储器件中的半导体衬底上的随机存取存储器单元的阵列中的指定地址处，响应于命令将数据传送到存储器件的计算部分，并且对不同的RAM单元进行大致同时的访问至少由外部组件和计算部分组成。

7. 发明申请

WO2010079448A2 SYSTEM, METHOD AND APPARATUS FOR MEMORY WITH CONTROL LOGIC TO CONTROL ASSOCIATIVE COMPUTATIONS 审中-公开
标题翻译：具有控制逻辑的存储器的系统，方法和装置来控制相关计算
公开(公告)号：WO2010079448A2
公开(公告)日：2010-07-15
申请号：PCT/IB2010/050045
申请日：2010-01-07
申请人： ZIKBIT LTD. , AKERIB, Avidan , EHRMAN, Eli , MEIR, Josh , MEYASSED, Moshe , ALPERN, Yair , AGAM, Oren
发明人： AKERIB, Avidan , EHRMAN, Eli , MEIR, Josh , MEYASSED, Moshe , ALPERN, Yair , AGAM, Oren
IPC分类号： G11C15/00 , G11C7/00 , G06F12/02
CPC分类号： G11C15/00 , G06F9/3879 , G06F15/7821 , G11C7/1006 , G11C11/005
摘要： An integrated circuit device includes a semiconductor substrate, an array of random access memory (RAM) cells, which are arranged on the substrate in first columns and are configured to store data, a computational section including associative memory cells, which are arranged on the substrate in second columns, which are in communication with the respective first columns so as to receive the data from the array of the RAM cells and to perform an associative computation on the data, and control logic to control the associative computation.
摘要翻译：一种集成电路装置，包括半导体衬底，随机存取存储器（RAM）单元阵列，其布置在第一列中的衬底上并被配置为存储数据;计算部分，包括相关存储器单元，其布置在衬底上在第二列中，它们与各自的第一列通信，以便从RAM单元的阵列接收数据，并且对数据执行关联计算，以及控制逻辑来控制关联计算。

8. 发明申请

WO2004077335A3 MULTI-PROTOCOL MEMORY CARD 审中-公开
标题翻译：多协议记忆卡
公开(公告)号：WO2004077335A3
公开(公告)日：2005-03-17
申请号：PCT/IL2004000190
申请日：2004-02-25
申请人： INFINEON TECHNOLOGIES FLASH , KRYGIER MARCELO , MEYASSED MOSHE , AMIR ELAD
发明人： KRYGIER MARCELO , MEYASSED MOSHE , AMIR ELAD
IPC分类号： G06K7/00 , G06K19/07 , G06K19/06
CPC分类号： G06K19/07732 , G06K7/0008 , G06K7/10297 , G06K19/07 , G06K19/0719 , G06K19/07733 , G06K19/07741 , G06Q20/341 , G06Q20/3576 , G07F7/1008
摘要： According to some embodiments of the present invention, a multi-protocol non-volatile memory ("NVM") card may include a NVM array, at least two protocol units, and a controller adapted to provide an external application access to the NVM array with the use of one of the protocol units. The controller or control logic may select which protocol unit to use based on a signal or other indicator of the protocol used by the external application. According to some embodiments of the present invention, a method of operating a multi-protocol memory card may include switching between a first and a second protocol or mode of the card based on a signal from an application attempting to access to the NVM card.
摘要翻译：根据本发明的一些实施例，多协议非易失性存储器（“NVM”）卡可以包括NVM阵列，至少两个协议单元，以及适于向NVM阵列提供对NVM阵列的外部应用访问的控制器，使用协议单位之一。控制器或控制逻辑可以基于由外部应用使用的协议的信号或其他指示符来选择要使用的协议单元。根据本发明的一些实施例，操作多协议存储卡的方法可以包括基于来自尝试访问NVM卡的应用的信号在卡的第一和第二协议或模式之间进行切换。

9. 发明申请

WO2011048572A2 AN IN-MEMORY PROCESSOR 审中-公开
标题翻译：内存处理器
公开(公告)号：WO2011048572A2
公开(公告)日：2011-04-28
申请号：PCT/IB2010/054780
申请日：2010-10-21
申请人： ZIKBIT LTD. , AGAM, Oren , MEYASSED, Moshe , FUKUZO, Yukio
发明人： AGAM, Oren , MEYASSED, Moshe , FUKUZO, Yukio
IPC分类号： H01L27/108
CPC分类号： G11C7/1006
摘要： A memory device includes at least two memory banks storing data and an internal processor. The at least two memory banks are accessible by a host processor. The internal processor receives a timeslot from the host processor and processes a portion of the data from an indicated one of the at least two banks of the memory array during the timeslot while the remaining banks are available to the host processor during the timeslot. A method of operating a memory device having banks storing data includes a host processor issuing per bank timeslots to an internal processor of a memory device, the internal processor operating on an indicated bank of the memory device during the timeslot and the host processor not accessing the indicated bank during the timeslot.
摘要翻译：存储器件包括至少两个存储数据的存储体和内部处理器。至少两个存储体可由主处理器访问。内部处理器从主机处理器接收时隙，并且在时隙期间处理来自存储器阵列的至少两个存储体组中指定的一个的数据的一部分，而在时隙期间剩余的存储体可用于主机处理器。一种操作具有存储数据的存储器的存储器件的方法包括：主处理器，每个存储体时隙向存储器件的内部处理器发出，所述内部处理器在时隙期间在存储器件的指示库上操作，并且主机处理器不访问存储器在时间段内指定银行。

10. 发明申请

WO2010079450A3 SYSTEM, METHOD AND APPARATUS FOR MEMORY WITH SEMAPHORE CONTROLLED ACCESS OF COMPONENT RAM CELLS BY AN EXTERNAL COMPONENT 审中-公开
标题翻译：用于利用外部组件对SEMAPHORE控制存取组件RAM存储器的系统，方法和装置
公开(公告)号：WO2010079450A3
公开(公告)日：2010-09-02
申请号：PCT/IB2010050047
申请日：2010-01-07
申请人： ZIKBIT LTD , AKERIB AVIDAN , EHRMAN ELI , MEIR JOSH , MEYASSED MOSHE , ALPERN YAIR , AGAM OREN
发明人： AKERIB AVIDAN , EHRMAN ELI , MEIR JOSH , MEYASSED MOSHE , ALPERN YAIR , AGAM OREN
IPC分类号： G06F13/00
CPC分类号： G11C15/00 , G06F9/3879 , G06F15/7821 , G11C7/1006 , G11C11/005
摘要： An integrated circuit device includes a semiconductor substrate, an array of random access memory (RAM) cells, which are arranged on the substrate in first columns and are configured to store data, a computational section including associative memory cells, which are arranged on the substrate in second columns, which are in communication with the respective first columns so as to receive the data from the array of the RAM cells and to perform an associative computation on the data, and a semaphore to control an access of an external component to at least a portion of the array of RAM cells.
摘要翻译：一种集成电路器件包括半导体衬底，在第一列中布置在衬底上并且被配置为存储数据的随机存取存储器（RAM）单元的阵列，包括关联存储器单元的计算部分，其被布置在衬底上在与相应的第一列通信以便接收来自RAM单元阵列的数据并且对数据执行关联计算的第二列中，以及用于至少控制外部组件的访问的信号灯 RAM单元阵列的一部分。

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