专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

WO1983001705A1 PORTABLE DATA PROCESSING AND STORAGE SYSTEM 审中-公开
标题翻译：便携式数据处理和存储系统
公开(公告)号：WO1983001705A1
公开(公告)日：1983-05-11
申请号：PCT/GB1982000311
申请日：1982-11-01
申请人： KRAMER, Kane, Nicholas , CAMPBELL, James, Sebastian
IPC分类号： G11C07/00
CPC分类号： G11C19/0875 , G10H1/0033 , G10H2250/591 , G11C7/16 , G11C2207/16
摘要： A credit card size portable system comprises (a) a memory (22) for storage serially of digital data, especially of sound analogue signal which has been digitally encoded, (b) decoder means (26) for converting the memory output into analogue form, preferably several decoders each for one sound band, (c) a control register (34) for controlling input and output of data from the memory (22) and which is responsive to control data present in the input and ouput stream, and input (14) and output (15) for data entering and leaving the card system. Memory (a) can be of magnetic bubbles, of 8 megabyte size, which records 3 1/2 minutes of music. A card is readily programmed with the digital data and can be stored or transported for replay of sound signal as desired, in place of conventional discs or cassettes. The control data bits are detected by the control register and serve to control the recording and reply steps. The digital data may be replayed directly from the memory without passing through the decoders, for input into another memory upon command from the control register. A replay unit includes a controller and decoders, for producing analogue data for sound reproduction.
摘要翻译：信用卡尺寸便携式系统包括：（a）用于数字数据的串行存储的存储器，特别是已被数字编码的声音模拟信号，（b）用于将存储器输出转换为模拟形式的解码器装置，优选地，每个用于一个声带的几个解码器，（c）用于控制来自存储器（22）的数据的输入和输出并且响应于输入和输出流中存在的控制数据的控制寄存器（34）和输入（14））和用于进入和离开卡系统的数据的输出（15）。内存（a）可以是8兆字节大小的磁性气泡，记录3 1/2分钟的音乐。卡可以容易地用数字数据编程，并且可以根据需要存储或传输以重放声音信号，代替常规的盘或盒。控制数据位由控制寄存器检测，用于控制记录和回复步骤。可以直接从存储器重放数字数据而不通过解码器，以便根据来自控制寄存器的命令输入到另一个存储器。重放单元包括用于产生用于声音再现的模拟数据的控制器和解码器。

2. 发明申请

WO1982001958A1 DATA REWRITING SYSTEM FOR BUBBLE MEMORY 审中-公开
标题翻译：泡泡记忆体数据刷新系统
公开(公告)号：WO1982001958A1
公开(公告)日：1982-06-10
申请号：PCT/JP1981000340
申请日：1981-11-18
申请人： FUJITSU FANUC LTD , KINOSHITA MITSUO
发明人： FUJITSU FANUC LTD
IPC分类号： G11C11/14
CPC分类号： G11C19/0875 , G05B19/406 , G06F11/1435 , G11C19/08
摘要： Systeme de reecriture d'informations ecrivant des informations specifiques dans l'enregistrement final (Bn) de la premiere adresse de memoire d'informations (102a) d'une memoire a bulles, representant l'invalidation des informations dans la premiere adresse de memoire (102a) de la memoire a bulles (102) de maniere a maintenir la simultaneite des informations pendant la reecriture des informations dans la memoire a bulles meme si le courant electrique est interrompu, et la reecriture de nouvelles informations de maniere sequentielle dans l'enregistrement de tete (B1) sur l'enregistrement final (Bn) de la premiere adresse de memoire (102a) sous la commande d'un controleur a bulles. Ce systeme de reecriture d'informations efface aussi les informations specifiques apres avoir termine la reecriture dans la premiere adresse de memoire (102a) puis ecrit les nouvelles informations ecrites dans la premiere adresse de memoire (102a) de nouveau dans l'enregistrement de tete (A1) sur l'enregistrement final (An) de la seconde adresse d'enregistrement d'informations (102a).

3. 发明申请

WO2015171620A1 PHYSICALLY UNCLONABLE FUNCTION BASED ON DOMAIN WALL MEMORY AND METHOD OF USE 审中-公开
标题翻译：基于域墙存储器的物理不可靠函数及其使用方法
公开(公告)号：WO2015171620A1
公开(公告)日：2015-11-12
申请号：PCT/US2015/029255
申请日：2015-05-05
申请人： UNIVERSITY OF SOUTH FLORIDA , GHOSH, Swaroop , IYENGAR, Anirudh Srikant , RAMCLAM, Kenneth
发明人： GHOSH, Swaroop , IYENGAR, Anirudh Srikant , RAMCLAM, Kenneth
IPC分类号： G11C11/16
CPC分类号： G11C19/0866 , B82Y10/00 , G11C11/1655 , G11C11/1657 , G11C11/1659 , G11C11/1673 , G11C11/1675 , G11C11/1693 , G11C19/0841 , G11C19/0875
摘要： A system and method for providing a physically unclonable function (PFU) is described. In operation, the method includes applying a domain wall shift pulse challenge to a plurality of nanowires of a domain wall memory (DWM) array, wherein the nanowires of the domain wall memory (DWM) array have process induced variations, resulting in pinning potentials which affect the velocity of the domain walls along the length of the nanowires. Following the application of the domain wall shift pulse, the response to the challenge is determined by measuring the response of the plurality of nanowires of the domain wall memory to the applied domain wall shift pulse challenge to provide a physically unclonable function (PUF) for the integrated circuit.
摘要翻译：描述了用于提供物理不可克隆功能（PFU）的系统和方法。在操作中，该方法包括对域壁存储器（DWM）阵列的多个纳米线应用域壁移位脉冲挑战，其中域壁存储器（DWM）阵列的纳米线具有处理引起的变化，导致固定电位，影响沿着纳米线长度的畴壁的速度。在应用域壁移位脉冲之后，通过测量域壁存储器的多个纳米线对所应用的域壁移位脉冲挑战的响应来确定对挑战的响应，以提供用于所述域壁移位脉冲的物理不可克隆功能（PUF）集成电路。

4. 发明申请

WO2013054098A1 METHOD OF PINNING DOMAIN WALLS IN A NANOWIRE MAGNETIC MEMORY DEVICE 审中-公开
标题翻译：在纳米磁记忆体装置中引导域网的方法
公开(公告)号：WO2013054098A1
公开(公告)日：2013-04-18
申请号：PCT/GB2012/052493
申请日：2012-10-08
申请人： UNIVERSITY OF YORK
发明人： O'GRADY, Kevin , VALLEJO FERNANDEZ, Gonzalo , HIROHATA, Atsufumi
IPC分类号： G11C19/08 , G11C11/14
CPC分类号： G11C11/1675 , G11C11/14 , G11C11/161 , G11C14/0081 , G11C19/02 , G11C19/0808 , G11C19/0833 , G11C19/085 , G11C19/0875 , H01L43/02 , H01L43/10 , H04L43/02 , H04L43/10
摘要： There is provided a method of pinning domain walls in a magnetic memory device (10) comprising using an antiferromagnetic material to create domain wall pinning sites. Junctions (22) where arrays of ferromagnetic nanowires (16) and antiferromagnetic nanowires (20) cross exhibit a permanent exchange bias interaction between the ferromagnetic material and the antiferromagnetic material which creates domain wall pinning sites. The exchange bias field is between 30 to 3600Oe and the anisotropy direction of the ferromagnetic elements is between 15 to 75° to an anisotropy direction of the antiferromagnetic elements.
摘要翻译：提供了一种在磁存储器装置（10）中钉扎畴壁的方法，包括使用反铁磁材料来产生畴壁钉扎位置。铁磁性纳米线（16）和反铁磁性纳米线（20）交叉排列的结（22）在铁磁材料和反铁磁材料之间呈现永久的交换偏压相互作用，产生畴壁钉扎位置。交换偏压场在30至3600Oe之间，铁磁元件的各向异性方向与反铁磁性元件的各向异性方向成15至75°。

5. 发明申请

WO1985000244A1 BUBBLE MEMORY WHICH TRANSFERS BUBBLES IN BOTH RIGHT-TO-LEFT AND LEFT-TO-RIGHT SPS LOOPS TO PROVIDE A SHORT ACCESS TIME 审中-公开
标题翻译：在双向向右和向右移动SPS插座的泡沫转移泡沫存储器以提供短时间访问时间
公开(公告)号：WO1985000244A1
公开(公告)日：1985-01-17
申请号：PCT/US1984000995
申请日：1984-06-27
申请人： BURROUGHS CORPORATION
发明人： BURROUGHS CORPORATION , SCHWARTZ, Sidney, J. (deceased)
IPC分类号： G11C19/08
CPC分类号： G11C19/0866 , G11C19/0875
摘要： A bubble memory comprises a substrate (30) with a major surface; a first storage loop (31) for storing bubbles on the left side of the surface having parallel inputs and parallel outputs; a second storage loop (32) for storing bubbles on the right side of the surface having parallel inputs and parallel outputs; a first input generator (33) on the left side of the surface including a serial-parallel track (34) along which the bubbles move to the right to enter the parallel inputs of the first storage loop; a second input generator (35) on the right side of the surface including a serial-parallel track (36) along which the bubbles move to the left to enter the parallel inputs of the second storage loop; a detector (38) for detecting bubbles disposed equally on the left side and the right side of the surface; a first output mechanism (37) on the left side of the surface including a parallel-serial track which receives bubbles from the parallel outputs of the first storage loop and moves them to the right to the detector; and a second output mechanism (39) on the right side of the surface including a parallel-serial track which receives bubbles from the parallel outputs of the second storage loop and moves them to the left to the detector.

6. 发明申请

WO1981001768A1 REDUNDANT MAGNETIC DOMAIN MEMORY USING PARTY 审中-公开
标题翻译：使用方的冗余磁性记忆体
公开(公告)号：WO1981001768A1
公开(公告)日：1981-06-25
申请号：PCT/US1980001664
申请日：1980-12-09
申请人： NCR CORP
发明人： NCR CORP , ELLSWORTH W
IPC分类号： G11C19/08
CPC分类号： G11C29/86 , G06F11/1032 , G11C19/0875
摘要： A magnetic bubble domain memory device that includes a magnetic domain data chip having a major-minor (20, 26) loop organization with on-chip firmware providing redundancy information enabling the use of the chip even though one or more defective minor loops may be present thereon. One of the pages (68) is written in the minor loop (26), where a page is defined as a common bit position in each of the plurality of minor loops, with a series of magnetic domains having an odd total number. The next succeeding page (70) in the minor loops contains a series of magnetic domains and voids which are representative of the loop numbers of defective minor loops on the chip with the remaining pages (72) in the minor loop having an even number of magnetic domains contained in each of the pages. Collectively, the pages containing the odd and even number of magnetic domains together with the page containing the map of the defective minor loops comprise the on-chip firmware providing redundancy information. This magnetic domain structure is capable of screening out defective minor loops in the read and write operation, and enables synchronization of the magnetic domain device such that a selected page of data may be readily accessed from a plurality of minor loops when desired.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式