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1. 发明申请

WO1981003571A1 MEMORY ARRAY HAVING IMPROVED ISOLATION BETWEEN SENSE LINES 审中-公开
标题翻译：记忆阵列具有改善的感知线之间的隔离
公开(公告)号：WO1981003571A1
公开(公告)日：1981-12-10
申请号：PCT/US1981000607
申请日：1981-05-04
申请人： MOTOROLA INC
发明人： MOTOROLA INC , DONOGHUE W
IPC分类号： G11C07/02
CPC分类号： G11C7/18 , G11C17/126
摘要： A memory array having improved isolation between the bit sense common lines (22, 23, 26, 27) is provided by using diode connected transistors (40-43). The diode connected transistors (40-43) substantially eliminate any current flow between bit sense common lines (22, 23, 26, 27) when a certain portion of the column select circuitry has not been selected. Since the blocking transistors (40-43) prevent current flow there is no noise generated to be coupled to one of the control lines (28). This results in a memory array which can operate at higher speeds since better differential signals are established to be sensed by the sense amplifier.

2. 发明申请

WO1995033266A1 FLAT-CELL ROM AND DECODER 审中-公开
标题翻译：平板ROM和解码器
公开(公告)号：WO1995033266A1
公开(公告)日：1995-12-07
申请号：PCT/US1995006624
申请日：1995-05-24
申请人： APLUS INTEGRATED CIRCUITS, INC.
发明人： APLUS INTEGRATED CIRCUITS, INC. , LEE, Peter, W.
IPC分类号： G11C17/00
CPC分类号： G11C17/126
摘要： A flat-cell ROM array (10) comprises a bank of field effect transistors, each having a source, drain and gate, formed by ion implantation between columns (54a-i) of buried N+ and under rows of polysilicon (56), wherein adjacent columns of buried N+ are the source and drain of at least one transistor and a corresponding row of polysilicon is the gate of the transistor. Each of these transistors is programmed to have one of a plurality of threshold voltages depending on a desired storage value. Attached to the bank of transistors is an upper selector network (14) associated with the bank connected to a first class of alternating sets of the columns, and a lower selector network (16) associated with the bank connected to a second class of alternating sets of the columns. A method provides steps for performing the present invention.
摘要翻译：平板单元ROM阵列（10）包括一组场效应晶体管，每一个具有源极，漏极和栅极，通过在掩埋N +的列（54a-i）和多晶硅行（56）之间的离子注入形成，其中埋入N +的相邻列是至少一个晶体管的源极和漏极，并且相应的多晶硅行是晶体管的栅极。根据期望的存储值，将这些晶体管中的每一个编程为具有多个阈值电压中的一个。连接到晶体管组的是与连接到第一类交替的列的组相关联的上选择器网络（14），以及与连接到第二类交替集合的组相关联的下选择器网络（16）的列。一种方法提供了执行本发明的步骤。

3. 发明申请

WO1994000846A1 DATA READ METHOD AND READ ONLY MEMORY CIRCUIT 审中-公开
标题翻译：数据读取方法和只读存储器电路
公开(公告)号：WO1994000846A1
公开(公告)日：1994-01-06
申请号：PCT/JP1993000882
申请日：1993-06-28
申请人： OKI ELECTRIC INDUSTRY CO., LTD. , HARADA, Teruhiro
发明人： OKI ELECTRIC INDUSTRY CO., LTD.
IPC分类号： G11C16/06
CPC分类号： G11C17/126 , G11C16/26
摘要： A given column line and a bit line adjacent to it are selected from a plurality of string lines (102-1 to 102-3) and bit lines (101-1 to 101-2) by the string selection signals (Y1 to Y3); and a given row line is selected from a plurality of row lines (103-1 to 103-n) by the row selection signals (X0 to Xn). The data stored in the memory cells (104-01 to 104-n4) which are connected to the selected column line and row line are read out on the selected bit line. The selected column line is made to be at a first potential level (the potential level supplied from a constant-voltage circuit (160)). Substantially at the same time, the selected bit line is made to be at a second potential level (the potential level provided by a sense amplifying circuit (150)) which is lower than the first potential. The column lines which are not selected are made to be at a third potential level (the ground potential level or the potential level provided by a potential supply circuit (190)) which is lower than the second potential level. Then, the data are read out. Therefore, it is possible to read the data at a high speed, and further, to materialize a low power consumption because no reactive current flows.
摘要翻译：通过串选择信号（Y1至Y3）从多个串行（102-1至102-3）和位线（101-1至101-2）中选择给定列线和与其相邻的位线， ; 并且通过行选择信号（X0至Xn）从多条行线（103-1至103-n）中选择给定的行线。存储在存储单元（104-01至104-n4）中的与选择的列线和行线连接的数据在所选位线上被读出。所选列线被制成处于第一电位电平（从恒压电路（160）提供的电位电平）。基本上同时，使所选择的位线处于低于第一电位的第二电位电平（由感测放大电路（150）提供的电位电平）。未选择的列线被制成低于第二电位电平的第三电位电平（由电位供给电路（190）提供的接地电位或电位电平）。然后，读出数据。因此，可以高速地读取数据，并且进一步在没有无功电流的情况下实现低功耗。

4. 发明申请

WO1995000954A1 A GROUNDED MEMORY CORE FOR ROMS, EPROMS, AND EEPROMS 审中-公开
标题翻译：一个接地的存储器核心的环境，EPROMS和EEPROMS
公开(公告)号：WO1995000954A1
公开(公告)日：1995-01-05
申请号：PCT/US1994007317
申请日：1994-06-27
申请人： CREATIVE INTEGRATED SYSTEMS, INC.
发明人： CREATIVE INTEGRATED SYSTEMS, INC. , KOMAREK, James, A. , PADGETT, Clarence, W. , AMNEUS, Robert, D. , TANNER, Scott, B.
IPC分类号： G11C17/00
CPC分类号： G11C7/1057 , G11C7/062 , G11C7/065 , G11C7/1051 , G11C7/106 , G11C7/12 , G11C7/22 , G11C8/06 , G11C8/10 , G11C8/18 , G11C16/0491 , G11C16/24 , G11C16/28 , G11C17/12 , G11C17/126 , G11C2207/108 , H01L27/115 , H03K3/3565
摘要： The invention is an improved bank select read only memory in which the bit lines (mBL) and virtual ground lines (VGLs) are all precharged to ground (GND) instead of being precharged to an internal low supply voltage. Both of the two virtual ground lines (VGLs) are selected for the selected bit and both the selected virtual ground lines are driven to ground during the precharge phase. At the top of the memory array, all virtual ground lines (VGLs) in the memory array are precharge to ground during the precharge phase. Next, during the sensing phase, the operation of the two virtual ground lines for the selected bit is changed to selectively hold one virtual ground line (VGL1) at ground and switch the second virtual ground line (VGL2) to a positive voltage. All bit lines (mBL) are precharged to ground during the precharge phase. In the following sensing phase, the selected bit line is driven positive by the selected memory core FET if it is programmed with a low threshold voltage. If the selected memory core FET is programmed with a high threshold voltage, the bit line remains floating at the ground level, or it may be held at ground by means of the second virtual ground line, which is held at ground, and by low threshold core FETs, adjacent to the selected core FET, which are connected to the selected word line (WLn).
摘要翻译：本发明是一种改进的存储体选择只读存储器，其中位线（mBL）和虚拟接地线（VGL）都被预充电到地（GND），而不是预充电到内部低电源电压。对于所选择的位选择两个虚拟接地线（VGL），并且在预充电阶段期间所选择的虚拟接地线都被驱动到地。在存储器阵列的顶部，存储器阵列中的所有虚拟接地线（VGL）在预充电阶段期间预充电到地。接下来，在感测阶段期间，改变所选位的两个虚拟接地线的操作，以选择性地将一个虚拟接地线（VGL1）保持在地，并将第二虚拟接地线（VGL2）切换到正电压。所有位线（mBL）在预充电阶段都被预充电到地。在下一个感测阶段，如果所选择的位线被编程为低阈值电压，则所选择的位线被所选择的存储器芯FET驱动为正。如果所选择的存储核心FET被编程为具有高阈值电压，则位线保持在地电平浮动，或者它可以通过保持在地的第二虚拟接地线保持在地，并且通过低阈值与所选择的核心FET相邻的核心FET，其连接到所选择的字线（WLn）。

5. 发明申请

WO1994018677A1 IMPROVEMENTS IN A VERY LARGE SCALE INTEGRATED PLANAR READ ONLY MEMORY 审中-公开
标题翻译：在非常大的规模集成平面中的改进只读存储器
公开(公告)号：WO1994018677A1
公开(公告)日：1994-08-18
申请号：PCT/US1994001538
申请日：1994-02-10
申请人： CREATIVE INTERGRATED SYSTEMS, INC.
发明人： CREATIVE INTERGRATED SYSTEMS, INC. , KOMAREK, James, A. , PADGETT, Clarence, W. , TANNER, Scott, B. , MINNEY, Jack, L.
IPC分类号： G11C07/00
CPC分类号： G11C7/1057 , G11C7/04 , G11C7/062 , G11C7/065 , G11C7/1051 , G11C7/106 , G11C7/12 , G11C7/22 , G11C8/06 , G11C8/10 , G11C8/18 , G11C17/12 , G11C17/126 , G11C2207/108 , H01L27/115 , H03K3/3565
摘要： A very large scale, read-only memory which is read by selectively discharging bit lines (30(i)) and virtual ground lines (32(i)) is read at subtantially higher speeds by precharging the bit lines and virtual ground lines of memory core (10) at both the top and bottom of the memory core at opposing ends of bit lines and virtual ground lines. The memory core is precharged using a precharge decoder (28) which provides upper and lower address precharging signals timed on sequential clocks. The precharge decoder is selected to precharge sectors of the memory core by the address signals of the memory core. A precharge decoder is provided for each sector of the memory core so that the entire memory core is precharged in this manner.
摘要翻译：通过对位线（30（i））和虚拟接地线（32（i））进行选择性地放电读取的非常大规模的只读存储器通过预先充电存储器的位线和虚拟接地线而以较小的速度被读取在位线和虚拟接地线的相对端处的存储器芯的顶部和底部处的芯（10）。使用预充电解码器（28）对存储器芯进行预充电，该预充电解码器（28）提供在顺序时钟上定时的上部和下部地址预充电信号。选择预充电解码器以通过存储器核心的地址信号对存储器核心的扇区进行预充电。为存储器芯的每个扇区提供预充电解码器，使得整个存储器芯以这种方式被预充电。

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