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1. 发明申请

WO1996005655A1 IMPROVEMENTS IN A VLSI MEMORY CIRCUIT 审中-公开
标题翻译： VLSI存储器电路中的改进
公开(公告)号：WO1996005655A1
公开(公告)日：1996-02-22
申请号：PCT/US1995010397
申请日：1995-08-14
申请人： CREATIVE INTEGRATED SYSTEMS, INC. , RICOH COMPANY, LTD.
发明人： CREATIVE INTEGRATED SYSTEMS, INC. , RICOH COMPANY, LTD. , KOMAREK, James, A. , PADGETT, Clarence, W. , MINNEY, Jack, L. , TANNER, Scott, B. , KOJIMA, Shin-ichi , OISHI, Motohiro , FUKUMURA, Keiji , NAKANISHI, Hiroaki
IPC分类号： H03K17/16
CPC分类号： G11C7/1057 , G11C7/1051 , G11C7/106 , G11C7/12 , G11C7/22 , G11C8/06 , G11C8/18
摘要： The rate of increase or decrease of the rising and falling edge respectively of an output driver in a read-only memory circuit is provided by driving a CMOS output amplifier by gate control signals whose rate of increase or decrease in turn is controlled by a control signal, SLOW. The signal SLOW is generated based upon the speed of operation of the ROM and is binary, one state being indicative of normal speed of operation and a second state being indicative of a slow speed of operation of the ROM. When the signal SLOW is high, the rate at which complementary gate drive signals are applied to the CMOS amplifier are generated at a first or normal rate. However, when the signal SLOW is low, the rate of generation of these gate drive signals is also decreased to correspondingly decrease the switching speed of the CMOS amplifier. A voltage precharge signal VPC is also applied to the rate controlling circuit so that variations in the precharge voltage indicative of manufacturing parameters, voltage variations and temperature variations directly effect the rate at which the gate drive signals are generated and hence the switching speeds of the CMOS amplifier.
摘要翻译：只读存储器电路中的输出驱动器的上升沿和下降沿的增加或减小的速率通过由控制信号控制的栅极控制信号驱动CMOS输出放大器来提供，，慢。基于ROM的操作速度产生信号SLOW，是二进制的，一个状态表示正常的操作速度，第二个状态指示ROM的低速操作。当信号SLOW为高时，互补栅极驱动信号施加到CMOS放大器的速率以第一或正常速率产生。然而，当信号SLOW为低电平时，这些栅极驱动信号的产生速率也降低，以相应地降低CMOS放大器的开关速度。电压预充电信号VPC也被施加到速率控制电路，使得指示制造参数，电压变化和温度变化的预充电电压的变化直接影响产生栅极驱动信号的速率，因此CMOS的开关速度放大器。

2. 发明申请

WO1995000954A1 A GROUNDED MEMORY CORE FOR ROMS, EPROMS, AND EEPROMS 审中-公开
标题翻译：一个接地的存储器核心的环境，EPROMS和EEPROMS
公开(公告)号：WO1995000954A1
公开(公告)日：1995-01-05
申请号：PCT/US1994007317
申请日：1994-06-27
申请人： CREATIVE INTEGRATED SYSTEMS, INC.
发明人： CREATIVE INTEGRATED SYSTEMS, INC. , KOMAREK, James, A. , PADGETT, Clarence, W. , AMNEUS, Robert, D. , TANNER, Scott, B.
IPC分类号： G11C17/00
CPC分类号： G11C7/1057 , G11C7/062 , G11C7/065 , G11C7/1051 , G11C7/106 , G11C7/12 , G11C7/22 , G11C8/06 , G11C8/10 , G11C8/18 , G11C16/0491 , G11C16/24 , G11C16/28 , G11C17/12 , G11C17/126 , G11C2207/108 , H01L27/115 , H03K3/3565
摘要： The invention is an improved bank select read only memory in which the bit lines (mBL) and virtual ground lines (VGLs) are all precharged to ground (GND) instead of being precharged to an internal low supply voltage. Both of the two virtual ground lines (VGLs) are selected for the selected bit and both the selected virtual ground lines are driven to ground during the precharge phase. At the top of the memory array, all virtual ground lines (VGLs) in the memory array are precharge to ground during the precharge phase. Next, during the sensing phase, the operation of the two virtual ground lines for the selected bit is changed to selectively hold one virtual ground line (VGL1) at ground and switch the second virtual ground line (VGL2) to a positive voltage. All bit lines (mBL) are precharged to ground during the precharge phase. In the following sensing phase, the selected bit line is driven positive by the selected memory core FET if it is programmed with a low threshold voltage. If the selected memory core FET is programmed with a high threshold voltage, the bit line remains floating at the ground level, or it may be held at ground by means of the second virtual ground line, which is held at ground, and by low threshold core FETs, adjacent to the selected core FET, which are connected to the selected word line (WLn).
摘要翻译：本发明是一种改进的存储体选择只读存储器，其中位线（mBL）和虚拟接地线（VGL）都被预充电到地（GND），而不是预充电到内部低电源电压。对于所选择的位选择两个虚拟接地线（VGL），并且在预充电阶段期间所选择的虚拟接地线都被驱动到地。在存储器阵列的顶部，存储器阵列中的所有虚拟接地线（VGL）在预充电阶段期间预充电到地。接下来，在感测阶段期间，改变所选位的两个虚拟接地线的操作，以选择性地将一个虚拟接地线（VGL1）保持在地，并将第二虚拟接地线（VGL2）切换到正电压。所有位线（mBL）在预充电阶段都被预充电到地。在下一个感测阶段，如果所选择的位线被编程为低阈值电压，则所选择的位线被所选择的存储器芯FET驱动为正。如果所选择的存储核心FET被编程为具有高阈值电压，则位线保持在地电平浮动，或者它可以通过保持在地的第二虚拟接地线保持在地，并且通过低阈值与所选择的核心FET相邻的核心FET，其连接到所选择的字线（WLn）。

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