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1. 发明申请

WO2016018212A1 MULTI-CORE PROCESSOR INCLUDING A MASTER CORE AND SLAVE CORES 审中-公开
标题翻译：多核处理器，包括主核和从机
公开(公告)号：WO2016018212A1
公开(公告)日：2016-02-04
申请号：PCT/US2014/048403
申请日：2014-07-28
申请人： HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
发明人： SPRAGUE, Fred A.
IPC分类号： G06F9/54
CPC分类号： G06F9/48 , G06F9/4856 , G06F9/545 , G06F15/8038 , G06F2209/483 , Y02D10/24 , Y02D10/32
摘要： A multi-core processor comprises a plurality of slave cores, the slave cores being without operating system kernel-related features, and the slave cores to execute respective instructions. A master core configures the operating system kernel-related features on behalf of the slave cores. The master core is to control usage of the operating system kernel-related features during execution of the instructions on the respective slave cores.
摘要翻译：多核处理器包括多个从核，从核不具有操作系统内核相关特征，并且从核执行相应的指令。主核心代表从核心配置与操作系统内核相关的功能。主核心是在执行相应从属核心指令的过程中控制操作系统内核相关特性的使用。

2. 发明申请

WO00022503A1 EFFICIENT COMPLEX MULTIPLICATION AND FAST FOURIER TRANSFORM (FFT) IMPLEMENTATION ON THE MANARRAY ARCHITECTURE 审中-公开
标题翻译： MANARRAY建筑的高效复用和快速傅立叶变换（FFT）实现
公开(公告)号：WO00022503A1
公开(公告)日：2000-04-20
申请号：PCT/US1999/023494
申请日：1999-10-08
IPC分类号： G06F9/38 , G06F9/30 , G06F15/16 , G06F15/173 , G06F15/80 , G06F17/14 , G06F17/16 , G06F7/50 , G06F7/52 , G06F17/10
CPC分类号： G06F15/82 , G06F9/30014 , G06F9/30032 , G06F9/30036 , G06F9/3853 , G06F9/3885 , G06F15/8023 , G06F15/8038 , G06F17/142
摘要： Efficient computation of complex multiplication results and very efficient fast Fourier transforms (FFTs) are provided. A parallel array VLIW digital signal processor (100) is employed along with specialized complex multiplication instructions and communication operations between the processing elements (101, 151, 153, 155) which are overlapped with computation to provide very high performance operation. Successive iterations of a loop of tightly packed VLIWs (100) are used allowing the complex multiplication pipeline hardware to be efficiently used. In addition, efficient techniques for supporting combined multiply accumulate operations are described.
摘要翻译：提供了复数乘法结果和非常有效的快速傅里叶变换（FFT）的有效计算。并行阵列VLIW数字信号处理器（100）与处理元件（101,151,153,155）之间的专门的复数乘法指令和通信操作一起使用，这些操作与计算重叠以提供非常高的性能操作。使用紧密压缩的VLIW（100）的循环的连续迭代，允许有效地使用复数乘法管线硬件。此外，描述了用于支持组合乘法累加操作的有效技术。

3. 发明申请

WO2016189294A1 SINGLE-CHIP MULTI-PROCESSOR COMMUNICATION 审中-公开
标题翻译：单芯片多处理器通信
公开(公告)号：WO2016189294A1
公开(公告)日：2016-12-01
申请号：PCT/GB2016/051489
申请日：2016-05-24
申请人： DISPLAYLINK (UK) LIMITED , CAWLEY, Robin Alexander , SKINNER, Colin , HAMAKER, Eric Kenneth
发明人： CAWLEY, Robin Alexander , SKINNER, Colin , HAMAKER, Eric Kenneth
IPC分类号： G06F15/173 , G06F13/24 , G06F9/38
CPC分类号： G06F15/8038 , G06F9/3877 , G06F13/24 , G06F13/4282 , G06F15/17337 , G06F2213/0042
摘要： A heterogeneous multi-core integrated circuit comprising two or more processors (21), at least one of the processors (21A) being a general purpose CPU and at least one of the processors (21B) being a specialized hardware processing engine, the processors (21) being connected by a processor local bus (22) on the integrated circuit, wherein the general purpose CPU (21A) is configured to generate a first instruction for an atomic operation to be performed by a second processor (21B), different from the general purpose CPU (21A), the first instruction comprising an address of the second processor (21B) and a first command indicating a first action to be executed by the second processor (21B), and transmit the first instruction to the second processor (21B) over the processor local bus (22). The first command may include the first action, or may be a descriptor of the first action or a pointer to where the first action may be found in a memory (23).
摘要翻译：包括两个或多个处理器（21）的异构多核集成电路，所述处理器（21A）中的至少一个是通用CPU，并且所述处理器（21B）中的至少一个是专用硬件处理引擎，所述处理器 21）通过集成电路上的处理器本地总线（22）连接，其中通用CPU（21A）被配置为生成用于由第二处理器（21B）执行的原子操作的第一指令，其不同于通用CPU（21A），包括第二处理器（21B）的地址的第一指令和指示要由第二处理器（21B）执行的第一动作的第一命令，并将第一指令发送到第二处理器（21B））处理器本地总线（22）。第一命令可以包括第一动作，或者可以是第一动作的描述符或指向可在存储器（23）中找到第一动作的指针。

4. 发明申请

WO2014081461A1 PROCESSING SYSTEM WITH INTERSPERSED PROCESSORS WITH MULTI-LAYER INTERCONNECT 审中-公开
标题翻译：具有多层互连的交互处理器的处理系统
公开(公告)号：WO2014081461A1
公开(公告)日：2014-05-30
申请号：PCT/US2013/034125
申请日：2013-03-27
申请人： COHERENT LOGIX, INCORPORATED
发明人： DOBBS, Carl, S. , TROCINO, Michael, R. , SOLKA, Michael, B.
IPC分类号： G06F13/40 , G06F15/163
CPC分类号： G06F9/546 , G06F9/44505 , G06F13/1673 , G06F13/28 , G06F13/4022 , G06F13/4027 , G06F13/4282 , G06F15/76 , G06F15/8038 , Y02D10/14 , Y02D10/151
摘要： Embodiments of a multi-processor array are disclosed that may include a plurality of processors and configurable communication elements coupled together in a interspersed arrangement. Each configurable communication element may include a local memory and a plurality of routing engines. The local memory may be coupled to a subset of the plurality of processors. Each routing engine may be configured to receive one or more messages from a plurality of sources, assign each received message to a given destination of a plurality of destinations dependent upon configuration information, and forward each message to assigned destination. The plurality of destinations may include the local memory, and routing engines included in a subset of the plurality of configurable communication elements.
摘要翻译：公开了一种多处理器阵列的实施例，其可以包括多个处理器和以散置的布置耦合在一起的可配置通信元件。每个可配置的通信元件可以包括本地存储器和多个路由引擎。本地存储器可以耦合到多个处理器的子集。每个路由引擎可以被配置为从多个源接收一个或多个消息，根据配置信息将每个接收到的消息分配给多个目的地的给定目的地，并将每个消息转发到分配的目的地。多个目的地可以包括本地存储器和包括在多个可配置通信元件的子集中的路由引擎。

5. 发明申请

WO2014081457A1 PROCESSING SYSTEM WITH INTERSPERSED PROCESSORS DMA-FIFO 审中-公开
标题翻译：具有交互处理器DMA-FIFO的处理系统
公开(公告)号：WO2014081457A1
公开(公告)日：2014-05-30
申请号：PCT/US2013/029915
申请日：2013-03-08
申请人： COHERENT LOGIX INCORPORATED
发明人： DOBBS, Carl , TROCINO, Michael , BINDLOSS, Keith
IPC分类号： G06F15/163 , G06F13/40 , G06F13/28
CPC分类号： G06F9/546 , G06F9/44505 , G06F13/1673 , G06F13/28 , G06F13/4022 , G06F13/4027 , G06F13/4282 , G06F15/76 , G06F15/8038 , Y02D10/14 , Y02D10/151
摘要： Embodiments of a multi-processor array are disclosed that may include a plurality of processors, local memories, configurable communication elements, and direct memory access (DMA) engines, and a DMA controller. Each processor may be coupled to one of the local memories, and the plurality of processors, local memories, and configurable communication elements may be coupled together in an interspersed arrangement. The DMA controller may be configured to control the operation of the plurality of DMA engines.
摘要翻译：公开了可以包括多个处理器，本地存储器，可配置通信元件和直接存储器访问（DMA）引擎以及DMA控制器的多处理器阵列的实施例。每个处理器可以耦合到本地存储器之一，并且多个处理器，本地存储器和可配置通信元件可以以散置的布置耦合在一起。 DMA控制器可以被配置为控制多个DMA引擎的操作。

6. 发明申请

WO1995016234A1 APPARATUS AND METHOD FOR SIGNAL PROCESSING 审中-公开
标题翻译：装置和信号处理方法
公开(公告)号：WO1995016234A1
公开(公告)日：1995-06-15
申请号：PCT/US1994014219
申请日：1994-12-09
申请人： ASP SOLUTIONS USA, INC. , AKERIB, Avidan
发明人： ASP SOLUTIONS USA, INC.
IPC分类号： G06F07/02
CPC分类号： G06T7/00 , G06F15/8023 , G06F15/8038 , G06K9/00986 , G06K9/4609
摘要： Associative signal processing apparatus for processing an incoming signal including a plurality of samples, the apparatus including a two-dimensional array of processors, each processor (20) including a multiplicity of content addressable memory cells (122), each sample of an incoming signal being processed by at least one of the processors, and a register array including at least one register operative to store responders arriving from the processors and to provide communication, within a single cycle, between non-adjacent processors.
摘要翻译：用于处理包括多个采样的输入信号的相关信号处理装置，所述装置包括二维处理器阵列，每个处理器（20）包括多个内容可寻址存储单元（122），每个采样的输入信号为由至少一个处理器处理的寄存器阵列和包括至少一个寄存器的寄存器阵列，该寄存器阵列用于存储从处理器到达的应答器，并且在单个周期内提供在非相邻处理器之间的通信。

7. 发明申请

WO2013108100A1 EXTERNAL AUXILIARY EXECUTION UNIT INTERFACE TO OFF-CHIP AUXILIARY EXECUTION UNIT 审中-公开
标题翻译：外部辅助执行单元接口切换辅助执行单元
公开(公告)号：WO2013108100A1
公开(公告)日：2013-07-25
申请号：PCT/IB2012/057453
申请日：2012-12-19
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , IBM UNITED KINGDOM LIMITED , IBM JAPAN LIMITED
发明人： MEJDRICH, Eric , SHEARER, Robert , SCHARDT, Paul , SWENSON, Corey, Virgil
IPC分类号： G06F9/38 , G06F17/50 , H01L21/82
CPC分类号： G06F9/3881 , G06F9/3877 , G06F15/7864 , G06F15/8038
摘要： An external Auxiliary Execution Unit (AXU) interface is provided between a processing core disposed in a first programmable chip and an off-chip AXU disposed in a second programmable chip to integrate the AXU with an issue unit, a fixed point execution unit, and optionally other functional units in the processing core. The external AXU interface enables the issue unit to issue instructions to the AXU in much the same manner as the issue unit would be able to issue instructions to an AXU that was disposed on the same chip. By doing so, the AXU on the second programmable chip can be designed, tested and verified independent of the processing core on the first programmable chip, thereby enabling a common processing core, which has been designed, tested, and verified, to be used in connection with multiple different AXU designs.
摘要翻译：在设置在第一可编程芯片中的处理核心和设置在第二可编程芯片中的芯片外AXU之间提供外部辅助执行单元（AXU）接口，以将AXU与发行单元，固定点执行单元以及可选地处理核心中的其他功能单元。外部AXU接口使发布单元能够以与发布单元能够向安置在同一芯片上的AXU发出指令的方式大致相同的方式向AXU发出指令。通过这样做，可以独立于第一可编程芯片上的处理核心设计，测试和验证第二可编程芯片上的AXU，从而使已经设计，测试和验证的公共处理核心被用于连接多个不同的AXU设计。

8. 发明申请

WO2004055688A1 SCALABLE PROCESSING NETWORK FOR SEARCHING AND ADDING IN A CONTENT ADDRESSABLE MEMORY 审中-公开
标题翻译：可扩展处理网络，用于搜索和添加内容可寻址存储器
公开(公告)号：WO2004055688A1
公开(公告)日：2004-07-01
申请号：PCT/GB2003/005532
申请日：2003-12-17
申请人： ASPEX TECHNOLOGY LIMITED , JALOWIECKI, Ian , WHITTAKER, Martin , LANCASTER, John , BOUGHTON, Donald
发明人： JALOWIECKI, Ian , WHITTAKER, Martin , LANCASTER, John , BOUGHTON, Donald
IPC分类号： G06F15/80
CPC分类号： G06F15/8038
摘要： An alternation network for use with a content addressable memory for implementing a divide and conquer algorithm is described. The alternation network comprises: a plurality of alternation modules connected in series together, each module comprising: a plurality of cascaded logic gates arranged to propagate a match parity signal via the gates along at least part of a matching result vector, the matching result vector being generated by execution of a matching instruction on the content addressable memory, and the logic gates being configured to change the parity of the match parity signal in accordance with the matching result vector; and a vector output arranged to output a parity level vector of the propagated match parity signal present at the each gate of the plurality of logic gates; a logic network for dividing the matching result vector into an odd match vector and an even match vector representing respectively odd and even numbered elements of the matching result vector, by use of the parity level vector; and means for writing a selected one of the odd and even match vectors to the content addressable memory.
摘要翻译：描述了用于实现分割和征服算法的内容可寻址存储器的交替网络。所述交替网络包括：串联连接的多个交替模块，每个模块包括：多个级联逻辑门，布置成沿着匹配结果向量的至少一部分经由所述门传播匹配奇偶校验信号，所述匹配结果向量为通过在内容可寻址存储器上执行匹配指令而产生，并且逻辑门被配置为根据匹配结果向量改变匹配奇偶校验信号的奇偶校验; 以及矢量输出，被布置为输出存在于所述多个逻辑门的每个门处的所传播的匹配奇偶校验信号的奇偶校验电平矢量; 用于通过使用奇偶校验电平矢量将匹配结果矢量划分为奇数匹配矢量和偶数匹配矢量，分别表示匹配结果向量的奇数和偶数编号元素的逻辑网络; 以及用于将奇数和偶数匹配矢量中选择的一个写入内容可寻址存储器的装置。

9. 发明申请

WO1996036920A1 ASSOCIATIVE NETWORK METHOD AND APPARATUS 审中-公开
标题翻译：相关网络方法和设备
公开(公告)号：WO1996036920A1
公开(公告)日：1996-11-21
申请号：PCT/US1996006450
申请日：1996-05-08
申请人： ESTES, Mark, D.
IPC分类号： G06F13/00
CPC分类号： G06F15/17343 , G06F15/8038
摘要： A reconfigurable associative network in which during a configuration phase (409), active signals corresponding to wanted input patterns (405) are configured as an associative network and distinguished from signals corresponding to unwanted input patterns, wanted input patterns (405) can be further associated with output patterns (410) corresponding to wanted responses. During an operational phase of a previously configured associative network (402), input patterns (405) are formed from signals produced by one or a plurality of activated inputs (403). Selected input patterns (404) are then filtered from a set of possible input patterns (408), and output patterns (410) are obtained in response to a particular set of connections between input and output signals.
摘要翻译：一种可重配置关联网络，其中在配置阶段（409）期间，对应于所需输入模式（405）的活动信号被配置为关联网络并且与对应于不需要的输入模式的信号区分开，所需输入模式（405）可进一步关联其中输出模式（410）对应于所需响应。在先前配置的关联网络（402）的操作阶段期间，由一个或多个激活的输入（403）产生的信号形成输入模式（405）。然后从一组可能的输入模式（408）中过滤所选择的输入模式（404），并且响应于输入和输出信号之间的一组特定连接获得输出模式（410）。

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