专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

WO2004055688A1 SCALABLE PROCESSING NETWORK FOR SEARCHING AND ADDING IN A CONTENT ADDRESSABLE MEMORY 审中-公开
标题翻译：可扩展处理网络，用于搜索和添加内容可寻址存储器
公开(公告)号：WO2004055688A1
公开(公告)日：2004-07-01
申请号：PCT/GB2003/005532
申请日：2003-12-17
申请人： ASPEX TECHNOLOGY LIMITED , JALOWIECKI, Ian , WHITTAKER, Martin , LANCASTER, John , BOUGHTON, Donald
发明人： JALOWIECKI, Ian , WHITTAKER, Martin , LANCASTER, John , BOUGHTON, Donald
IPC分类号： G06F15/80
CPC分类号： G06F15/8038
摘要： An alternation network for use with a content addressable memory for implementing a divide and conquer algorithm is described. The alternation network comprises: a plurality of alternation modules connected in series together, each module comprising: a plurality of cascaded logic gates arranged to propagate a match parity signal via the gates along at least part of a matching result vector, the matching result vector being generated by execution of a matching instruction on the content addressable memory, and the logic gates being configured to change the parity of the match parity signal in accordance with the matching result vector; and a vector output arranged to output a parity level vector of the propagated match parity signal present at the each gate of the plurality of logic gates; a logic network for dividing the matching result vector into an odd match vector and an even match vector representing respectively odd and even numbered elements of the matching result vector, by use of the parity level vector; and means for writing a selected one of the odd and even match vectors to the content addressable memory.
摘要翻译：描述了用于实现分割和征服算法的内容可寻址存储器的交替网络。所述交替网络包括：串联连接的多个交替模块，每个模块包括：多个级联逻辑门，布置成沿着匹配结果向量的至少一部分经由所述门传播匹配奇偶校验信号，所述匹配结果向量为通过在内容可寻址存储器上执行匹配指令而产生，并且逻辑门被配置为根据匹配结果向量改变匹配奇偶校验信号的奇偶校验; 以及矢量输出，被布置为输出存在于所述多个逻辑门的每个门处的所传播的匹配奇偶校验信号的奇偶校验电平矢量; 用于通过使用奇偶校验电平矢量将匹配结果矢量划分为奇数匹配矢量和偶数匹配矢量，分别表示匹配结果向量的奇数和偶数编号元素的逻辑网络; 以及用于将奇数和偶数匹配矢量中选择的一个写入内容可寻址存储器的装置。

2. 发明申请

WO2003054707A3 METHOD AND APPARATUS TO GENERATE A STREAM OF NON-CONTIGUOUS MEMORY ADDRESSES 审中-公开
公开(公告)号：WO2003054707A3
公开(公告)日：2003-07-03
申请号：PCT/GB2002/005852
申请日：2002-12-20
申请人： ASPEX TECHNOLOGY LIMITED , WHITAKER, Martin
发明人： WHITAKER, Martin
IPC分类号： G06F9/345
摘要： A method of generating a stream of non-contiguous memory addresses representing contiguous points in logical space is described. The method comprises: generating initialising parameters describing the contiguous points in the logical space; configuring a memory address engine with the initialising parameters; performing an algorithm in the memory address engine according to the initialising parameters to produce a plurality of non-contiguous memory addresses; and collating the non-contiguous memory addresses into the stream of memory addresses for output to a data memory. The present invention has particular application to SIMD processing techniques where there are a plurality of memory address engines.

3. 发明申请

WO2003054707A2 IMPROVEMENTS RELATING TO MEMORY ADDRESSING TECHNIQUES 审中-公开
标题翻译：与存储器寻址技术相关的改进
公开(公告)号：WO2003054707A2
公开(公告)日：2003-07-03
申请号：PCT/GB2002/005852
申请日：2002-12-20
申请人： ASPEX TECHNOLOGY LIMITED , WHITAKER, Martin
发明人： WHITAKER, Martin
IPC分类号： G06F13/00
CPC分类号： G06F9/3895 , G06F9/345
摘要： A method of generating a stream of non-contiguous memory addresses representing contiguous points in logical space is described. The method comprises: generating initialising parameters describing the contiguous points in the logical space; configuring a memory address engine with the initialising parameters; performing an algorithm in the memory address engine according to the initialising parameters to produce a plurality of non-contiguous memory addresses; and collating the non-contiguous memory addresses into the stream of memory addresses for output to a data memory. The present invention has particular application to SIMD processing techniques where there are a plurality of memory address engines.
摘要翻译：描述了一种生成表示逻辑空间中的连续点的不连续的存储器地址流的方法。该方法包括：生成描述逻辑空间中的连续点的初始化参数; 使用初始化参数配置内存地址引擎; 根据初始化参数在存储器地址引擎中执行算法以产生多个不连续的存储器地址; 以及将不连续的存储器地址对准到存储器地址流中以输出到数据存储器。本发明特别适用于存在多个存储器地址引擎的SIMD处理技术。

4. 发明申请

WO2002043068A3 BIT-PARALLEL/BIT-SERIAL COMPOUND CONTENT-ADDRESSABLE (ASSOCIATIVE) MEMORY DEVICES 审中-公开
公开(公告)号：WO2002043068A3
公开(公告)日：2002-05-30
申请号：PCT/GB2001/005134
申请日：2001-11-21
申请人： ASPEX TECHNOLOGY LIMITED , JALOWIECKI, Ian, Paul , LANCASTER, John , KRIKELIS, Anargyros
发明人： JALOWIECKI, Ian, Paul , LANCASTER, John , KRIKELIS, Anargyros
IPC分类号： G11C15/00
摘要： A compound associative memory (or content Addressable Memory) foruse with a SIMD associative data-parallel computer is described. The compound memory (50) comprises a bit-parallel word-organised associative memory (52) comprising an array of associative memory cells (200) arranged to be capable of bit-parallel search and write operations; and a bit-serial associative memory (56) which comprises an array of associative memory cells (400) arranged to be capable of bit-serial search and write operations, but not word bit-parallel search and write operations. The bit-serial memory (52) is operatively connected to the bit-parallel memory (52) and arranged to operated as an extension of the same. The organisation of memory cells (400) into words in the bit-serial memory (56) is aligned transversely with the organisation of memory cells (200) into words in the bit-parallel memory (52) such that the bit-serial memory (56) can be used to index the bit-parallel associative memory (52) efficiently.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式