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1. 发明申请

WO1996006390A2 A TWO-WAY SET-ASSOCIATIVE CACHE MEMORY 审中-公开
标题翻译：一个双向相关的高速缓存存储器
公开(公告)号：WO1996006390A2
公开(公告)日：1996-02-29
申请号：PCT/US1995009896
申请日：1995-08-04
申请人： INTEL CORPORATION
发明人： INTEL CORPORATION , WANG, Wen-Hann , LAI, Konrad, K.
IPC分类号： G06F00/00
CPC分类号： G06F12/0864
摘要： A two-way set-associative cache memory includes both a set array and a data array in one embodiment. The data array comprises multiple elements, each of which can contain a cache line. The set array comprises multiple sets, with each set in the set array corresponding to an element in the data array. Each set in the set array contains information which indicates whether an address received by the cache memory matches the cache line contained in its corresponding element of the data array. The information stored in each set includes a tag and a state. The tag contains a reference to one of the cache lines in the data array. If the tag of a particular set matches the address received by the cache memory, then the cache line associated with that particular set is the requested cache line. The state of a particular set indicates the number of cache lines mapped into that particular set.
摘要翻译：双向组相关高速缓冲存储器在一个实施例中包括集阵列和数据阵列。数据阵列包括多个元素，每个元素可以包含高速缓存行。集合阵列包括多个集合，集合阵列中的每个集合对应于数据数组中的一个元素。集合阵列中的每个集合包含指示高速缓冲存储器接收的地址与数据阵列的相应元素中包含的高速缓存行匹配的信息。存储在每个集合中的信息包括标签和状态。标签包含对数据数组中的一条缓存行的引用。如果特定集合的标签与高速缓存存储器接收的地址匹配，则与该特定集合相关联的高速缓存行是所请求的高速缓存行。特定集合的状态指示映射到该特定集合的高速缓存行数。

2. 发明申请

WO1995001603A1 METHOD AND APPARATUS FOR PERFORMING BUS TRANSACTIONS IN A COMPUTER SYSTEM 审中-公开
标题翻译：在计算机系统中执行总线交易的方法和装置
公开(公告)号：WO1995001603A1
公开(公告)日：1995-01-12
申请号：PCT/US1994004745
申请日：1994-05-02
申请人： INTEL CORPORATION
发明人： INTEL CORPORATION , SARANGDHAR, Nitin, V. , LAI, Konrad, K. , SINGH, Gurbir
IPC分类号： G06F13/16
CPC分类号： G06F13/4213
摘要： A computer system of performing bus transactions on the external bus (101) of the computer system. The computer system permits out-of-order replies in a pipelined bus system. The out-of-order responses include the sending of tokens between both the requesting agents (102 and 103) and the responding agents (110 and 122) in the computer system without the use of dedicated token buses.
摘要翻译：一种在计算机系统的外部总线（101）上执行总线事务的计算机系统。计算机系统允许流水线总线系统中的无序回复。无序响应包括在计算机系统中的请求代理（102和103）与响应代理（110和122）之间发送令牌，而不使用专用令牌总线。

3. 发明申请

WO2014004222A1 INSTRUCTION AND LOGIC TO TEST TRANSACTIONAL EXECUTION STATUS 审中-公开
标题翻译：指令和逻辑测试交易执行状态
公开(公告)号：WO2014004222A1
公开(公告)日：2014-01-03
申请号：PCT/US2013/046633
申请日：2013-06-19
申请人： INTEL CORPORATION , RAJWAR, Ravi , TOLL, Bret, L. , LAI, Konrad, K. , MERTEN, Matthew, C. , DIXON, Martin, G.
发明人： RAJWAR, Ravi , TOLL, Bret, L. , LAI, Konrad, K. , MERTEN, Matthew, C. , DIXON, Martin, G.
IPC分类号： G06F11/22
CPC分类号： G06F11/2236
摘要： Novel instructions, logic, methods and apparatus are disclosed to test transactional execution status. Embodiments include decoding a first instruction to start a transactional region. Responsive to the first instruction, a checkpoint for a set of architecture state registers is generated and memory accesses from a processing element in the transactional region associated with the first instruction are tracked. A second instruction to detect transactional execution of the transactional region is then decoded. An operation is executed, responsive to decoding the second instruction, to determine if an execution context of the second instruction is within the transactional region. Then responsive to the second instruction, a first flag is updated. In some embodiments, a register may optionally be updated and/or a second flag may optionally be updated responsive to the second instruction.
摘要翻译：公开了新的指令，逻辑，方法和装置来测试事务执行状态。实施例包括解码第一指令以启动事务区域。响应于第一指令，生成一组架构状态寄存器的检查点，并跟踪与第一指令相关联的事务区域中的处理元件的存储器访问。然后解码用于检测事务区域的事务执行的第二指令。执行对第二指令的解码的操作，以确定第二指令的执行上下文是否在事务区域内。然后响应于第二指令，更新第一标志。在一些实施例中，可以可选地更新寄存器和/或响应于第二指令任选地更新第二标志。

4. 发明申请

WO1996007970A1 METHOD AND APPARATUS FOR PERFORMING DEFERRED TRANSACTIONS 审中-公开
标题翻译：执行延期交易的方法和装置
公开(公告)号：WO1996007970A1
公开(公告)日：1996-03-14
申请号：PCT/US1995011315
申请日：1995-09-08
申请人： INTEL CORPORATION
发明人： INTEL CORPORATION , SARANGDHAR, Nitin, V. , LAI, Konrad, K. , SINGH, Gurbir , MACWILLIAMS, Peter, D.
IPC分类号： G06F13/14
CPC分类号： G06F13/37 , G06F13/368 , G06F13/4213
摘要： A method and apparatus for performing bus transactions on the bus of the computer system. The present invention includes a method and apparatus for permitting out-of-order replies in a pipelined bus system. The out-of-order responses include the sending of tokens (302) between both the requesting agents and the responding agents in the computer system without the use of dedicated token buses.
摘要翻译：一种用于在计算机系统的总线上执行总线事务的方法和装置。本发明包括一种用于允许流水线总线系统中的无序回复的方法和装置。无序响应包括在计算机系统中的请求代理和响应代理之间发送令牌（302），而不使用专用令牌总线。

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