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1. 发明申请

WO2014171977A1 SEMICONDUCTOR PACKAGE HAVING IC DICE AND VOLTAGE TUNERS 审中-公开
标题翻译：具有IC数字和电压调谐器的半导体封装
公开(公告)号：WO2014171977A1
公开(公告)日：2014-10-23
申请号：PCT/US2013/073683
申请日：2013-12-06
申请人： XILINX, INC.
发明人： VO, Thao, H.T. , GAN, Andy, H. , LI, Xiao-Yu , KLEIN, Matthew, H.
IPC分类号： H01L25/065 , G06F1/32
CPC分类号： H01L25/0652 , G06F1/3203 , G06F1/324 , G06F17/5045 , G06F17/5054 , H01L25/0655 , H01L2224/0401 , H01L2224/0557 , H01L2224/06181 , H01L2224/14181 , H01L2224/16145 , H01L2224/16225 , H01L2224/48227 , H01L2224/73257 , H01L2924/00014 , H01L2924/15192 , H01L2924/15311 , H01L2224/05552
摘要： A semiconductor package includes an interposer (208, 326, 416, 516) and a plurality of integrated circuit (IC) dice (102-108, 232-234, 322-324, 412-414, 512-514) disposed on and intercoupled via the interposer. A first IC die (102, 232, 322, 412, 512) has a clock speed rating that is greater than a clock speed rating of another (104-108, 234, 324, 414, 514) of the IC dice. A plurality of programmable voltage tuners (1 10-1 16, 202-204, 312 & 316, 402-404, 502-504) are coupled to the plurality of IC dice, respectively. A first voltage tuner (1 10, 202, 312, 402, 502) is coupled to the first IC die (102, 232, 322, 412, 512), and the first voltage tuner is programmed to reduce a voltage level of a voltage input to the first voltage tuner and output the reduced voltage to the first IC die.
摘要翻译：半导体封装包括插入器（208,326,416,516）和多个集成电路（IC）芯片（102-108,232-234,322-324,412-414,512-514），其设置在并联上通过插入器。第一IC芯片（102,232,322,412,512）的时钟速度额定值大于IC芯片的另一个时钟速度等级（104-108,234,324,414,514）。多个可编程电压调谐器（110-116,202-204,312和316,402-404,502-504）分别耦合到多个IC芯片。第一电压调谐器（110,202,312,402,502）耦合到第一IC管芯（102,232,312,412,512），并且第一电压调谐器被编程以降低电压的电压电平输入到第一电压调谐器并将降低的电压输出到第一IC芯片。

2. 发明申请

WO2011139597A1 DEVICE SPECIFIC CONFIGURATION OF OPERATING VOLTAGE 审中-公开
标题翻译：器件特定的工作电压配置
公开(公告)号：WO2011139597A1
公开(公告)日：2011-11-10
申请号：PCT/US2011/033553
申请日：2011-04-22
申请人： XILINX, INC.
发明人： TUAN, Tim , CHUNG, David, Y. , CLINE, Ronald, L. , DEBAETS, Andrew, J. , KLEIN, Matthew, H.
IPC分类号： G06F17/50
CPC分类号： G06F17/5054 , G06F17/5068 , G06F2217/84
摘要： A method and circuit for device specific configuration of an operating voltage is provided. A circuit design is analyzed (309) to determine a maximum gate-level delay for the circuit design. A minimum voltage value corresponding to the maximum gate-level delay is determined along with a default voltage value corresponding to a default gate-level delay (306). A voltage scaling factor corresponding to the minimum voltage and default voltage values is determined (320). The circuit design is synthesized such that the synthesized design includes the voltage scaling factor (408). The synthesized design specifies setting an operating voltage to a value of a startup voltage (410) value scaled by the voltage scaling factor (408).
摘要翻译：提供了用于器件特定配置工作电压的方法和电路。分析电路设计（309）以确定电路设计的最大门级延迟。确定对应于最大门级延迟的最小电压值以及对应于默认门级延迟的默认电压值（306）。确定对应于最小电压和默认电压值的电压缩放因子（320）。合成电路设计，使得合成设计包括电压比例因子（408）。合成设计指定将工作电压设置为由电压缩放因子（408）缩放的启动电压（410）值的值。

3. 发明申请

WO2019083721A1 DATABASE LOOKUP USING A SCANNABLE CODE FOR PART SELECTION 审中-公开
公开(公告)号：WO2019083721A1
公开(公告)日：2019-05-02
申请号：PCT/US2018/055003
申请日：2018-10-09
申请人： XILINX, INC.
发明人： KLEIN, Matthew, H. , TEO, Wei Yee Jocelyn , TAYLOR, Craig, E.
IPC分类号： G06F17/50
摘要： Embodiments described herein include techniques for providing information regarding a hardware part (102) using a scannable code (106) so that a customer can make an informed decision when placing the hardware part in a larger computing system (450). A customer may purchase hardware parts that are categorized into a certain bin which has guaranteed range of power consumption or performance. The customer may over design the computing system to accommodate the worst parameter in the range (e.g., the minimum performance or the maximum power consumption) to ensure the timing or power specifications are not violated. Instead, the embodiments herein provide a scannable code on the hardware part which the customer can use to access a database (410) which stores more granular information about the part. The customer can use the performance parameters to make better informed decisions to determine where to place the part in the computing system.

4. 发明申请

WO2014074632A1 CONFIGURABLE EMBEDDED MEMORY SYSTEM 审中-公开
标题翻译：可配置嵌入式存储系统
公开(公告)号：WO2014074632A1
公开(公告)日：2014-05-15
申请号：PCT/US2013/068797
申请日：2013-11-06
申请人： XILINX, INC.
发明人： SUBODH, Kumar , SIMKINS, James, M. , STRADER, Thomas, H. , KLEIN, Matthew, H. , OGDEN, James, E. , DURAIRAJAN, Uma
IPC分类号： G06F13/42 , G11C11/40 , H01L27/11 , H03K19/177
CPC分类号： G06F13/4234 , G11C7/1006 , G11C7/1039 , G11C7/1069 , G11C7/1096 , G11C16/26 , G11C2207/104 , H03K19/17732 , H03K19/1776 , Y02D10/14 , Y02D10/151
摘要： An embodiment of a memory module is disclosed. This memory module (250) is a configurable hard macro. A portion of this memory module (250) includes a data input multiplexer (305) coupled to select between cascaded data and direct/bused data. Such portion further includes, a memory (313) coupled to receive output from the data input multiplexer (305) for storage therein, and a register input multiplexer (325) coupled to select between read data from the memory (313) and the cascaded data. This memory module (250) further includes: a register (335) coupled to receive output from the register input multiplexer (325), a latch/register mode multiplexer (345) coupled to select between the read data from the memory (313) and registered data from the register (335), and a data output multiplexer (217) coupled to select between the cascaded data and output from the latch/register mode multiplexer (345) to provide output data.
摘要翻译：公开了一种存储器模块的实施例。该存储器模块（250）是可配置的硬宏。该存储器模块（250）的一部分包括耦合以在级联数据和直接/传输数据之间进行选择的数据输入多路复用器（305）。这种部分还包括：存储器（313），其被耦合以接收来自数据输入多路复用器（305）的输出以存储在其中;以及寄存器输入多路复用器（325），其耦合以在来自存储器（313）的读取数据和级联数据。该存储器模块（250）还包括：耦合以接收来自寄存器输入多路复用器（325）的输出的寄存器（335），耦合以在来自存储器（313）的读取数据和来自寄存器（335）的注册数据和数据输出多路复用器（217）耦合以在级联数据和从锁存/寄存器模式多路复用器（345）输出之间进行选择以提供输出数据。

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