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1. 发明申请

WO2017007584A1 SEMICONDUCTOR DEVICE WITH NON-UNIFORM TRENCH OXIDE LAYER 审中-公开
标题翻译：具有非均匀三氧化钛层的半导体器件
公开(公告)号：WO2017007584A1
公开(公告)日：2017-01-12
申请号：PCT/US2016/037815
申请日：2016-06-16
申请人： VISHAY-SILICONIX
发明人： PARK, Chanho , SHIBIB, Ayman , TERRIL, Kyle
IPC分类号： H01L29/78 , H01L29/423 , H01L21/02
CPC分类号： H01L29/7802 , H01L29/086 , H01L29/0865 , H01L29/0878 , H01L29/1095 , H01L29/36 , H01L29/404 , H01L29/407 , H01L29/41741 , H01L29/41766 , H01L29/66348 , H01L29/66712 , H01L29/66734 , H01L29/7397 , H01L29/7813 , H01L29/872
摘要： A semiconductor device includes a trench formed in an epitaxial layer and an oxide layer that lines the sidewalls of the trench. The thickness of the oxide layer is non-uniform, so that the thickness of the oxide layer toward the top of the trench is thinner than it is toward the bottom of the trench. The epitaxial layer can have a non-uniform dopant concentration, where the dopant concentration varies according to the thickness of the oxide layer.
摘要翻译：半导体器件包括形成在外延层中的沟槽和对沟槽的侧壁进行排列的氧化物层。氧化物层的厚度不均匀，使得朝向沟槽顶部的氧化物层的厚度比向沟槽底部的厚度薄。外延层可以具有不均匀的掺杂剂浓度，其中掺杂剂浓度根据氧化物层的厚度而变化。

2. 发明申请

WO2012158977A2 SEMICONDUCTOR DEVICE 审中-公开
标题翻译：半导体器件
公开(公告)号：WO2012158977A2
公开(公告)日：2012-11-22
申请号：PCT/US2012/038456
申请日：2012-05-17
申请人： VISHAY-SILICONIX , TERRILL, Kyle , PARK, Chanho
发明人： TERRILL, Kyle , PARK, Chanho
CPC分类号： H01L29/7813 , H01L29/407 , H01L29/41766 , H01L29/4238 , H01L29/66727 , H01L29/66734
摘要： A semiconductor device includes a first group of trench-like structures and a second group of trench-like structures. Each trench-like structure in the first group includes a gate electrode contacted to gate metal and a source electrode contacted to source metal. Each of the trench-like structures in the second group is disabled. The second group of disabled trench-like structures is interleaved with the first group of trench-like structures.
摘要翻译：半导体器件包括第一组沟槽状结构和第二组沟槽状结构。第一组中的每个沟槽状结构包括与栅极金属接触的栅电极和与源极金属接触的源电极。第二组中的每个沟槽状结构都被禁用。第二组残留沟槽状结构与第一组沟槽状结构交错。

3. 发明申请

WO2017180614A1 SEMICONDUCTOR DEVICE HAVING MULTIPLE GATE PADS 审中-公开
标题翻译：半导体器件具有多个闸板
公开(公告)号：WO2017180614A1
公开(公告)日：2017-10-19
申请号：PCT/US2017/026992
申请日：2017-04-11
申请人： VISHAY-SILICONIX
发明人： PARK, Chanho , SHIBIB, Ayman , TERRILL, Kyle
IPC分类号： H01L21/66
摘要： Disclosed are semiconductor devices that include additional gate pads, and methods of fabricating and testing such devices. A device may include a first gate pad, a second gate pad, and a third gate pad. The first gate pad is connected to a gate including a gate oxide layer. The second and third gate pads are part of an electro-static discharge (ESD) protection network for the device. The ESD protection network is initially isolated from the first gate pad and hence from the gate and gate oxide layer. Accordingly, gate oxide integrity (GOI) testing can be effectively performed and the reliability and quality of the gate oxide layer can be checked. The second gate pad can be subsequently connected to the first gate pad to enable the ESD protection network, and the third gate pad can be subsequently connected to an external terminal when the device is packaged.
摘要翻译：公开了包括附加栅极焊盘的半导体器件以及制造和测试这种器件的方法。器件可以包括第一栅极焊盘，第二栅极焊盘和第三栅极焊盘。第一栅极焊盘连接到包括栅极氧化物层的栅极。第二和第三栅极焊盘是器件的静电放电（ESD）保护网络的一部分。 ESD保护网络最初与第一栅极焊盘隔离，因此与栅极和栅极氧化层隔离。因此，可以有效地执行栅极氧化物完整性（GOI）测试，并且可以检查栅极氧化物层的可靠性和质量。随后可以将第二栅极焊盘连接到第一栅极焊盘以启用ESD保护网络，并且当器件被封装时，第三栅极焊盘随后可以连接到外部端子。

4. 发明申请

WO2011050115A2 SPLIT GATE FIELD EFFECT TRANSISTOR 审中-公开
标题翻译：分离栅场效应晶体管
公开(公告)号：WO2011050115A2
公开(公告)日：2011-04-28
申请号：PCT/US2010/053452
申请日：2010-10-20
申请人： VISHAY-SILICONIX , TERRILL, Kyle , YANG, Gao , PARK, Chanho
发明人： TERRILL, Kyle , YANG, Gao , PARK, Chanho
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7813 , H01L29/407 , H01L29/42368 , H01L29/4238 , H01L29/66734 , H01L29/7811
摘要： A split gate field effect transistor device. The device includes a split gate structure having a trench, a gate electrode and a source electrode. A first poly layer is disposed within the trench and is connected to the gate electrode. A second poly layer connected to the source electrode, wherein the first poly layer and the second poly layer are independent.
摘要翻译：分路栅场效应晶体管器件。该器件包括具有沟槽，栅电极和源电极的分离栅结构。第一多晶硅层设置在沟槽内并连接到栅电极。连接到源电极的第二多晶硅层，其中第一多晶硅层和第二多晶硅层是独立的。

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