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1. 发明申请

WO2012170982A2 TOUCH SCREEN 审中-公开
标题翻译：触摸屏
公开(公告)号：WO2012170982A2
公开(公告)日：2012-12-13
申请号：PCT/US2012/041826
申请日：2012-06-11
申请人： TEXAS INSTRUMENTS INCORPORATED , TEXAS INSTRUMENTS JAPAN LIMITED , HAROUN, Baher, S. , CORSI, Marco , GINSBURG, Brian, P. , RENTALA, Vijay, B. , RAMASWAMY, Srinath, M. , SEOK, Eunyoung
发明人： HAROUN, Baher, S. , CORSI, Marco , GINSBURG, Brian, P. , RENTALA, Vijay, B. , RAMASWAMY, Srinath, M. , SEOK, Eunyoung
CPC分类号： G06F3/0421 , G06F3/046 , G06F2203/04109
摘要： A method for determining the location of an object on a touch panel is provided. Initially, a pulse of terahertz radiation (108) is transmitted through a touch panel (102), which formed of a dielectric material such that the pulse generates an evanescent field (116) in a region (114) adjacent to a touch surface of the touch panel. A reflected pulse (118) is generated by an object located within the region adjacent to the touch surface of the touch panel, and a position of the object on the touch surface of the touch panel is triangulated at least in part from the reflected pulse.
摘要翻译：提供了一种用于确定物体在触摸面板上的位置的方法。最初，太赫兹辐射（108）的脉冲通过由电介质材料形成的触摸面板（102）传输，使得该脉冲在邻近触摸表面的区域（114）中产生消逝场（116）触控面板。反射脉冲（118）由位于与触摸面板的触摸面相邻的区域内的物体产生，并且物体在触摸面板的触摸面上的位置至少部分地从反射脉冲进行三角测量。

2. 发明申请

WO2012040376A1 CHIP-TO-CHIP COMMUNICATIONS USING SUB-MILLIMETER WAVES AND DIELECTRIC WAVEGUIDE 审中-公开
标题翻译：使用亚微米波形和电介质波导的芯片间通信
公开(公告)号：WO2012040376A1
公开(公告)日：2012-03-29
申请号：PCT/US2011/052630
申请日：2011-09-21
申请人： TEXAS INSTRUMENTS INCORPORATED , TEXAS INSTRUMENTS JAPAN LIMITED , HAROUN, Baher, S. , CORSI, Marco , AKHTAR, Siraj , WARKE, Nirmal, C.
发明人： HAROUN, Baher, S. , CORSI, Marco , AKHTAR, Siraj , WARKE, Nirmal, C.
IPC分类号： H01L27/00 , H01L21/768 , H01L27/15
CPC分类号： H01L25/0655 , H01L23/66 , H01L24/48 , H01L2224/48091 , H01L2224/48227 , H01L2924/00014 , H01L2924/12041 , H01L2924/12043 , H01L2924/14 , H01L2924/181 , H01L2924/3011 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A system 300-1 provides a "wireless" interconnect system between ICs 302-1 and 304-1 using a dielectric waveguide 316. Each of ICs 302-1 and 304-1 respectively includes a transmitter 306-1 or 306-2 and a receiver 308-1 or 308-2 which are each respectively coupled to a directional antenna 314-1 or 314-2. Typically, the antennas 314-1 and 314-2 generate radio frequency (RF) signals in the sub-millimeter range (i.e., wavelength of
摘要翻译：系统300-1使用介质波导316在IC 302-1和304-1之间提供“无线”互连系统.IC 302-1和304-1中的每一个分别包括发射机306-1或306-2和接收机308-1或308-2分别耦合到定向天线314-1或314-2。通常，天线314-1和314-2产生亚毫米范围（即，波长<1mm）的射频（RF）信号，在介质波导上建立RF链路。公开了用于单向通信的类似系统。

3. 发明申请

WO2012048140A2 PIPELINED CONTINUOUS-TIME SIGMA DELTA MODULATOR 审中-公开
标题翻译：流水线连续时间SIGMA DELTA调制器
公开(公告)号：WO2012048140A2
公开(公告)日：2012-04-12
申请号：PCT/US2011/055147
申请日：2011-10-06
申请人： TEXAS INSTRUMENTS INCORPORATED , TEXAS INSTRUMENTS JAPAN LIMITED , HAROUN, Baher, S. , SRINIVASAN, Venkatesh , SATARZADEH, Patrick , CORSI, Marco
发明人： HAROUN, Baher, S. , SRINIVASAN, Venkatesh , SATARZADEH, Patrick , CORSI, Marco
IPC分类号： H03M3/00
CPC分类号： H03M3/344 , H03M3/458
摘要： A pipelined continuous-time (CT) sigma-delta modulators (SDM) is provided that has an architecture that is readily calibrated. The system includes a digital filter and other features that can be adjusted to account for input imbalance errors and well as quantization leakage noise. An example two-stage pipeline arrangement has CT SDMs (or sub-CT SDMs) 202 and 212, DAC 204, digital filter 206, amplifiers 220 and 210, digital gain circuit 214, summing circuits 208 and 216, output circuit 218, and an adjustable delay 222. CT SDM 202 may be a lower order modulator (i.e., order of 1 or 2), while CT SDM 212 may be a higher order modulator (i.e., order greater than 3) with aggressive noise shaping. Amplifier 210 also includes a filter.
摘要翻译：提供流水线连续时间（CT）Σ-Δ调制器（SDM），其具有容易校准的架构。该系统包括数字滤波器和其他功能，可以根据输入不平衡误差和量化泄漏噪声进行调整。示例性两级流水线装置具有CT SDM（或子CT SDM）202和212，DAC 204，数字滤波器206，放大器220和210，数字增益电路214，求和电路208和216，输出电路218以及可调延迟222.CT SDM 202可以是较低阶调制器（即，阶数为1或2），而CT SDM 212可以是具有激进噪声整形的较高阶调制器（即阶数大于3）。放大器210还包括一个滤波器。

4. 发明申请

WO2012024371A3 TRACK AND HOLD ARCHITECTURE WITH TUNABLE BANDWIDTH 审中-公开
公开(公告)号：WO2012024371A3
公开(公告)日：2012-02-23
申请号：PCT/US2011/048037
申请日：2011-08-17
申请人： TEXAS INSTRUMENTS INCORPORATED , TEXAS INSTRUMENTS JAPAN LIMITED , PAYNE, Robert, F. , CORSI, Marco
发明人： PAYNE, Robert, F. , CORSI, Marco
IPC分类号： H03M1/12 , H03M1/66
摘要： An analog-to-digital converter (ADC) 400 converts analog input signal X(t) to a digital signal Y[n]. To do this, divider 402 divides a clock signal CLK (with a frequency of F s or period of T s ) into M clock signals (each with a frequency of F s /M) that are staggered by delay circuits 418- 1 to 418-M and provided to ADCs 410- 1 to 410-M. This allows each of ADCs 410- 1 to 410-M to convert the analog signal X(t) to digital signals X 1 (k) to X(k). The gain and DC offset adjustments are applied to digital signals X 1 (k) to Χ Μ (k) by correction circuits 416- 1 to 416-M to generate digital signals Y[1] to Y[M], which can then be multiplexed by multiplexer 408 to generate the digital signal Y[N].

5. 发明申请

WO2012051478A2 PIPELINED ADC HAVING THREE-LEVEL DAC ELEMENTS 审中-公开
标题翻译：具有三层DAC元件的流水线ADC
公开(公告)号：WO2012051478A2
公开(公告)日：2012-04-19
申请号：PCT/US2011/056256
申请日：2011-10-14
申请人： TEXAS INSTRUMENTS INCORPORATED , TEXAS INSTRUMENTS JAPAN LIMITED , CORSI, Marco , PAYNE, Robert, F.
发明人： CORSI, Marco , PAYNE, Robert, F.
IPC分类号： H03M1/12 , H03M1/66
CPC分类号： H03M1/069 , H03M1/44
摘要： A pipelined analog-to-digital converter (ADC) includes three-state digital-to-analog converter (DAC) switches or segments. An example DAC 300 has logic circuitry 304 and three-state DAC switches 302-1 to 302-k. In operation, the logic circuitry 304 receives a control word from the ADC and generates a plurality of control signals for each three-state switch. The switches may include transistors and a current source so that, based on the control signals, the switches can generate "+1", "-1"or "0" logic states.
摘要翻译：流水线模数转换器（ADC）包括三态数模转换器（DAC）开关或片段。示例DAC 300具有逻辑电路304和三态DAC开关302-1至302-k。在操作中，逻辑电路304从ADC接收控制字并为每个三态开关产生多个控制信号。开关可以包括晶体管和电流源，使得基于控制信号，开关可以产生“+ 1”，“-1”或“0” 逻辑状态。

6. 发明申请

WO2011056908A2 SYSTEM AND METHOD FOR IMPLEMENTING LOW-COST ELECTRONIC GYROSCOPES AND ACCELEROMETER 审中-公开
标题翻译：用于实现低成本电子陀螺仪和加速度计的系统和方法
公开(公告)号：WO2011056908A2
公开(公告)日：2011-05-12
申请号：PCT/US2010/055350
申请日：2010-11-04
申请人： TEXAS INSTRUMENTS INCORPORATED , HUNG, Chih-Ming , CORSI, Marco , TEXAS INSTRUMENTS JAPAN LIMITED
发明人： HUNG, Chih-Ming , CORSI, Marco
IPC分类号： G01C19/66 , G01C19/62 , G01C19/60 , G01P9/00
CPC分类号： G01C19/64 , G01R25/00
摘要： A disclosed gyroscope or accelerometer apparatus is integrated into an integrated circuit chip. The apparatus has phase locked loops (PLLs) (210, 212) formed on a substrate that generate a signal having a wavelength that is less than 10mm and greater than l00μm. The PLLs are coupled to propagation paths (202, 204) formed on the substrate with coupled sections of larger and smaller similar (e.g., circular or triangular) nested shapes. Detection circuitry (such as phase detector 218) is coupled between the different paths, with the size of path sections selected such that, when the apparatus is at rest, output signals from corresponding propagation path sections are substantially in phase.
摘要翻译：所公开的陀螺仪或加速度计装置被集成到集成电路芯片中。该装置具有在衬底上形成的锁相环（PLL）（210,212），其产生具有小于10mm且大于100μm的波长的信号。 PLL被耦合到形成在衬底上的传播路径（202,204），耦合部分具有较大和较小的类似（例如，圆形或三角形）嵌套形状。检测电路（诸如相位检测器218）耦合在不同路径之间，其中路径部分的大小被选择为使得当装置静止时，来自相应传播路径部分的输出信号基本上同相。

7. 发明申请

WO2013149218A1 SENSOR POWER MANAGEMENT 审中-公开
标题翻译：传感器电源管理
公开(公告)号：WO2013149218A1
公开(公告)日：2013-10-03
申请号：PCT/US2013/034727
申请日：2013-03-29
申请人： TEXAS INSTRUMENTS INCORPORATED , TEXAS INSTRUMENTS JAPAN LIMITED
发明人： NARAYANAN, Sriram , FREEMAN, David, Louis , CORSI, Marco
IPC分类号： G05F1/565
CPC分类号： G01D3/10 , G01D18/00
摘要： A sensor power management arrangement (200) includes a signal processing circuit (220) configured to receive signal from a sensor (210), to test the signal against at least one criterion, and to pass the signal for further processing in response to the signal passing the at least one criterion. In this way, only signals that are of a sufficient importance or significance will consume the maximum amount of processing energy and through processing by later processes or circuitry. Should a signal from a sensor (210) not be strong enough or meet other criteria, power will not be wasted in preparing that signal for provision to the microcontroller or microprocessor (260). Additional flexibility in the sensor power management can be realized by adjusting the criteria against which the sensor signal is compared based on a status of the sensor apparatus (200).
摘要翻译：传感器电源管理装置（200）包括被配置为从传感器（210）接收信号的信号处理电路（220），以针对至少一个准则测试该信号，并响应信号传递该信号用于进一步处理传递至少一个标准。以这种方式，只有具有足够重要性或重要性的信号将消耗最大量的处理能量并通过后续处理或电路的处理。如果来自传感器（210）的信号不足够强或符合其他标准，则在准备该信号以提供给微控制器或微处理器（260）时不会浪费功率。基于传感器装置（200）的状态，可以通过调整传感器信号被比较的准则来实现传感器电源管理中的额外的灵活性。

8. 发明申请

WO2021041596A1 TRACK AND HOLD CIRCUITS WITH TRANSFORMER COUPLED BOOTSTRAP SWITCH 审中-公开
公开(公告)号：WO2021041596A1
公开(公告)日：2021-03-04
申请号：PCT/US2020/048088
申请日：2020-08-27
申请人： TEXAS INSTRUMENTS INCORPORATED , TEXAS INSTRUMENTS JAPAN LIMITED
发明人： RAGHUNATHAN, Ashwin , CORSI, Marco , HAROUN, Baher , SEYED ALIROTEH, Seyed, Miaad , SANKARAN, Swaminathan , PAYNE, Robert, Floyd
IPC分类号： G11C27/02 , H03K17/00
摘要： A track and hold circuit (100) includes a signal input terminal (119), a clock input terminal (110), an output terminal (106), a transistor (112), and a bootstrapping circuit with a transformer (120). The transistor includes a source (113), a drain (114), and a gate (115), where the source (113) is coupled to the signal input terminal (119), and the drain (114) is coupled to the output terminal (106). The transformer (120) includes a primary winding (121) coupled to the clock input terminal (110), and a secondary winding (124). The secondary winding (124) is coupled between the source (113) and the gate (115) to control a gate-source voltage (VGS) of the transistor (112).

9. 发明申请

WO2013152226A1 INTERCHIP COMMUNICATION USING EMBEDDED DIELECTRIC AND METAL WAVEGUIDES 审中-公开
标题翻译：使用嵌入式电介质和金属波导的交互通信
公开(公告)号：WO2013152226A1
公开(公告)日：2013-10-10
申请号：PCT/US2013/035322
申请日：2013-04-04
申请人： TEXAS INSTRUMENTS INCORPORATED , TEXAS INSTRUMENTS JAPAN LIMITED
发明人： HERBSOMMER, Juan, A. , PAYNE, Robert, F. , CORSI, Marco , HAROUN, Baher, S. , ALI, Hassan
IPC分类号： G02B6/12 , G02B6/10
CPC分类号： G02B6/12004 , G02B6/1228 , G02B6/43 , H01L2223/6627 , H01L2224/16227 , H01L2924/15311 , H01P3/121 , H01P3/122 , H01P5/107 , H05K1/0239 , H05K1/0243 , H05K1/025 , H05K1/0274 , H05K2201/0187 , H05K2201/037 , H05K2201/09618 , H05K2201/10098
摘要： An apparatus is provided. There is a circuit assembly (206-A1) with a package substrate (304-A) and an integrated circuit (IC) (302-A). The package substrate has a microstrip line (208-A1), and the IC is secured to the package substrate and is electrically coupled to the microstrip line. A circuit board (202-A) is also secured to the package substrate. A dielectric waveguide (204- A) is secured to the circuit board. The dielectric waveguide has a dielectric core (310-A) that extends into a transition region (314- A) located between the dielectric waveguide and the microstrip line, and the microstrip line is configured to form a communication link with the dielectric waveguide.
摘要翻译：提供了一种装置。存在具有封装衬底（304-A）和集成电路（IC）（302-A）的电路组件（206-A1）。封装衬底具有微带线（208-A1），并且IC被固定到封装衬底并且电耦合到微带线。电路板（202-A）也固定到封装衬底。电介质波导（204-A）固定到电路板上。电介质波导具有延伸到位于电介质波导和微带线之间的过渡区域（314-A）中的介质芯（310-A），并且微带线被配置为与介质波导形成通信链路。

10. 发明申请

WO2006072030A1 SWITCHED-CAPACITOR CIRCUIT WITH SCALED REFERENCE VOLTAGE 审中-公开
标题翻译：具有标定参考电压的开关电容器电路
公开(公告)号：WO2006072030A1
公开(公告)日：2006-07-06
申请号：PCT/US2005/047539
申请日：2005-12-30
申请人： TEXAS INSTRUMENTS INCORPORATED , CORSI, Marco
发明人： CORSI, Marco
IPC分类号： H03M1/38
CPC分类号： H03M1/08 , H03M1/0695 , H03M1/442
摘要： A pipelined analog-to-digital converter (ADC) (30) with improved precision is disclosed. The pipelined ADC (30) includes a sequence of stages (20), each of which includes a sample-and-hold circuit (22), an analog-to-digital converter (23), and the functions of a digital-to-analog converter (DAC) (25), an adder (24), and a gain stage (27) at which a residue signal (RES) is generated for application to the next stage (20) in the sequence. A multiplying DAC performs the functions of the DAC (25), adder (24), and gain stage (27) in the stage (20), and is based on an operational amplifier. Sample capacitors and reference capacitors receive the analog input from the sample-and-hold circuit (22) in a sample phase; parallel capacitors are provided to maintain constant circuit gain. Extended reference voltages (V REFNX V REFNX ) at levels that exceed the output range of the operational amplifier are applied to the reference capacitors, in response to the digital output of the analog-to-digital converter (23) in its stage (20). The reference capacitors are scaled according to the extent to which the extended reference voltages (V REFNX V REFNX ) exceed the op amp output levels. The effects of noise on the reference voltages (V REFNX V REFNX ) on the residue signal (RES) are thus greatly reduced.
摘要翻译：公开了一种具有改进精度的流水线模数转换器（ADC）（30）。流水线ADC（30）包括一系列级（20），每个级包括采样保持电路（22），模数转换器（23），以及数模转换器模拟转换器（DAC）（25），加法器（24）和增益级（27），在所述增益级（27）中产生用于按顺序施加到下一级（20）的残留信号（RES）。乘法DAC在级（20）中执行DAC（25），加法器（24）和增益级（27）的功能，并且基于运算放大器。样品电容器和参考电容器在采样阶段接收来自采样保持电路（22）的模拟输入; 提供并联电容器以保持恒定的电路增益。扩展的参考电压（V REF REF）

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