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1. 发明申请

WO2008144629A1 RAISED SOURCE/DRAIN REGIONS IN MOS DEVICE 审中-公开
标题翻译： MOS设备中的提取源/排水区域
公开(公告)号：WO2008144629A1
公开(公告)日：2008-11-27
申请号：PCT/US2008/064082
申请日：2008-05-19
申请人： TEXAS INSTRUMENTS INCORPORATED , SRIDHAR, Seetharaman , MANSOORI, Majid
发明人： SRIDHAR, Seetharaman , MANSOORI, Majid
IPC分类号： H01L21/336
CPC分类号： H01L21/823814 , H01L21/823807 , H01L29/66636 , H01L29/7848
摘要： Provided is a method for manufacturing a semiconductor device that includes a substrate (210) having a PMOS device region (220) and NMOS device region (260). A first gate structure (240) including a first hardmask (248) and a second gate structure (280) including a second hardmask (288) are formed in the region and region, respectively. Epitaxial SiGe regions (610) are created in the substrate proximate the first gate structure, the first hardmask protecting the first gate structure from the SiGe. First source/drain regions (410, 1020) are formed proximate the first gate structure, at least a portion of each of the first source/drain regions located within one of the SiGe regions. Additionally, a raised portion (710) is grown above the substrate proximate the second gate structure, the portion forming at least a part of second source/drain regions (820, 1120) located on opposing sides of the second gate structure. Additionally, the first and second hardmasks protect the first and second gate structures from the growing.
摘要翻译：提供一种制造半导体器件的方法，该半导体器件包括具有PMOS器件区（220）和NMOS器件区（260）的衬底（210）。分别在区域和区域中形成包括第一硬掩模（248）和包括第二硬掩模（288）的第二栅极结构（280）的第一栅极结构（240）。在靠近第一栅极结构的衬底中形成外延SiGe区域（610），第一硬掩模保护第一栅极结构与SiGe。第一源极/漏极区（410,1020）形成在第一栅极结构附近，第一源/漏区中的每一个的至少一部分位于SiGe区之一内。另外，凸起部分（710）在靠近第二栅极结构的衬底上方生长，该部分形成位于第二栅极结构的相对侧上的第二源极/漏极区域（820,1120）的至少一部分。此外，第一和第二硬掩模保护第一和第二门结构免受增长。

2. 发明申请

WO2008144631A1 TRENCH ISOLATION STRUCTURE AND METHOD OF MANUFACTURE 审中-公开
标题翻译： TRENCH隔离结构和制造方法
公开(公告)号：WO2008144631A1
公开(公告)日：2008-11-27
申请号：PCT/US2008/064087
申请日：2008-05-19
申请人： TEXAS INSTRUMENTS INCORPORATED , SRIDHAR, Seetharaman , HALL, Craig
发明人： SRIDHAR, Seetharaman , HALL, Craig
IPC分类号： H01L21/768
CPC分类号： H01L21/823878 , H01L21/76232
摘要： The disclosure provides a trench isolation structure, a semiconductor device, and a method for manufacturing a semiconductor device. The semiconductor device (100), in one embodiment, includes a substrate (105) having a first device region (120) and a second device region (160), wherein the first device region includes a first gate structure (125) and first source/drain regions (150) and the second device region includes a second gate structure (165) and second source/drain regions (190). The semiconductor device further includes a trench isolation structure (110) configured to isolate the first device region from the second device region, the trench isolation structure comprising: 1) an isolation trench located within the substrate, wherein the isolation trench includes an opening portion and a bulbous portion, and further wherein a maximum width of the opening portion is less than a maximum width of the bulbous portion, and 2) dielectric material substantially filling the isolation trench.
摘要翻译：本公开提供了沟槽隔离结构，半导体器件以及半导体器件的制造方法。在一个实施例中，半导体器件（100）包括具有第一器件区域（120）和第二器件区域（160）的衬底（105），其中第一器件区域包括第一栅极结构（125）和第一源极漏极区域（150），第二器件区域包括第二栅极结构（165）和第二源极/漏极区域（190）。所述半导体器件还包括被配置为将所述第一器件区域与所述第二器件区隔离的沟槽隔离结构（110），所述沟槽隔离结构包括：1）位于所述衬底内的隔离沟槽，其中所述隔离沟槽包括开口部分和球根部分，并且其中所述开口部分的最大宽度小于所述球形部分的最大宽度，以及2）绝缘材料基本上填充所述隔离沟槽。

3. 发明申请

WO2009021187A2 METHOD FOR FORMING SELF-ALIGNED WELLS TO SUPPORT TIGHT SPACING 审中-公开
标题翻译：用于形成自对准的孔以支持紧密间隔的方法
公开(公告)号：WO2009021187A2
公开(公告)日：2009-02-12
申请号：PCT/US2008/072631
申请日：2008-08-08
申请人： TEXAS INSTRUMENTS INCORPORATED , SRIDHAR, Seetharaman
发明人： SRIDHAR, Seetharaman
IPC分类号： H01L21/027
CPC分类号： H01L21/266 , H01L21/823892
摘要： Methods include utilizing a single mask layer (306) to form tightly spaced, adjacent first-type and second-type well regions (310, 314). The mask layer is formed over a substrate (302) in a region in which the second-type well regions will be formed. The first-type well regions are formed in the exposed portions of the substrate. Then, the second-type well-regions are formed through the resist mask.
摘要翻译：方法包括利用单个掩模层（306）形成紧密间隔的相邻的第一和第二类型阱区域（310,314）。掩模层形成在将形成第二类型阱区域的区域中的衬底（302）上。第一类型的阱区形成在衬底的暴露部分中。然后，通过抗蚀剂掩模形成第二类型的阱区。

4. 发明申请

WO2008144625A1 METHOD FOR INTEGRATING SILICON GERMANIUM AND CARBON DOPED SILICON WITHIN A STRAINED CMOS FLOW 审中-公开
标题翻译：在应变CMOS流中积聚硅锗和碳掺杂硅的方法
公开(公告)号：WO2008144625A1
公开(公告)日：2008-11-27
申请号：PCT/US2008/064077
申请日：2008-05-19
申请人： TEXAS INSTRUMENTS INCORPORATED , SRIDHAR, Seetharaman
发明人： SRIDHAR, Seetharaman
IPC分类号： H01L21/336
CPC分类号： H01L21/823807 , H01L21/823814 , H01L27/092 , H01L29/66636 , H01L29/7848
摘要： The disclosure provides a semiconductor device and method of manufacture therefore. The method for manufacturing the semiconductor device, in one embodiment, includes providing a substrate (210) having a PMOS device region (220) and NMOS device region (260). Thereafter, a first gate structure (240) and a second gate structure (280) are formed over the PMOS device region and the NMOS device region, respectively. Additionally, recessed epitaxial SiGe regions (710) may be formed in the substrate on opposing sides of the first gate structure. Moreover, first source/drain regions may be formed on opposing sides of the first gate structure and second source/drain regions on opposing sides of the second gate structure. The first source/drain regions and second source/drain regions may then be annealed to form activated first source/drain regions (1110) and activated second source/drain regions (1120), respectively. Additionally, recessed epitaxial carbon doped silicon regions (1410) may be formed in the substrate on opposing sides of the second gate structure after annealing.
摘要翻译：因此，本公开提供了一种半导体器件及其制造方法。在一个实施例中，制造半导体器件的方法包括提供具有PMOS器件区域（220）和NMOS器件区域（260）的衬底（210）。此后，分别在PMOS器件区域和NMOS器件区域上形成第一栅极结构（240）和第二栅极结构（280）。此外，可以在第一栅极结构的相对侧上的衬底中形成凹入的外延SiGe区域（710）。此外，第一源极/漏极区域可以形成在第一栅极结构的相对侧上，以及在第二栅极结构的相对侧上的第二源极/漏极区域。然后可以将第一源极/漏极区域和第二源极/漏极区域退火以分别形成激活的第一源极/漏极区域（1110）和激活的第二源极/漏极区域（1120）。此外，在退火之后，可以在第二栅极结构的相对侧上的衬底中形成凹入的外延碳掺杂硅区域（1410）。

5. 发明申请

WO2019100224A1 SEMICONDUCTOR PRODUCT AND FABRICATION PROCESS 审中-公开
公开(公告)号：WO2019100224A1
公开(公告)日：2019-05-31
申请号：PCT/CN2017/112240
申请日：2017-11-22
申请人： TEXAS INSTRUMENTS INCORPORATED , TEXAS INSTRUMENTS JAPAN LIMITED , CHEN, Yaping
发明人： CHEN, Yaping , YANG, Hong , ALI, Abbas , ZUO, Chao , SRIDHAR, Seetharaman , LIU, Yunlong
IPC分类号： H01L21/768
摘要： Processes(100) for fabricating a semiconductor product(200) and for forming a patterned stack with an aluminum layer(218) and a tungsten layer(216), include forming(104) a first dielectric layer(212) on a gate structure(204) and on first and second regions(208, 210) of a substrate(202), forming(108) a diffusion barrier layer(214) on the first dielectric layer(212), forming(110) a tungsten layer(216) on the diffusion barrier layer(214), forming(112) an aluminum layer(218) on the tungsten layer(216), forming(114) a hard mask layer(220) on the aluminum layer(218), forming(116) a patterned resist mask layer(222) which covers the hard mask layer(220) above the first region(208) and exposes the hard mask layer(220) above the second region(210), dry etching(118, 120) the hard mask layer(220) and the aluminum layer(218) above the second region(210) using the patterned resist mask layer(222), removing(122) the resist mask layer(222), and dry etching(124) the tungsten layer(216) using the hard mask layer(220) to expose the first dielectric layer(212) above the second region(210).

6. 发明申请

WO2019133966A1 HIGH-VOLTAGE DRAIN EXTENDED MOS TRANSISTOR 审中-公开
公开(公告)号：WO2019133966A1
公开(公告)日：2019-07-04
申请号：PCT/US2018/068126
申请日：2018-12-31
申请人： TEXAS INSTRUMENTS INCORPORATED , TEXAS INSTRUMENTS JAPAN LIMITED
发明人： KIM, Sunglyong , SRIDHAR, Seetharaman , PENSHARKAR, Sameer
IPC分类号： H01L29/78
摘要： A semiconductor device (100) includes a MOS transistor (101) located within a semiconductor substrate (105) of a first conductivity type. The transistor (101) includes a body well (135) located between a drain well (130) and a substrate contact well (160). A buried voltage blocking region (155) of a second conductivity type is located within the substrate (105) and is connected to the body well (135). The buried voltage blocking region (155) extends toward the substrate contact well (160), with an unmodified portion (195) of the substrate (105) remaining between the voltage blocking region (155) and the substrate contact well (160).

7. 发明申请

WO2014138453A1 DUAL RESURF TRENCH FIELD PLATE IN VERTICAL MOSFET 审中-公开
标题翻译：垂直场效应晶体管中的双光栅激光场
公开(公告)号：WO2014138453A1
公开(公告)日：2014-09-12
申请号：PCT/US2014/021348
申请日：2014-03-06
申请人： TEXAS INSTRUMENTS INCORPORATED , TEXAS INSTRUMENTS JAPAN LIMITED
发明人： KOCON, Christopher, B. , NEILSON, John, Manning, Savidge , MOLLOY, Simon, J. , KAWAHARA, Hideaki , YANG, Hong , SRIDHAR, Seetharaman , WU, Hao , WEN, Boling
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7813 , H01L29/0649 , H01L29/404 , H01L29/407 , H01L29/41766 , H01L29/66727 , H01L29/66734 , H01L29/7802
摘要： A semiconductor device (100) contains a vertical MOS transistor (106) with instances of a vertical reduced surface field (RESURF) trench (112) on opposite sides of a vertical drift region (110). The vertical RESURF trench (112) contains a dielectric trench liner (114) on sidewalls, a lower field plate (120) and an upper field plate (122). The dielectric trench liner (114) between the lower field plate and the vertical drift region (110) is thicker than between the upper field plate and the vertical drift region (110). A gate (126) is disposed over the vertical drift region (110) and is separate from the upper field plate (122). The upper field plate (122) and the lower field plate (120) are electrically coupled to a source electrode of the vertical MOS transistor.
摘要翻译：半导体器件（100）包含在垂直漂移区域（110）的相对侧上具有垂直缩小表面场（RESURF）沟槽（112）的实例的垂直MOS晶体管（106）。垂直RESURF沟槽（112）在侧壁上包含介电沟槽衬垫（114），下场板（120）和上场板（122）。下场板和垂直漂移区（110）之间的电介质沟槽衬垫（114）比上场板和垂直漂移区（110）之间厚。栅极（126）设置在垂直漂移区域（110）上方并与上部场板（122）分离。上场板（122）和下场板（120）电耦合到垂直MOS晶体管的源电极。

8. 发明申请

WO2022032566A1 SEMICONDUCTOR DEVICE INCLUDING LATERAL INSULATOR 审中-公开
公开(公告)号：WO2022032566A1
公开(公告)日：2022-02-17
申请号：PCT/CN2020/108857
申请日：2020-08-13
申请人： TEXAS INSTRUMENTS INCORPORATED , TEXAS INSTRUMENTS JAPAN LIMITED
发明人： MA, Fei , CHEN, Yaping , LIU, Yunlong , YANG, Hong , YANG, Shengpin , NIU, Baoqiang , LIU, Rui , FENG, Zhipeng , SRIDHAR, Seetharaman , KIM, Sunglyong
IPC分类号： H01L21/336 , H01L29/78
摘要： A semiconductor device (300), and methods of forming the same. In one example, the semiconductor device (300) includes a trench (305) in a substrate (310) having a top surface (302), and a shield (330) within the trench (305). The semiconductor device (300) also includes a shield liner (315) between a sidewall of the trench (305) and the shield (330), and a lateral insulator (345) over the shield (330) contacting the shield liner (315). The semiconductor device (300) also includes a gate dielectric layer (350) on an exposed sidewall of the trench (305) between the lateral insulator (345) and the top surface (302). The lateral insulator (345) may have a minimum thickness at least two times thicker than a maximum thickness of the gate dielectric layer (350).

9. 发明申请

WO2017156540A1 INTEGRATED HIGH-SIDE DRIVER FOR P-N BIMODAL POWER DEVICE 审中-公开
标题翻译：用于P-N双极型功率器件的集成高边驱动器
公开(公告)号：WO2017156540A1
公开(公告)日：2017-09-14
申请号：PCT/US2017/022183
申请日：2017-03-13
申请人： TEXAS INSTRUMENTS INCORPORATED , TEXAS INSTRUMENTS JAPAN LIMITED
发明人： ZHANG, Yongxi , PENDHARKAR, Sameer P. , HOWER, Philip L. , GIOMBANCO, Salvatore , MARINO, Filippo , SRIDHAR, Seetharaman
IPC分类号： H01L29/76 , H01L21/8238
摘要： In described examples, an integrated circuit chip (102) includes a bimodal power N-P -Laterally Diffused Metal Oxide Semiconductor (LDMOS) device (104) having an N-gate (G N ) coupled to receive an input signal (IN) and a level shifter (108) coupled to receive the input signal and to provide a control signal to a P-gate driver (106) of the N-P-LDMOS device.
摘要翻译：在所描述的示例中，集成电路芯片（102）包括具有N栅极（G N）的双模功率NP-正向扩散金属氧化物半导体（LDMOS）器件（104）（IN）和电平移位器（108），所述电平移位器（108）被耦合以接收输入信号并向NP-LDMOS装置的P门驱动器（106）提供控制信号。

10. 发明申请

WO2019126572A1 HIGH VOLTAGE LATERAL JUNCTION DIODE DEVICE 审中-公开
公开(公告)号：WO2019126572A1
公开(公告)日：2019-06-27
申请号：PCT/US2018/066933
申请日：2018-12-20
申请人： TEXAS INSTRUMENTS INCORPORATED , TEXAS INSTRUMENTS JAPAN LIMITED
发明人： KIM, Sunglyong , SRIDHAR, Seetharaman , PENDHARKAR, Sameer
IPC分类号： H01L27/06 , H01L29/861
摘要： A lateral junction diode device (110) includes a substrate (105) having at least a semiconductor surface. A depletion-mode LDMOS device (130) is in the semiconductor surface including a source (131), a drain and a gate (133) above a gate dielectric (134), and a channel region (135) between the source (131) and the drain under the gate (133). A drift region (136a, 136b, 138) is between the channel region (135) and the drain. The drain also provides a cathode for the lateral junction diode device (110). An embedded diode (120) includes a second cathode (121) and an anode (122) that is shared with the device (110). The embedded diode (120) is junction isolated by an isolation region that comprises a well (123) coupled to a buried layer (124) located between the anode (122) and the source (131). The anode (122) and isolation region are directly connected to the gate (133), and the second cathode (121) is directly connected to the source (131).

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