专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

WO2019100224A1 SEMICONDUCTOR PRODUCT AND FABRICATION PROCESS 审中-公开
公开(公告)号：WO2019100224A1
公开(公告)日：2019-05-31
申请号：PCT/CN2017/112240
申请日：2017-11-22
申请人： TEXAS INSTRUMENTS INCORPORATED , TEXAS INSTRUMENTS JAPAN LIMITED , CHEN, Yaping
发明人： CHEN, Yaping , YANG, Hong , ALI, Abbas , ZUO, Chao , SRIDHAR, Seetharaman , LIU, Yunlong
IPC分类号： H01L21/768
摘要： Processes(100) for fabricating a semiconductor product(200) and for forming a patterned stack with an aluminum layer(218) and a tungsten layer(216), include forming(104) a first dielectric layer(212) on a gate structure(204) and on first and second regions(208, 210) of a substrate(202), forming(108) a diffusion barrier layer(214) on the first dielectric layer(212), forming(110) a tungsten layer(216) on the diffusion barrier layer(214), forming(112) an aluminum layer(218) on the tungsten layer(216), forming(114) a hard mask layer(220) on the aluminum layer(218), forming(116) a patterned resist mask layer(222) which covers the hard mask layer(220) above the first region(208) and exposes the hard mask layer(220) above the second region(210), dry etching(118, 120) the hard mask layer(220) and the aluminum layer(218) above the second region(210) using the patterned resist mask layer(222), removing(122) the resist mask layer(222), and dry etching(124) the tungsten layer(216) using the hard mask layer(220) to expose the first dielectric layer(212) above the second region(210).

2. 发明申请

WO2022061654A1 DUAL SHIELD OXIDE DAMAGE CONTROL 审中-公开
公开(公告)号：WO2022061654A1
公开(公告)日：2022-03-31
申请号：PCT/CN2020/117461
申请日：2020-09-24
申请人： TEXAS INSTRUMENTS INCORPORATED , TEXAS INSTRUMENTS JAPAN LIMITED
发明人： LI, Peng , CHEN, Yaping , LIU, Yunlong , YANG, Hong , YANG, Shengpin , HU, Jing , ZHUANG, Chao
IPC分类号： H01L29/78 , H01L21/336 , H01L27/088
摘要： A method (200) of fabricating a semiconductor device includes etching (205) a group of trenches in a semiconductor surface layer of a substrate. The group of trenches includes an outermost trench that has a first width and remaining trenches of the group of trenches have a second width that is less than the first width. The outermost trench is formed at an edge of the group of trenches. A dielectric liner is formed (210) in the group of trenches and the dielectric liner is etched (215) in an upper portion of the group of trenches to remove a partial thickness of the dielectric liner. A full thickness of the dielectric liner is maintained in a lower portion of the group of trenches. The group of trenches is filled (220) with a polysilicon layer.

3. 发明申请

WO2018165809A1 TRANSISTOR DEVICE WITH SINKER CONTACTS AND METHODS FOR MANUFACTURING THE SAME 审中-公开
公开(公告)号：WO2018165809A1
公开(公告)日：2018-09-20
申请号：PCT/CN2017/076387
申请日：2017-03-13
申请人： TEXAS INSTRUMENTS INCORPORATED , TEXAS INSTRUMENTS JAPAN LIMITED
发明人： XIONG, Yufei , YANG, Hong , CHISHOLM, Michael F. , LIU, Yunlong
IPC分类号： H01L21/00 , H01L29/45
摘要： A device includes a semiconductor substrate (100); a buried layer (101); and a trench (128) with inner walls extending from the buried layer (101) to a surface of the semiconductor substrate (100), the trench (128) having sidewalls, a bottom wall, a barrier layer (134) including a titanium (Ti) layer covering the sidewalls and the bottom wall, and a filler including more than one layer of conductor material (130, 132) formed on the barrier layer (134).

4. 发明申请

WO2014138453A1 DUAL RESURF TRENCH FIELD PLATE IN VERTICAL MOSFET 审中-公开
标题翻译：垂直场效应晶体管中的双光栅激光场
公开(公告)号：WO2014138453A1
公开(公告)日：2014-09-12
申请号：PCT/US2014/021348
申请日：2014-03-06
申请人： TEXAS INSTRUMENTS INCORPORATED , TEXAS INSTRUMENTS JAPAN LIMITED
发明人： KOCON, Christopher, B. , NEILSON, John, Manning, Savidge , MOLLOY, Simon, J. , KAWAHARA, Hideaki , YANG, Hong , SRIDHAR, Seetharaman , WU, Hao , WEN, Boling
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7813 , H01L29/0649 , H01L29/404 , H01L29/407 , H01L29/41766 , H01L29/66727 , H01L29/66734 , H01L29/7802
摘要： A semiconductor device (100) contains a vertical MOS transistor (106) with instances of a vertical reduced surface field (RESURF) trench (112) on opposite sides of a vertical drift region (110). The vertical RESURF trench (112) contains a dielectric trench liner (114) on sidewalls, a lower field plate (120) and an upper field plate (122). The dielectric trench liner (114) between the lower field plate and the vertical drift region (110) is thicker than between the upper field plate and the vertical drift region (110). A gate (126) is disposed over the vertical drift region (110) and is separate from the upper field plate (122). The upper field plate (122) and the lower field plate (120) are electrically coupled to a source electrode of the vertical MOS transistor.
摘要翻译：半导体器件（100）包含在垂直漂移区域（110）的相对侧上具有垂直缩小表面场（RESURF）沟槽（112）的实例的垂直MOS晶体管（106）。垂直RESURF沟槽（112）在侧壁上包含介电沟槽衬垫（114），下场板（120）和上场板（122）。下场板和垂直漂移区（110）之间的电介质沟槽衬垫（114）比上场板和垂直漂移区（110）之间厚。栅极（126）设置在垂直漂移区域（110）上方并与上部场板（122）分离。上场板（122）和下场板（120）电耦合到垂直MOS晶体管的源电极。

5. 发明申请

WO2018000357A1 POWER MOSFET WITH METAL FILLED DEEP SINKER CONTACT FOR CSP 审中-公开
标题翻译：用于CSP的带金属填充深度接触器的功率MOSFET
公开(公告)号：WO2018000357A1
公开(公告)日：2018-01-04
申请号：PCT/CN2016/087968
申请日：2016-06-30
申请人： TEXAS INSTRUMENTS INCORPORATED , TEXAS INSTRUMENTS JAPAN LIMITED
发明人： LIU, Yunlong , YANG, Hong , LIN, Ho , LV, Tianping , ZOU, Sheng , JIA, Qiuling , XIONG, Yufei
IPC分类号： H01L29/417 , H01L29/78 , H01L21/311 , H01L21/768
摘要： A method of forming an IC (180) including a power semiconductor device includes providing a substrate (100) having an epi layer (150) thereon with at least one transistor (160) formed therein covered by a pre-metal dielectric (PMD) layer (118). Contact openings are etched from through the PMD into the epi layer to form a sinker trench extending to a first node of the device. A metal fill material (128b) is deposited to cover a sidewall and bottom of the sinker trench but not completely fill the sinker trench. A dielectric filler layer (128c) is deposited over the metal fill material to fill the sinker trench. An overburden region of the dielectric filler layer is removed stopping on a surface of the metal fill material in the overburden region to form a sinker contact (128). A patterned interconnect metal is formed providing a connection between the interconnect metal and metal fill material on the sidewall of the sinker trench.
摘要翻译：一种形成包括功率半导体器件的IC（180）的方法包括：提供其上具有外延层（150）的衬底（100），其中形成有至少一个晶体管（160），所述晶体管预金属电介质（PMD）层（118）。将接触开口从PMD蚀刻到外延层中以形成延伸到装置的第一节点的下沉沟槽。沉积金属填充材料（128b）以覆盖沉降槽的侧壁和底部，但不完全填充沉降槽。介电填料层（128c）沉积在金属填充材料上以填充沉陷沟槽。去除介电填充层的覆盖层区域，停止在覆盖层区域中的金属填充材料的表面上以形成沉降片接触（128）。形成图案化的互连金属，从而在互连金属和沉陷沟槽的侧壁上的金属填充材料之间提供连接。

6. 发明申请

WO2022032566A1 SEMICONDUCTOR DEVICE INCLUDING LATERAL INSULATOR 审中-公开
公开(公告)号：WO2022032566A1
公开(公告)日：2022-02-17
申请号：PCT/CN2020/108857
申请日：2020-08-13
申请人： TEXAS INSTRUMENTS INCORPORATED , TEXAS INSTRUMENTS JAPAN LIMITED
发明人： MA, Fei , CHEN, Yaping , LIU, Yunlong , YANG, Hong , YANG, Shengpin , NIU, Baoqiang , LIU, Rui , FENG, Zhipeng , SRIDHAR, Seetharaman , KIM, Sunglyong
IPC分类号： H01L21/336 , H01L29/78
摘要： A semiconductor device (300), and methods of forming the same. In one example, the semiconductor device (300) includes a trench (305) in a substrate (310) having a top surface (302), and a shield (330) within the trench (305). The semiconductor device (300) also includes a shield liner (315) between a sidewall of the trench (305) and the shield (330), and a lateral insulator (345) over the shield (330) contacting the shield liner (315). The semiconductor device (300) also includes a gate dielectric layer (350) on an exposed sidewall of the trench (305) between the lateral insulator (345) and the top surface (302). The lateral insulator (345) may have a minimum thickness at least two times thicker than a maximum thickness of the gate dielectric layer (350).

7. 发明申请

WO2017106824A1 IC HAVING FAILSAFE FUSE ON FIELD DIELECTRIC 审中-公开
标题翻译：集成电路在现场电介质上具有故障保险丝
公开(公告)号：WO2017106824A1
公开(公告)日：2017-06-22
申请号：PCT/US2016/067481
申请日：2016-12-19
申请人： TEXAS INSTRUMENTS INCORPORATED , TEXAS INSTRUMENTS JAPAN LIMITED
发明人： KAWAHARA, Hideaki , YANG, Hong , MINDRICELU, Eugen, Pompiliu , SHAW, Robert, Graham
IPC分类号： H01L23/62
CPC分类号： H01L23/5256
摘要： In described examples, a fuse circuit includes a substrate (105), a top semiconductor layer (110) doped a first conductivity type having a well (130) doped a second conductivity type formed therein including a well contact (130a). A field dielectric layer (FOX) (115) is on the semiconductor layer (110). A fuse (116, 117, 118) is on the FOX (115) within the well (130) including a fuse body (116) including electrically conductive material having first and second fuse contacts (117, 118). A transistor (125) is formed in the semiconductor layer (110) including a control terminal (CT) (121) with CT contact (121a), a first terminal (FT) (122) with FT contact (122a), and a second terminal (ST) (123) with a ST contact (123a). A coupling path (144) is between the CT contact (121a) and well contact (130a), a first resistor (141) is coupled between the FT contact (122a) and CT contact (121a), and a coupling path (143) is between the ST contact (123a) and the first fuse contact (117).
摘要翻译：在所描述的示例中，熔丝电路包括：衬底（105）;掺杂第一导电类型的顶部半导体层（110），其具有掺杂了第二导电类型的阱（130），所述阱包括阱接触（130a）。场介电层（FOX）（115）位于半导体层（110）上。保险丝（116,117,118）在阱（130）内的FOX（115）上，包括具有第一和第二熔丝触点（117,118）的导电材料的保险丝体（116）。在包括具有CT触点（121a）的控制端子（CT）（121），具有FT触点（122a）的第一端子（FT）（122）和第二触点终端（ST）（123）与ST触点（123a）。耦合路径144位于CT触点121a和阱触点130a之间，第一电阻器141耦合在FT触点122a和CT触点121a之间，位于ST触头（123a）和第一个熔丝触头（117）之间。

8. 发明申请

WO2016179598A1 MULTIPLE SHIELDING TRENCH GATE FET 审中-公开
标题翻译：多功能屏蔽闸门FET
公开(公告)号：WO2016179598A1
公开(公告)日：2016-11-10
申请号：PCT/US2016/031517
申请日：2016-05-09
申请人： TEXAS INSTRUMENTS INCORPORATED , TEXAS INSTRUMENTS JAPAN LIMITED
发明人： KAWAHARA, Hideaki , SRIDHAR, Seetharaman , KOCON, Christopher, Boguslaw , MOLLOY, Simon, John , YANG, Hong
IPC分类号： H01L29/78
CPC分类号： H01L29/7813 , H01L21/28114 , H01L29/063 , H01L29/0649 , H01L29/1095 , H01L29/404 , H01L29/407 , H01L29/41766 , H01L29/4236 , H01L29/42368 , H01L29/513 , H01L29/66734
摘要： In described examples, a semiconductor device (100) contains a vertical MOS transistor (104) having a trench gate (120) in trenches (110) extending through a vertical drift region (108) to a drain region (106). The trenches (110) have field plates (116) under the gate (120). The field plates (116) are adjacent to the drift region (108) and have multiple segments (122) and (124). A dielectric liner (112) in the trenches (110) separating the field plates (116) from the drift region (108) has a thickness greater than a gate dielectric layer (118) between the gate (120) and the body (130). The dielectric liner (112) is thicker on a lower segment (122) of the field plate (116), at a bottom (114) of the trenches (110), than an upper segment (124), immediately under the gate (120).
摘要翻译：在所描述的示例中，半导体器件（100）包含在沟槽（110）中具有沟槽栅极（120）的垂直MOS晶体管（104），其延伸穿过垂直漂移区（108）到漏极区（106）。沟槽（110）在栅极（120）下方具有场板（116）。场板（116）与漂移区（108）相邻并且具有多个段（122）和（124）。将场板（116）与漂移区（108）分离的沟槽（110）中的电介质衬垫（112）的厚度大于栅极（120）和主体（130）之间的栅介质层（118）。电介质衬垫（112）在场板（116）的下部段（122）上，在沟槽（110）的底部（114）处比在栅极（120）正下方的上部段（124）更厚）。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式