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1. 发明申请

WO9848541A3 DIRECT DIGITAL ACCESS ARRANGEMENT CIRCUITRY AND METHOD FOR CONNECTING TO PHONE LINES 审中-公开
标题翻译：直接数字访问安排电路和连接到电话线的方法
公开(公告)号：WO9848541A3
公开(公告)日：1999-03-18
申请号：PCT/US9808116
申请日：1998-04-21
申请人： SILICON LAB INC , SCOTT JEFFREY W , SOOCH NAVDEEP S , WELLAND DAVID R
发明人： SCOTT JEFFREY W , SOOCH NAVDEEP S , WELLAND DAVID R
IPC分类号： H04M1/76 , H03M1/42 , H04L7/033 , H04L25/02 , H04L25/06 , H04M1/57 , H04M3/00 , H04M11/06 , H04M19/00 , H04M19/02 , H04L12/00
CPC分类号： H04M1/573 , H04L7/033 , H04L25/0266 , H04L25/06 , H04M1/76 , H04M3/007 , H04M11/06 , H04M19/001 , H04M19/02
摘要： An isolation system is provided that is suitable for use in telephony, medical instrumentation, industrial process control and other applications. Preferred embodiments of the invention comprise a capacitive isolation barrier across which a digital signal is communicated (209, 210). The system provides a means of communication (225) across the isolation barrier that is highly immune to amplitude and phase noise interference. Clock recovery circuitry (216) may be employed on one side of the isolation barrier to extract timing information from the digital signal communicated across the barrier, and to filter the effects of phase noise introduced at the barrier. Delta-sigma converters (201, 208) may be disposed on both sides of the isolation barrier to convert signals between analog and digital domains. An isolated power supply (220) may also be provided on the isolated side of the barrier, whereby direct current is generated in response to the digital data received across the isolation barrier. Finally, a bidirectional isolation system is provided whereby bidirectional communication of digital signals is accomplished using a single pair of isolation capacitors (209, 110). In preferred embodiments, the digital data communicated across the barrier consists of digital delta-sigma data signals multiplexed in time with other digital control, signaling and framing information.

2. 发明申请

WO02056488A3 DIGITAL INTERFACE IN RADIO-FREQUENCY APPARATUS AND ASSOCIATED METHODS 审中-公开
标题翻译：无线电频率设备的数字接口及相关方法
公开(公告)号：WO02056488A3
公开(公告)日：2003-03-06
申请号：PCT/US0200895
申请日：2002-01-10
申请人： SILICON LAB INC
发明人： VISHAKHADATTA G DIWAKAR , SCOTT JEFFREY W , TUTTLE G TYSON , SRINIVASAN VISHNU SHANKAR , RAFI ASLAMALI A
IPC分类号： H04B1/28 , H04B1/40 , H04B15/02 , H04B15/04
CPC分类号： H04B1/0003 , H04B1/28 , H04B1/406 , H04B15/02 , H04B15/04 , H04B2215/064
摘要： Radio-frequency (RF) apparatus includes receiver analog circuitry that receives an RF signal and provides at least one digital signal to receiver digital circuitry that functions in cooperation with the receiver analog circuitry. The interface between the receiver analog circuitry and the receiver digital circuitry includes configurable signal lines that function as a serial interface, or as a data and clock signal interface, depending on the state of a control signal.
摘要翻译：射频（RF）设备包括接收模拟电路，其接收RF信号并且向与接收机模拟电路协作起作用的接收机数字电路提供至少一个数字信号。接收器模拟电路和接收机数字电路之间的接口包括用作串行接口的可配置信号线，或者根据控制信号的状态作为数据和时钟信号接口。

3. 发明申请

WO02056487A3 PARTITIONED RADIO-FREQUENCY APPARATUS AND ASSOCIATED METHODS 审中-公开
标题翻译：分频无线电频率设备及相关方法
公开(公告)号：WO02056487A3
公开(公告)日：2003-03-06
申请号：PCT/US0200896
申请日：2002-01-10
申请人： SILICON LAB INC
发明人： KERTH DONALD A , BEHRENS RICHARD T , SCOTT JEFFREY W , VISHAKHADATTA G DIWAKAR , TUTTLE G TYSON , SRINIVASAN VISHNU SHANKAR
IPC分类号： H04B1/28 , H04B1/40 , H04B15/02 , H04B15/04 , H04B1/16
CPC分类号： H04B1/0003 , H04B1/28 , H04B1/406 , H04B15/02 , H04B15/04 , H04B2215/064
摘要： Radio-frequency (RF) apparatus includes receiver analog circuitry that receives an RF signal and provides at least one digital signal to receiver digital circuitry that functions in cooperation with the receiver analog circuitry. The receiver analog circuitry and the receiver digital circuitry are partitioned so that interference effects between the receiver analog circuitry and the receiver digital circuitry tend to be reduced.
摘要翻译：射频（RF）设备包括接收模拟电路，其接收RF信号并且向与接收机模拟电路协作起作用的接收机数字电路提供至少一个数字信号。接收机模拟电路和接收机数字电路被分割，使得接收机模拟电路和接收机数字电路之间的干扰效应趋于降低。

4. 发明申请

WO2007109395A3 DATA PROCESSOR HAVING DYNAMIC CONTROL OF INSTRUCTION PREFETCH BUFFER DEPTH AND METHOD THEREFOR 审中-公开
标题翻译：具有指令预留缓冲区深度的动态控制的数据处理器及其方法
公开(公告)号：WO2007109395A3
公开(公告)日：2008-10-30
申请号：PCT/US2007062651
申请日：2007-02-23
申请人： FREESCALE SEMICONDUCTOR INC , SCOTT JEFFREY W , MOYER WILLIAM C
发明人： SCOTT JEFFREY W , MOYER WILLIAM C
IPC分类号： G06F9/30 , G06F9/40 , G06F15/00
CPC分类号： G06F9/3802 , G06F9/30149 , G06F9/3814 , G06F12/0862 , G06F2212/6022 , Y02D10/13
摘要： A data processor (102) includes a prefetch buffer (112) and a fetch control unit (116). The prefetch buffer (112) has a plurality of lines. The prefetch buffer (112) has a variable maximum depth that defines a number of lines of the plurality of lines that are capable of storing instructions. The fetch control unit (116) is coupled to the prefetch buffer to monitor at least one of the plurality of lines of the prefetch buffer (112) and to adjust the variable maximum depth of the prefetch buffer (112) in response to a state of the data processor (102).
摘要翻译：数据处理器（102）包括预取缓冲器（112）和获取控制单元（116）。预取缓冲器（112）具有多条线。预取缓冲器（112）具有可变的最大深度，其定义能够存储指令的多行的行数。取指控制单元（116）耦合到预取缓冲器以监视预取缓冲器（112）的多行中的至少一行并响应于预取缓冲器（112）的状态来调整预取缓冲器（112）的可变最大深度数据处理器（102）。

5. 发明申请

WO2008085648A3 SELECTIVE GUARDED MEMORY ACCESS ON A PER-INSTRUCTION BASIS 审中-公开
标题翻译：选择性的保护记忆访问在一个基本的基础上
公开(公告)号：WO2008085648A3
公开(公告)日：2008-10-16
申请号：PCT/US2007087258
申请日：2007-12-12
申请人： FREESCALE SEMICONDUCTOR INC , SCOTT JEFFREY W , MOYER WILLIAM C
发明人： SCOTT JEFFREY W , MOYER WILLIAM C
IPC分类号： G06F12/00
CPC分类号： G06F9/3834 , G06F9/30043 , G06F9/30181
摘要： A method includes receiving, at a processing device, a memory access instruction (402) comprising a guarded access specifier representative of a guarded access policy. The method further includes performing, at the processing device, a memory access represented by the memory access instruction in accordance with the guarded access policy (408). A processing device (100) includes a processor core (110) configured to determine a guarded access policy for a memory access instruction based on a guarded access specifier (310) of the memory access instruction (300). The processing device (100) further includes a memory management unit (112) configured to facilitate a memory access represented by the memory access instruction based on the guarded access policy.
摘要翻译：一种方法包括在处理设备处接收包括代表受保护的访问策略的被保护的访问说明符的存储器访问指令（402）。该方法还包括在处理装置处执行根据被保护的访问策略（408）由存储器访问指令表示的存储器访问。处理设备（100）包括处理器核心（110），其被配置为基于存储器访问指令（300）的被保护的访问说明符（310）确定存储器访问指令的保护访问策略。处理装置（100）还包括存储器管理单元（112），被配置为基于被保护的访问策略来促进由存储器访问指令表示的存储器访问。

6. 发明申请

WO2008061141A9 SUB-PIXEL NBN DETECTOR 审中-公开
标题翻译：亚像素NBN探测器
公开(公告)号：WO2008061141A9
公开(公告)日：2008-07-03
申请号：PCT/US2007084674
申请日：2007-11-14
申请人： LOCKHEED CORP , CAINE ERNIE J , SCOTT JEFFREY W , JONES COLIN E , COCKRUM CHARLES A
发明人： CAINE ERNIE J , SCOTT JEFFREY W , JONES COLIN E , COCKRUM CHARLES A
IPC分类号： H01L27/146
CPC分类号： H01L31/035281 , H01L27/146 , H01L27/14601 , H01L27/14603 , H01L27/14638 , H01L27/14643 , H01L27/14694 , H01L31/0304 , H01L31/101 , H01L31/102 , Y02E10/50
摘要： A method of making a two-dimensional detector array (and of such an array) comprising, for each of a plurality of rows and a plurality of columns of individual detectors, forming an n-doped semiconductor photo absorbing layer, forming a barrier layer comprising one or more of AISb, AIAsSb, AIGaAsSb, AIPSb, AIGaPSb, and HgZnTe, and forming an n-doped semiconductor contact area.
摘要翻译：一种制造二维检测器阵列（以及这种阵列）的方法，对于多个行和多列独立检测器中的每一个，形成n掺杂半导体光吸收层，形成阻挡层，该阻挡层包括一个或多个AISb，AIAsSb，AIGaAsSb，AIPSb，AIGaPSb和HgZnTe，并形成n掺杂的半导体接触区。

7. 发明申请

WO2005060458A2 METHOD AND APPARATUS FOR ALLOCATING ENTRIES IN A BRANCH TARGET BUFFER 审中-公开
标题翻译：用于在分支目标缓冲器中分配入口的方法和设备
公开(公告)号：WO2005060458A2
公开(公告)日：2005-07-07
申请号：PCT/US2004037627
申请日：2004-11-12
申请人： FREESCALE SEMICONDUCTOR INC , MOYER WILLIAM C , SCOTT JEFFREY W
发明人： MOYER WILLIAM C , SCOTT JEFFREY W
IPC分类号： G06F9/00 , G06F9/38 , G06F15/00
CPC分类号： G06F9/382 , G06F9/3806
摘要： A method (200) and apparatus (100) for allocating entries in a branch target buffer (BTB) (144) in a pipelined data processing system includes: sequentially fetching instructions; determining that one of the instructions is a branch instruction (210, 215, 220); decoding the branch instruction to determine a branch target address; determining if the branch target address can be obtained without causing a stall condition in the pipelined data processing system; and selectively allocating an entry of the BTB (144) based on the determination. In one embodiment, an entry of the BTB (144) is allocated if the branch instruction is not loaded into a predetermined slot (S1) of a prefetch buffer (102) and no other stall condition will occur. The method (200) and apparatus (100) combine the advantages of using a BTB (144) and branch lookahead to reduce stall conditions in the data processing system.
摘要翻译：一种用于在流水线数据处理系统中分配分支目标缓冲器（BTB）（144）中的条目的方法（200）和装置（100）包括：顺序地取指令; 确定所述指令之一是分支指令（210,215,220）; 解码分支指令以确定分支目标地址; 确定在流水线数据处理系统中是否可以获得分支目标地址而不引起失速状况; 并且基于该确定来选择性地分配BTB（144）的条目。在一个实施例中，如果分支指令未被加载到预取缓冲器（102）的预定时隙（S1）中并且不会发生其他停顿条件，则分配BTB（144）的条目。方法（200）和设备（100）结合使用BTB（144）和分支先行的优点来减少数据处理系统中的停滞条件。

8. 发明申请

WO0030226A8 VERTICAL CAVITY SURFACE EMITTING LASERS WITH CONSISTENT SLOPE EFFICIENCIES 审中-公开
标题翻译：具有一致性斜率效应的垂直孔表面发射激光
公开(公告)号：WO0030226A8
公开(公告)日：2000-07-06
申请号：PCT/US9926793
申请日：1999-11-12
申请人： CIELO COMMUNICATIONS INC , SCOTT JEFFREY W
发明人： SCOTT JEFFREY W
IPC分类号： H01S5/00 , H01S5/02 , H01S5/028 , H01S5/183 , H01S5/10
CPC分类号： H01S5/183 , H01S5/0042 , H01S5/0201 , H01S5/02284 , H01S5/0285 , H01S5/0427
摘要： A vertical cavity surface emitting laser, VCSEL, (2) with variable tuning layer (10) for adjusting the slope of the laser (2) and method for manufacturing the same are disclosed. In practice, a VCSEL wafer is grown by any conventional technique, and fabricated into discrete lasers (2) while maintained in wafer form. The initial lasers (2) are then tested to determine characteristics, such as the slope efficiency distribution to within a target specification by altering the phase of the top facet reflectivity of the initial lasers (2). The resulting change in transmission directly changes the laser slope in a predictable fashion. The tuning step may be repeated, if necessary, to further refine the slope to the desired value. The method produces VCSELs (2) with similar or consistent slopes from a plurality of wafers. Also disclosed are an optical subassembly (110) and optical transceiver (130) incorporating the improved VCSELs.
摘要翻译：公开了一种垂直腔面发射激光器，具有用于调节激光器斜率的可变调谐层（2）的VCSEL（2）及其制造方法。实际上，通过任何常规技术生长VCSEL晶片，并将其制成分立激光器（2），同时保持晶片形式。然后测试初始激光器（2），以通过改变初始激光器（2）的顶面反射率的相位来确定特征，例如目标规格内的斜率效率分布。所产生的变化的变化直接以可预测的方式改变激光斜率。如果需要，可以重复调整步骤，以进一步将斜率细化到期望值。该方法产生具有与多个晶片相似或一致的斜率的VCSEL（2）。还公开了结合有改进的VCSEL的光学子组件（110）和光收发器（130）。

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