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1. 发明申请

WO2011085054A2 IN-SITU PASSIVATION METHODS TO IMPROVE PERFORMANCE OF POLYSILICON DIODE 审中-公开
标题翻译：用于提高多晶硅二极管性能的现场通用方法
公开(公告)号：WO2011085054A2
公开(公告)日：2011-07-14
申请号：PCT/US2011020293
申请日：2011-01-06
申请人： SANDISK 3D LLC , CHEN XIYING , HOU KUN , PAN CHUANBIN , BANDYOPADHYAY ABHIJIT , CHEN YUNG-TIN
发明人： CHEN XIYING , HOU KUN , PAN CHUANBIN , BANDYOPADHYAY ABHIJIT , CHEN YUNG-TIN
IPC分类号： H01L29/68 , H01L21/02 , H01L21/329
CPC分类号： H01L29/8615 , G11C13/003 , G11C2213/72 , H01L27/1021 , H01L27/2409 , H01L29/6609 , H01L45/04 , H01L45/06 , H01L45/085 , H01L45/1233 , H01L45/146 , H01L45/147 , H01L45/149 , H01L45/16
摘要： A nonvolatile memory cell including a storage element in series with a diode steering element. At least one interface of the diode steering element is passivated.
摘要翻译：一种非易失性存储单元，包括与二极管转向元件串联的存储元件。二极管操纵元件的至少一个界面被钝化。

2. 发明申请

WO2011159583A3 COMPOSITION OF MEMORY CELL WITH RESISTANCE-SWITCHING LAYERS 审中-公开
标题翻译：具有电阻切换层的记忆体组成
公开(公告)号：WO2011159583A3
公开(公告)日：2012-06-14
申请号：PCT/US2011040105
申请日：2011-06-10
申请人： SANDISK 3D LLC , KREUPL FRANZ , BANDYOPADHYAY ABHIJIT , CHEN YUNG-TIN , FU CHU-CHEN , JAYASEKARA WIPUL PEMSIRI , KAI JAMES , MAKALA RAGHUVEER S , RABKIN PETER , SAMACHISA GEORGE , ZHANG JINGYAN
发明人： KREUPL FRANZ , BANDYOPADHYAY ABHIJIT , CHEN YUNG-TIN , FU CHU-CHEN , JAYASEKARA WIPUL PEMSIRI , KAI JAMES , MAKALA RAGHUVEER S , RABKIN PETER , SAMACHISA GEORGE , ZHANG JINGYAN
IPC分类号： H01L45/00 , H01L27/24
CPC分类号： H01L27/2409 , G11C11/16 , G11C11/1659 , G11C13/0007 , G11C2213/31 , G11C2213/71 , G11C2213/72 , H01L27/2481 , H01L45/08 , H01L45/122 , H01L45/1233 , H01L45/1253 , H01L45/145 , H01L45/146
摘要： A memory device in a 3-D read and write memory includes memory cells. Each memory cell includes a resistance-switching memory element (RSME) in series with a steering element. The RSME has first and second resistance-switching layers on either side of a conductive intermediate layer, and first and second electrodes at either end of the RSME. The first and second resistance-switching layers can both have a bipolar or unipolar switching characteristic. In a set or reset operation of the memory cell, an ionic current flows in the resistance-switching layers, contributing to a switching mechanism. An electron flow, which does not contribute to the switching mechanism, is reduced due to scattering by the conductive intermediate layer, to avoid damage to the steering element. Particular materials and combinations of materials for the different layers of the RSME are provided.
摘要翻译： 3-D读写存储器中的存储器件包括存储器单元。每个存储单元包括与转向元件串联的电阻切换存储元件（RSME）。 RSME在导电中间层的任一侧上具有第一和第二电阻切换层，在RSME的任一端具有第一和第二电极。第一和第二电阻切换层都可以具有双极或单极开关特性。在存储单元的置位或复位操作中，离子电流在电阻切换层中流动，有助于切换机构。由于导电中间层的散射，对切换机构无贡献的电子流减少，以避免损坏转向元件。提供了用于RSME不同层的材料和材料的组合。

3. 发明申请

WO2011159583A4 COMPOSITION OF MEMORY CELL WITH RESISTANCE-SWITCHING LAYERS 审中-公开
标题翻译：具有电阻切换层的存储器单元的组成
公开(公告)号：WO2011159583A4
公开(公告)日：2012-08-02
申请号：PCT/US2011040105
申请日：2011-06-10
申请人： SANDISK 3D LLC , KREUPL FRANZ , BANDYOPADHYAY ABHIJIT , CHEN YUNG-TIN , FU CHU-CHEN , JAYASEKARA WIPUL PEMSIRI , KAI JAMES , MAKALA RAGHUVEER S , RABKIN PETER , SAMACHISA GEORGE , ZHANG JINGYAN
发明人： KREUPL FRANZ , BANDYOPADHYAY ABHIJIT , CHEN YUNG-TIN , FU CHU-CHEN , JAYASEKARA WIPUL PEMSIRI , KAI JAMES , MAKALA RAGHUVEER S , RABKIN PETER , SAMACHISA GEORGE , ZHANG JINGYAN
IPC分类号： H01L45/00 , H01L27/24
CPC分类号： H01L27/2409 , G11C11/16 , G11C11/1659 , G11C13/0007 , G11C2213/31 , G11C2213/71 , G11C2213/72 , H01L27/2481 , H01L45/08 , H01L45/122 , H01L45/1233 , H01L45/1253 , H01L45/145 , H01L45/146
摘要： A memory device in a 3-D read and write memory includes memory cells. Each memory cell includes a resistance-switching memory element (RSME) in series with a steering element. The RSME has first and second resistance-switching layers on either side of a conductive intermediate layer, and first and second electrodes at either end of the RSME. The first and second resistance-switching layers can both have a bipolar or unipolar switching characteristic. In a set or reset operation of the memory cell, an ionic current flows in the resistance-switching layers, contributing to a switching mechanism. An electron flow, which does not contribute to the switching mechanism, is reduced due to scattering by the conductive intermediate layer, to avoid damage to the steering element. Particular materials and combinations of materials for the different layers of the RSME are provided.
摘要翻译：三维读写存储器中的存储器件包括存储器单元。每个存储单元包括与转向元件串联的电阻切换存储元件（RSME）。 RSME在导电中间层的任一侧具有第一和第二电阻转换层，并且在RSME的任一端具有第一和第二电极。第一和第二电阻切换层都可以具有双极性或单极性切换特性。在存储器单元的置位或复位操作中，离子电流在电阻切换层中流动，从而有助于切换机制。由于导电中间层的散射，对开关机构没有贡献的电子流被减少，以避免损坏导向元件。提供了用于RSME的不同层的特定材料和材料的组合。

4. 发明申请

WO2011088050A3 PATTERNING METHOD FOR HIGH DENSITY PILLAR STRUCTURES 审中-公开
标题翻译：高密度支柱结构的方法
公开(公告)号：WO2011088050A3
公开(公告)日：2012-03-29
申请号：PCT/US2011020848
申请日：2011-01-11
申请人： SANDISK 3D LLC , NGUYEN NATALIE , POON PAUL WAI KIE , RADIGAN STEVEN J , KONEVECKI MICHAEL , CHEN YUNG-TIN , MAKALA RAGHUVEER , DUNTON VANCE
发明人： NGUYEN NATALIE , POON PAUL WAI KIE , RADIGAN STEVEN J , KONEVECKI MICHAEL , CHEN YUNG-TIN , MAKALA RAGHUVEER , DUNTON VANCE
IPC分类号： H01L21/027 , H01L21/033 , H01L21/768 , H01L27/24
CPC分类号： H01L21/0274 , H01L21/0337 , H01L27/1021 , Y10S438/947 , Y10S438/948 , Y10S438/949
摘要： A method of making a device includes forming a first photoresist layer over a sacrificial layer, patterning the first photoresist layer to form first photoresist features, rendering the first photoresist features insoluble to a solvent, forming a second photoresist layer over the first photoresist features, patterning the second photoresist layer to form second photoresist features, forming a spacer layer over the first and second photoresist features, etching the spacer layer to form spacer features and to expose the first and second photoresist features, forming third photoresist features between the spacer features, removing the spacer features, and patterning the sacrificial layer using the first, second and third photoresist features as a mask to form sacrificial features.
摘要翻译：制造器件的方法包括在牺牲层上形成第一光致抗蚀剂层，图案化第一光致抗蚀剂层以形成第一光致抗蚀剂特征，使得第一光致抗蚀剂特征不溶于溶剂，在第一光致抗蚀剂特征上形成第二光致抗蚀剂层，第二光致抗蚀剂层以形成第二光致抗蚀剂特征，在第一和第二光致抗蚀剂特征上形成间隔层，蚀刻间隔层以形成间隔物特征并暴露第一和第二光致抗蚀剂特征，在间隔物特征之间形成第三光致抗蚀剂特征，去除间隔物特征，并且使用第一，第二和第三光致抗蚀剂特征作为掩模来图案化牺牲层以形成牺牲特征。

5. 发明申请

WO2010078343A2 RESIST FEATURE AND REMOVABLE SPACER PITCH DOUBLING PATTERNING METHOD FOR PILLAR STRUCTURES 审中-公开
标题翻译：支柱结构的抗剪特征和可拆卸间距间距加倍方法
公开(公告)号：WO2010078343A2
公开(公告)日：2010-07-08
申请号：PCT/US2009069711
申请日：2009-12-29
申请人： SANDISK 3D LLC , CHEN YUNG-TIN , RADIGAN STEVEN J
发明人： CHEN YUNG-TIN , RADIGAN STEVEN J
IPC分类号： H01L21/033
CPC分类号： H01L45/1691 , H01L21/0337 , H01L21/0338 , H01L27/1021
摘要： A method of making a semiconductor device includes forming at least one layer over a substrate, forming at least two spaced apart features of imagable material over the at least one layer, forming sidewall spacers on the at least two features and filling a space between a first sidewall spacer on a first feature and a second sidewall spacer on a second feature with a filler feature. The method also includes selectively removing the sidewall spacers to leave the first feature, the filler feature and the second feature spaced apart from each other, and etching the at least one layer using the first feature, the filler feature and the second feature as a mask.
摘要翻译：一种制造半导体器件的方法包括：在衬底上形成至少一个层;在至少一个层上形成至少两个可成像材料的间隔开的特征;在至少两个特征上形成侧壁间隔物并填充第一第一特征上的侧壁间隔物和具有填充物特征的第二特征上的第二侧壁间隔物。该方法还包括选择性地去除侧壁间隔物以使第一特征，填充特征和第二特征彼此间隔开，并且使用第一特征，填充特征和第二特征作为掩模来蚀刻至少一个层。

6. 发明申请

WO2009006175A3 TEST STRUCTURE, TEST STRUCTURE FORMATION AND MASK REUSE IN SEMICONDUCTOR PROCESSING 审中-公开
标题翻译：测试结构，半导体处理中的测试结构形成和掩蔽重现
公开(公告)号：WO2009006175A3
公开(公告)日：2009-03-12
申请号：PCT/US2008068273
申请日：2008-06-26
申请人： SANDISK 3D LLC , LI CALVIN K , CHEN YUNG-TIN , CHEN EN-SHING , POON PAUL WAI KIE
发明人： LI CALVIN K , CHEN YUNG-TIN , CHEN EN-SHING , POON PAUL WAI KIE
IPC分类号： H01L21/66 , G01R31/28
CPC分类号： H01L22/14 , G01R31/2884 , H01L2924/0002 , H01L2924/00
摘要： Different types of test structures are formed during semiconductor processing with a mask that is reused to form the same pattern in multiple layers. Reference marks that allow alignment accuracy to be checked are also formed with the mask. One type of test structure comprises features that are aligned with one another and that are formed from different layers. Other types of test structures comprise features formed from respective layers that are not aligned with other test structure features. The different types of test structures are formed with a single mask that is used in a manner that also allows alignment marks to be formed which do not interfere with one another as subsequent layers are patterned. The different types of test structures can provide insight into performance characteristics of different types of devices as the semiconductor process proceeds.
摘要翻译：不同类型的测试结构在半导体处理期间用掩模形成，该掩模被重复使用以在多层中形成相同的图案。也可以使用掩模形成允许校准精度的参考标记。一种类型的测试结构包括彼此对准并且由不同层形成的特征。其他类型的测试结构包括由不同于其它测试结构特征的各层形成的特征。不同类型的测试结构形成有单个掩模，其以允许形成对准标记的方式使用，其中随后的层被图案化而不会彼此干扰。不同类型的测试结构可以提供对半导体工艺进行中不同类型器件的性能特性的洞察。

7. 发明申请

WO2008083197A3 IMAGING POST STRUCTURES USING X AND Y DIPOLE OPTICS AND A SINGLE MASK 审中-公开
标题翻译：使用X和Y DIPOLE OPTICS和单个掩模成像后结构
公开(公告)号：WO2008083197A3
公开(公告)日：2008-10-02
申请号：PCT/US2007088901
申请日：2007-12-27
申请人： SANDISK CORP , CHEN YUNG-TIN , RADIGAN STEVEN J , POON PAUL , KONEVECKI MICHAEL W
发明人： CHEN YUNG-TIN , RADIGAN STEVEN J , POON PAUL , KONEVECKI MICHAEL W
IPC分类号： G03F7/20
CPC分类号： G03F7/70466 , G03F1/00 , G03F7/70425
摘要： A photolithographic method uses different exposure patterns. In one aspect, a photo-sensitive layer on a substrate is subject to a first exposure using optics having a first exposure pattern, such as an x-dipole pattern, followed by exposure using optics having a second exposure pattern, such as a y-dipole pattern, via the same mask, and with the photo-sensitive layer fixed relative to the mask. A 2-D post pattern with a pitch of approximately 70-150 nm may be formed in a layer beneath the photo-sensitive layer using 157-193 nm UV light, and hyper-numerical aperture optics, in one approach. In another aspect, hard baking is performed after both of the first and second exposures to erase a memory effect of photoresist after the first exposure. In another aspect, etching of a hard mask beneath the photo-sensitive layer is performed after both of the first and second exposures.
摘要翻译：光刻方法使用不同的曝光模式。在一个方面，使用具有第一曝光图案（例如x-偶极图案）的光学器件，然后使用具有第二曝光图案的光学元件例如y型曝光，使用基板上的感光层进行第一次曝光，偶极图案，通过相同的掩模，并且光敏层相对于掩模固定。在一种方法中，可以使用157-193nm UV光和超数值孔径光学器件在光敏层下方的层中形成具有约70-150nm间距的2-D柱状图案。另一方面，在第一曝光和第二次曝光之后进行硬烘烤，以擦除在第一曝光之后的光致抗蚀剂的记忆效应。在另一方面，在第一和第二次曝光之后进行光敏层下面的硬掩模的蚀刻。

8. 发明申请

WO2008083114A3 HYBRID MASK AND METHOD OF FORMING SAME 审中-公开
标题翻译：混合式面具及其制造方法
公开(公告)号：WO2008083114A3
公开(公告)日：2008-09-04
申请号：PCT/US2007088683
申请日：2007-12-21
申请人： SANDISK CORP , CHEN YUNG-TIN
发明人： CHEN YUNG-TIN
IPC分类号： G03F1/00 , G03F7/00 , G03F9/00
CPC分类号： G03F9/7076 , G03F1/36
摘要： A hybrid topography mask is designed for facilitating the fabrication of a semiconductor wafer. The hybrid mask includes a substrate having a light receiving surface. The light receiving surface defines a plane. Pluralities of pattern elements are etched into and out of the light receiving surface. Each of the plurality of pattern elements defines a pattern surface that is parallel to the light receiving surface. Pattern sides extend between the pattern elements and the light receiving surface. Each of the pattern sides extends perpendicularly between the light receiving surface and the pattern elements. The hybrid mask also includes a tapered sub-resolution assist element etched out of the light receiving surface to position the mask with respect to the semiconductor wafer. The tapered sub-resolution assist element is fabricated to avoid affecting any photoresist residue from the sub-resolution assist element's presence on the semiconductor wafer disposed adjacent the hybrid mask.
摘要翻译：混合形貌掩模设计用于促进半导体晶片的制造。混合掩模包括具有光接收表面的衬底。光接收表面限定了一个平面。多个图案元件蚀刻进入和离开光接收表面。多个图案元件中的每一个限定平行于光接收表面的图案表面。图案面在图案元件和光接收面之间延伸。每个图案侧在光接收表面和图案元件之间垂直地延伸。混合掩模还包括从光接收表面蚀刻掉的锥形亚分辨率辅助元件，以将掩模相对于半导体晶片定位。制造锥形亚分辨率辅助元件以避免影响亚分辨率辅助元件出现在邻近混合掩模设置的半导体晶片上的任何光刻胶残余物。

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