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1. 发明申请

WO2009015350A1 EPITAXIAL METHODS AND TEMPLATES GROWN BY THE METHODS 审中-公开
标题翻译：方法生成的外来方法和模板
公开(公告)号：WO2009015350A1
公开(公告)日：2009-01-29
申请号：PCT/US2008/071219
申请日：2008-07-25
申请人： S.O.I.TEC SILICON ON INSULATOR TECHNOLOGIES , ARIZONA BOARD OF REGENTS FOR AND ON BEHALF OF ARIZONA STATE UNIVERSITY , ARENA, Chantal , WERKHOVEN, Christiaan, J. , BERTRAM, JR., Ronald, Thomas , LINDOW, Ed , MAHAJAN, Subhash , DATTA, Ranjan , TRIVEDI, Rahul, Ajay , HAN, Ilsu
发明人： ARENA, Chantal , WERKHOVEN, Christiaan, J. , BERTRAM, JR., Ronald, Thomas , LINDOW, Ed , MAHAJAN, Subhash , DATTA, Ranjan , TRIVEDI, Rahul, Ajay , HAN, Ilsu
IPC分类号： H01L21/20
CPC分类号： H01L21/0237 , H01L21/02458 , H01L21/0254 , H01L21/02639 , H01L21/02642 , H01L21/02645 , H01L21/02647
摘要： This invention provides methods for fabricating substantially continuous layers of a group III nitride semiconductor material having low defect densities and optionally having a selected crystal polarity. The methods include epitaxial growth nucleating and/or seeding on the upper portions of a plurality of pillars/islands of a group III nitride material that are irregularly arranged on a template structure. The upper portions of the islands have low defect densities and optionally have a selected crystal polarity. The invention also includes template structures having a substantially continuous layer of a masking material through which emerge upper portions of the pillars/islands. The invention can be applied to a wide range of elemental and compound semiconductor materials.
摘要翻译：本发明提供了用于制造具有低缺陷密度且任选地具有所选晶体极性的III族氮化物半导体材料的基本上连续的层的方法。所述方法包括在不规则地布置在模板结构上的III族氮化物材料的多个柱/岛的上部上的外延生长成核和/或接种。岛的上部具有低缺陷密度，并且可选地具有选定的晶体极性。本发明还包括具有基本连续的掩模材料层的模板结构，通过该掩模材料出现柱/岛的上部。本发明可应用于各种元素和化合物半导体材料。

2. 发明申请

WO2009015337A1 METHODS FOR PRODUCING IMPROVED EPITAXIAL MATERIALS 审中-公开
标题翻译：生产改良外源材料的方法
公开(公告)号：WO2009015337A1
公开(公告)日：2009-01-29
申请号：PCT/US2008/071199
申请日：2008-07-25
申请人： S.O.I.TEC SILICON ON INSULATOR TECHNOLOGIES , ARIZONA BOARD OF REGENTS FOR AND ON BEHALF OF ARIZONA STATE UNIVERSITY , ARENA, Chantal , MAHAJAN, Subhash , DATTA, Ranjan
发明人： ARENA, Chantal , MAHAJAN, Subhash , DATTA, Ranjan
IPC分类号： H01L21/20
CPC分类号： H01L21/0242 , H01L21/0237 , H01L21/02521 , H01L21/0254 , H01L21/02639 , H01L21/02645 , H01L21/02647
摘要： This invention provides methods for fabricating substantially continuous layers of group III nitride semiconductor materials having low defect densities. The methods include epitaxial growth of nucleation layers on a base substrate, thermally treatment of said nucleation layer and epitaxial growth of a discontinuous masking layer. The methods outlined promote defect reduction through masking, annihilation and coalescence, therefore producing semiconductor structures with low defect densities. The invention can be applied to a wide range of semiconductor materials, both elemental semiconductors, e.g., combinations of Si (silicon) with strained Si (sSi) and/or Ge (germanium), and compound semiconductors, e.g., group II-VI and group III-V compound semiconductor materials.
摘要翻译：本发明提供了用于制造具有低缺陷密度的III族氮化物半导体材料的基本上连续的层的方法。所述方法包括在基底基板上成核层的外延生长，所述成核层的热处理和不连续掩模层的外延生长。所概述的方法通过掩蔽，湮灭和聚结来促进缺陷减少，因此产生具有低缺陷密度的半导体结构。本发明可以应用于宽范围的半导体材料，包括元素半导体，例如Si（硅）与应变Si（sSi）和/或Ge（锗）的组合，以及化合物半导体，例如II-VI族和 III-V族化合物半导体材料。

3. 发明申请

WO2009139793A1 METHODS FOR IMPROVING THE QUALITY OF GROUP III-NITRIDE MATERIALS AND STRUCTURES PRODUCED BY THE METHODS 审中-公开
标题翻译：提高Ⅲ类氮素材料质量和方法生产的结构的方法
公开(公告)号：WO2009139793A1
公开(公告)日：2009-11-19
申请号：PCT/US2008/083630
申请日：2008-11-14
申请人： S.O.I.TEC SILICON ON INSULATOR TECHNOLOGIES , ARIZONA BOARD OF REGENTS FOR AND ON BEHALF OF ARIZONA STATE UNIVERSITY , ARENA, Chantal , MAHAJAN, Subhash
发明人： ARENA, Chantal , MAHAJAN, Subhash
IPC分类号： H01L21/20
CPC分类号： H01L21/0254 , H01L21/0242 , H01L21/02458 , H01L21/02639 , H01L21/02647
摘要： The invention provides methods which can be applied during the epitaxial growth of two or more layers of Group Ill-nitride semiconductor materials so that the qualities of successive layer are successively improved. In preferred embodiments, surface defects interact with a protective layer of a protective material to form amorphous complex regions capable of preventing the further propagation of defects and dislocations. The invention also includes semiconductor structures fabricated by these methods.
摘要翻译：本发明提供了可以在两层或更多层III族氮化物半导体材料的外延生长期间应用的方法，使得连续层的质量连续改善。在优选的实施方案中，表面缺陷与保护材料的保护层相互作用以形成能够防止缺陷和位错进一步扩散的非晶复合区。本发明还包括通过这些方法制造的半导体结构。

4. 发明申请

WO2011123303A1 III-V SEMICONDUCTOR STRUCTURES AND METHODS FOR FORMING THE SAME 审中-公开
标题翻译： III-V族半导体结构及其形成方法
公开(公告)号：WO2011123303A1
公开(公告)日：2011-10-06
申请号：PCT/US2011/029589
申请日：2011-03-23
申请人： S.O.I. TEC SILICON ON INSULATOR TECHNOLOGIES , ARIZONA BOARD OF REGENTS FOR AND on behalf of ARIZONA STATE UNIVERSITY , LINDOW, Ed , ARENA, Chantal , BERTRAM, Ronald , DATTA, Ranjan , MAHAJAN, Subhash
发明人： LINDOW, Ed , ARENA, Chantal , BERTRAM, Ronald , DATTA, Ranjan , MAHAJAN, Subhash
IPC分类号： H01L21/203 , H01L21/205 , H01L21/02
CPC分类号： H01L29/2003 , H01L21/0237 , H01L21/02455 , H01L21/02458 , H01L21/02538 , H01L21/0254 , H01L21/02617 , H01L21/0262
摘要： Embodiments of the invention relate to methods of fabricating semiconductor structures, and to semiconductor structures fabricated by such methods. In some embodiments, the methods may be used to fabricate semiconductor structures of III-V materials, such as InGaN. A semiconductor layer is fabricated by growing sublayers using differing sets of growth conditions to improve the homogeneity of the resulting layer, to improve a surface roughness of the resulting layer, and/or to enable the layer to be grown to an increased thickness without the onset of strain relaxation.
摘要翻译：本发明的实施例涉及制造半导体结构的方法以及通过这些方法制造的半导体结构。在一些实施例中，该方法可用于制造诸如InGaN的III-V材料的半导体结构。通过使用不同的生长条件生长子层来制造半导体层，以改善所得层的均匀性，改善所得层的表面粗糙度和/或使层能够生长到增加的厚度而不发生的应变松弛。

5. 发明申请

WO2012069530A1 METHODS FOR FORMING GROUP III-NITRIDE MATERIALS AND STRUCTURES FORMED BY SUCH METHODS 审中-公开
标题翻译：形成III类氮化物材料的方法和通过这些方法形成的结构
公开(公告)号：WO2012069530A1
公开(公告)日：2012-05-31
申请号：PCT/EP2011/070794
申请日：2011-11-23
申请人： SOITEC , ARIZONA BOARD OF REGENTS FOR AND ON BEHALF OF ARIZONA STATE UNIVERSITY , ARENA, Chantal , BERTRAM JR., Ronald Thomas , LINDOW, Ed , MAHAJAN, Subhash , MENG, Fanyu
发明人： ARENA, Chantal , BERTRAM JR., Ronald Thomas , LINDOW, Ed , MAHAJAN, Subhash , MENG, Fanyu
IPC分类号： C30B25/02 , C30B29/40
CPC分类号： H01L21/02104 , C30B25/02 , C30B29/403 , C30B29/406 , H01L29/2003
摘要： Embodiments of the invention include methods for forming Group III-nitride semiconductor structure using a halide vapor phase epitaxy (HVPE) process. The methods include forming a continuous Group III-nitride nucleation layer on a surface of a non-native growth substrate, the continuous Group III-nitride nucleation layer concealing the upper surface of the non-native growth substrate. Forming the continuous Group III- nitride nucleation layer may include forming a Group III-nitride layer and thermally treating said Group III-nitride layer. Methods may further include forming a further Group III-nitride layer upon the continuous Group III-nitride nucleation layer.
摘要翻译：本发明的实施方案包括使用卤化物气相外延（HVPE）方法形成III族氮化物半导体结构的方法。所述方法包括在非天然生长衬底的表面上形成连续的III族氮化物成核层，所述连续III族氮化物成核层隐藏非天然生长衬底的上表面。形成连续的III族氮化物成核层可以包括形成III族氮化物层并热处理所述III族氮化物层。方法还可以包括在连续的III族氮化物成核层上形成另外的III族氮化物层。

6. 发明申请

WO2012069521A1 IMPROVED TEMPLATE LAYERS FOR HETEROEPITAXIAL DEPOSITION OF III NITRIDE SEMICONDUCTOR MATERIALS USING HVPE PROCESSES 审中-公开
标题翻译：使用HVPE工艺改进III型氮化物半导体材料的异相沉积模板
公开(公告)号：WO2012069521A1
公开(公告)日：2012-05-31
申请号：PCT/EP2011/070772
申请日：2011-11-23
申请人： SOITEC , ARIZONA BOARD OF REGENTS FOR AND ON BEHALF OF ARIZONA STATE UNIVERSITY , ARENA, Chantal , BERTRAM JR, Ronald Thomas , LINDOW, Ed , MAHAJAN, Subhash , HAN, Ilsu
发明人： ARENA, Chantal , BERTRAM JR, Ronald Thomas , LINDOW, Ed , MAHAJAN, Subhash , HAN, Ilsu
IPC分类号： H01L21/02
CPC分类号： H01L29/0665 , C30B25/183 , C30B29/403 , H01L21/0242 , H01L21/02458 , H01L21/02513 , H01L21/0254 , H01L21/0262 , H01L21/02667
摘要： Methods of depositing ΙII-nitride semiconductor materials on substrates include depositing a layer of ΠΙ-nitride semiconductor material on a surface of a substrate in a nucleation HVPE process stage to form a nucleation layer having a microstructure comprising at least some amorphous ΙII-nitride semiconductor material. The nucleation layer may be annealed to form crystalline islands of epitaxial nucleation material on the surface of the substrate. The islands of epitaxial nucleation material may be grown and coalesced in a coalescence HVPE process stage to form a nucleation template layer of the epitaxial nucleation material. The nucleation template layer may at least substantially cover the surface of the substrate. Additional Ill-nitride semiconductor material may be deposited over the nucleation template layer of the epitaxial nucleation material in an additional HVPE process stage. Final and intermediate structures comprising ΙII-nitride semiconductor material are formed by such methods.
摘要翻译：在衬底上沉积π-N族半导体材料的方法包括在成核HVPE工艺阶段中在衬底的表面上沉积一层氮化物半导体材料，以形成具有微结构的成核层，所述微结构包含至少一些非晶态II- 氮化物半导体材料。可以将成核层退火以在衬底的表面上形成外延成核材料的晶体岛。外延成核材料岛可以在聚结HVPE工艺阶段中生长和聚结，以形成外延成核材料的成核模板层。成核模板层可以至少基本上覆盖基底的表面。附加的III族氮化物半导体材料可以在另外的HVPE工艺阶段中沉积在外延成核材料的成核模板层上。通过这种方法形成包含α-N族半导体材料的最终和中间结构。

7. 发明申请

WO2008141324A2 METHODS FOR IMPROVING THE QUALITY OF EPITAXIALLY-GROWN SEMICONDUCTOR MATERIALS 审中-公开
标题翻译：改善外延生长半导体材料质量的方法
公开(公告)号：WO2008141324A2
公开(公告)日：2008-11-20
申请号：PCT/US2008/063567
申请日：2008-05-14
申请人： S.O.I.TEC SILICON ON INSULATOR TECHNOLOGIES , THE ARIZONA BOARD OF REGENTS, A BODY CORPORATE OF THE STATE OF ARIZONA ACTING FOR AND ON BEHALF OF ARIZONA STATE UNIVERSITY , ARENA, Chantal , MAHAJAN, Subhash , HAN, Ilsu
发明人： ARENA, Chantal , MAHAJAN, Subhash , HAN, Ilsu
IPC分类号： H01L21/20
CPC分类号： H01L21/02458 , H01L21/0254 , H01L21/02639 , H01L21/02647
摘要： The invention provides methods which can be applied during the epitaxial growth of two or more layers of semiconductor materials so that the qualities of successive layer are successively improved. In preferred embodiments, surface defects present in one epitaxial layer are capped with a masking material. A following layer is then grown so it extends laterally above the caps according to the known phenomena of epitaxial lateral overgrowth. The methods of the invention can be repeated by capping surface defects in the following layer and then epitaxially growing a second following layer according to ELO. The invention also includes semiconductor structures fabricated by these methods.
摘要翻译：本发明提供了可以在两层或更多层半导体材料的外延生长期间应用的方法，使得连续层的质量连续改善。在优选实施例中，存在于一个外延层中的表面缺陷用掩模材料封盖。然后根据已知的外延横向过度生长现象，生长随后的层，使其沿盖子横向延伸。本发明的方法可以通过覆盖下一层中的表面缺陷，然后根据ELO外延生长第二个后续层来重复。本发明还包括通过这些方法制造的半导体结构。

8. 发明申请

WO2010112540A1 EPITAXIAL METHODS AND STRUCTURES FOR REDUCING SURFACE DISLOCATION DENSITY IN SEMICONDUCTOR MATERIALS 审中-公开
标题翻译：用于减少半导体材料表面偏离密度的外延方法和结构
公开(公告)号：WO2010112540A1
公开(公告)日：2010-10-07
申请号：PCT/EP2010/054276
申请日：2010-03-31
申请人： S.O.I.TEC SILICON ON INSULATOR TECHNOLOGIES , COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES , ARENA, Chantal , CLAVELIER, Laurent , RABAROT, Marc
发明人： ARENA, Chantal , CLAVELIER, Laurent , RABAROT, Marc
IPC分类号： H01L21/20 , H01L21/02
CPC分类号： H01L21/02639 , H01L21/0237 , H01L21/0242 , H01L21/02458 , H01L21/0254
摘要： The invention provides methods and structures for reducing surface dislocations of a semiconductor layer, and can be employed during the epitaxial growth of semiconductor structures and layers comprising Ill-nitride materials. Embodiments involve the formation of a plurality of dislocation pit plugs to prevent propagation of dislocations from an underlying layer of material into a following semiconductor layer of material.
摘要翻译：本发明提供了用于减少半导体层表面位错的方法和结构，并且可以在半导体结构和包含III族氮化物材料的层的外延生长期间使用。实施例涉及形成多个位错坑塞，以防止位错从材料的下层扩散到随后的材料半导体层中。

9. 发明申请

WO2008130448A2 TEMPERATURE-CONTROLLED PURGE GATE VALVE FOR CHEMICAL VAPOR DEPOSITION CHAMBER 审中-公开
标题翻译：化学蒸气沉积室的温度控制浇口阀
公开(公告)号：WO2008130448A2
公开(公告)日：2008-10-30
申请号：PCT/US2007/084930
申请日：2007-11-16
申请人： S.O.I.TEC SILICON ON INSULATOR TECHNOLOGIES , ARENA, Chantal , WERKHOVEN, Christiaan
发明人： ARENA, Chantal , WERKHOVEN, Christiaan
IPC分类号： H01L21/20
CPC分类号： C30B25/14 , C23C16/303 , C23C16/4401 , C23C16/4412 , C23C16/481 , C23C16/54 , C30B29/403 , H01L21/0254 , H01L21/0262 , Y10T117/10 , Y10T117/1008
摘要： The present invention relates to methods and apparatus that are optimized for producing Group III-N (nitrogen) compound semiconductor wafers and specifically for producing GaN wafers. Specifically, the methods relate to substantially preventing the formation of unwanted materials on an isolation valve fixture within a chemical vapor deposition (CVD) reactor. In particular, the invention provides apparatus and methods for limiting deposition/condensation of GaCl 3 and reaction by-products on an isolation valve that is used in the system and method for forming a monocrystalline Group III - V semiconductor material by reacting an amount of a gaseous Group III precursor as one reactant with an amount of a gaseous Group V component as another reactant in a reaction chamber.
摘要翻译：本发明涉及为生产III-N（氮）化合物半导体晶片而专门用于生产GaN晶片的方法和装置。具体地说，这些方法涉及基本上防止在化学气相沉积（CVD）反应器内的隔离阀装置上形成不需要的材料。特别地，本发明提供了用于限制GaCl 3和反应副产物在用于形成单晶III-V族半导体的系统和方法的隔离阀上的沉积/冷凝的装置和方法材料通过使一定量的气态III族前体作为一种反应物与一定量的气态V族组分作为反应室中的另一种反应物反应。

10. 发明申请

WO2008127425A2 ABATEMENT OF REACTION GASES FROM GALLIUM NITRIDE DEPOSITION 审中-公开
标题翻译：硝酸镓沉积反应气体的减少
公开(公告)号：WO2008127425A2
公开(公告)日：2008-10-23
申请号：PCT/US2007/084839
申请日：2007-11-15
申请人： S.O.I.TEC SILICON ON INSULATOR TECHNOLOGIES , ARENA, Chantal , WERKHOVEN, Christiaan
发明人： ARENA, Chantal , WERKHOVEN, Christiaan
IPC分类号： B32B15/16
CPC分类号： C30B25/14 , C23C16/4412 , C30B25/08 , C30B25/165 , C30B29/40 , C30B29/403
摘要： Methods for the sustained, high-volume production of Group III-V compound semiconductor material suitable for fabrication of optic and electronic components, for use as substrates for epitaxial deposition, or for wafers. The equipment and methods are optimized for producing Group III-N (nitrogen) compound semiconductor wafers and specifically for producing GaN wafers. The method includes reacting an amount of a gaseous Group III precursor as one reactant with an amount of a gaseous Group V component as another reactant in a reaction chamber to form the semiconductor material; removing exhaust gases including unreacted Group III precursor, unreacted Group V component and reaction byproducts; and heating the exhaust gases to a temperature sufficient to reduce condensation thereof and enhance manufacture of the semiconductor material. Advantageously, the exhaust gases are heated to sufficiently avoid condensation to facilitate sustained high volume manufacture of the semiconductor material.
摘要翻译：用于持续大批量生产III-V族化合物半导体材料的方法，该III-V族化合物半导体材料适用于制造光学和电子组件，用作外延沉积的基底或晶片。该设备和方法针对生产III-N族（氮）化合物半导体晶圆并专门用于生产GaN晶圆进行了优化。该方法包括使一定量的作为一种反应物的气态III族前体与作为另一反应物的一定量气态V族成分在反应室中反应以形成半导体材料; 除去包括未反应的III族前体，未反应的V族组分和反应副产物的废气; 并将废气加热到足以减少其冷凝的温度并增强半导体材料的制造。有利的是，废气被加热以充分避免冷凝，以促进半导体材料的持续大批量生产。

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