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1. 发明申请

WO2010144862A2 PRODUCTION OF ADIPIC ACID AND DERIVATIVES FROM CARBOHYDRATE-CONTAINING MATERIALS 审中-公开
标题翻译：从含有碳酸氢盐的材料中生产二酸和衍生物
公开(公告)号：WO2010144862A2
公开(公告)日：2010-12-16
申请号：PCT/US2010038408
申请日：2010-06-11
申请人： RENNOVIA INC , BOUSSIE THOMAS R , DIAS ERIC L , FRESCO ZACHARY M , MURPHY VINCENT J , SHOEMAKER JAMES , ARCHER RAYMOND , JIANG HONG
发明人： BOUSSIE THOMAS R , DIAS ERIC L , FRESCO ZACHARY M , MURPHY VINCENT J , SHOEMAKER JAMES , ARCHER RAYMOND , JIANG HONG
IPC分类号： C07C51/235 , C07C29/147 , C07C51/377 , C07C209/00 , C07C211/12 , C07C253/00 , C07D223/10 , C08G63/16 , C08G69/26
CPC分类号： C07C209/00 , C07B2200/07 , C07C51/235 , C07C51/377 , C07C51/412 , C07C253/00 , C07D201/08 , C07D223/10 , C07D309/30 , C08G63/16 , C08G69/14 , C08G69/26 , C08G69/36 , C07C55/14 , C07C211/12 , C07C255/04
摘要： The present invention generally relates to processes for the chemocatalytic conversion of a glucose source to an adipic acid product. The present invention includes processes for the conversion of glucose to an adipic acid product via glucaric acid or derivatives thereof. The present invention also includes processes comprising catalytic oxidation of glucose to glucaric acid or derivative thereof and processes comprising the catalytic hydrodeoxygenation of glucaric acid or derivatives thereof to an adipic acid product. The present invention also includes products produced from adipic acid product and processes for the production thereof from such adipic acid product.
摘要翻译：本发明一般涉及将葡萄糖源化学转化为己二酸产物的方法。本发明包括通过葡糖二酸或其衍生物将葡萄糖转化成己二酸产物的方法。本发明还包括将葡萄糖催化氧化成葡糖二酸或其衍生物的方法和包括将葡糖二酸或其衍生物催化加氢脱氧至己二酸产物的方法。本发明还包括由己二酸产物生产的产品和由己二酸产物生产的产品。

2. 发明申请

WO2007041146A3 APPARATUS AND METHOD FOR SWITCHING BETWEEN BUFFERS USING A VIDEO FRAME BUFFER FLIP QUEUE 审中-公开
标题翻译：使用视频帧缓冲器翻转队列在缓冲区之间切换的装置和方法
公开(公告)号：WO2007041146A3
公开(公告)日：2007-05-31
申请号：PCT/US2006037632
申请日：2006-09-26
申请人： INTEL CORP , JIANG HONG
发明人： JIANG HONG
IPC分类号： G09G5/399
CPC分类号： G09G5/399 , G09G5/12
摘要： A method, apparatus, and system are described in which a signal is generated to inhibit the execution of flip commands that cause a flip between buffers of a frame buffer. One or more of the flip commands and their associated instruction pointers may be preloaded into a frame buffer flip queue prior to removing the signal inhibiting the execution of the flip commands.
摘要翻译：描述了一种方法，装置和系统，其中产生信号以禁止执行在缓冲器的缓冲器之间翻转的翻转命令。可以在去除禁止执行翻转命令的信号之前将一个或多个翻转命令及其相关联的指令指针预加载到帧缓冲器翻转队列中。

3. 发明申请

WO2006066262A2 EVALUTATION UNIT FOR SINGLE INSTRUCTION, MULTIPLE DATA EXECUTION ENGINE FLAG REGISTERS 审中-公开
标题翻译：单个指令评估单元，多个数据执行引擎标志寄存器
公开(公告)号：WO2006066262A2
公开(公告)日：2006-06-22
申请号：PCT/US2005046321
申请日：2005-12-15
申请人： INTEL CORP , DWYER MICHAEL , JIANG HONG
发明人： DWYER MICHAEL , JIANG HONG
IPC分类号： G06F9/38
CPC分类号： G06F9/30094 , G06F9/30036 , G06F9/30101 , G06F9/3885 , G06F9/3887
摘要： According to some embodiments, a evaluation unit may be provided for Single Instruction, Multiple Data (SIMD) execution engine flag registers. For example, a horizontal evaluation unit might perform evaluation operation across multiple vectors being processed by the SIMD execution engine. According to some embodiments, a vertical evaluation unit might perform evaluation operations across multiple flag registers.
摘要翻译：根据一些实施例，可以为单指令，多数据（SIMD）执行引擎标志寄存器提供评估单元。例如，水平评估单元可以在由SIMD执行引擎处理的多个向量之间执行评估操作。根据一些实施例，垂直评估单元可以在多个标志寄存器之间执行评估操作。

4. 发明申请

WO2006012064A2 THREAD TO THREAD COMMUNICATION 审中-公开
标题翻译：线程通信
公开(公告)号：WO2006012064A2
公开(公告)日：2006-02-02
申请号：PCT/US2005021582
申请日：2005-06-17
申请人： INTEL CORP , JIANG HONG , DWYER MICHAEL
发明人： JIANG HONG , DWYER MICHAEL
IPC分类号： G06F9/40 , G06F9/00 , G06F9/46
CPC分类号： G06F9/542
摘要： Thread to thread communication is provided. A first thread registers with a gateway for receiving communication. Registration includes identifying a location for receiving messages. The gateway maps message payloads received from second threads to the location of the first thread. The first thread detects a payload in the location and consumes it for processing.
摘要翻译：提供线程到线程通信。第一个线程向网关注册以接收通信。注册包括识别接收消息的位置。网关将从第二线程接收的消息有效载荷映射到第一线程的位置。第一个线程检测位置中的有效负载并将其消耗用于处理。

5. 发明申请

WO0069162A2 A METHOD AND APPARATUS FOR VIDEO DECODING 审中-公开
标题翻译：一种用于视频解码的方法和装置
公开(公告)号：WO0069162A2
公开(公告)日：2000-11-16
申请号：PCT/US0011788
申请日：2000-05-01
申请人： INTEL CORP , JIANG HONG
发明人： JIANG HONG
IPC分类号： H04N7/26 , H04N7/50 , H04N
CPC分类号： H04N19/42 , H04N19/61
摘要： A method and apparatus for decoding compressed video, the decoding of compressed video comprising the steps of decoding a first portion of a first frame to produce a first data; generating a first signal; performing motion compensation using the first data in response to the first signal; generating a second signal; decoding a second portion of the first frame to produce a second data in response to the second signal; generating a third signal; and performing motion compensation using the second data in response to the third signal.
摘要翻译：一种用于对压缩视频进行解码的方法和装置，压缩视频的解码包括以下步骤：解码第一帧的第一部分以产生第一数据; 产生第一信号; 使用所述第一数据响应于所述第一信号执行运动补偿; 产生第二信号; 解码第一帧的第二部分以响应于第二信号产生第二数据; 产生第三信号; 以及响应于所述第三信号使用所述第二数据执行运动补偿。

6. 发明申请

WO2006124299A3 PARALLEL EXECUTION OF MEDIA ENCODING USING MULTI-THREADED SINGLE INSTRUCTION MULTIPLE DATA PROCESSING 审中-公开
标题翻译：使用多线程单指令多媒体数据处理的媒体编码并行执行
公开(公告)号：WO2006124299A3
公开(公告)日：2007-06-28
申请号：PCT/US2006017047
申请日：2006-05-02
申请人： INTEL CORP , JIANG HONG
发明人： JIANG HONG
IPC分类号： G06F15/80 , H04N7/26
CPC分类号： H04N19/176 , H04N19/436 , H04N19/61
摘要： An apparatus, system, method, and article for parallel execution of media encoding using single instruction multiple data processing are described. The apparatus may include a media processing node to perform single instruction multiple data processing of macroblock data. The macroblock data may include coefficients for multiple blocks of a macroblock. The media processing node may include an encoding module to generate multiple flag words associated with multiple blocks from the macroblock data and to determine run values for multiple blocks in parallel from the flag words. Other embodiments are described and claimed.
摘要翻译：描述了使用单指令多数据处理并行执行媒体编码的装置，系统，方法和文章。该装置可以包括媒体处理节点，以对宏块数据执行单指令多重数据处理。宏块数据可以包括用于宏块的多个块的系数。媒体处理节点可以包括编码模块，用于从宏块数据生成与多个块相关联的多个标志字，并从标志字并行确定多个块的运行值。描述和要求保护其他实施例。

7. 发明申请

WO2005066768A3 BEHAVIORAL MODEL BASED MULTI-THREADED ARCHITECTURE 审中-公开
标题翻译：基于行为模型的多层建筑
公开(公告)号：WO2005066768A3
公开(公告)日：2007-02-22
申请号：PCT/US2004043395
申请日：2004-12-23
申请人： INTEL CORP , JIANG HONG , PIAZZA THOMAS A
发明人： JIANG HONG , PIAZZA THOMAS A
IPC分类号： G06F9/46 , G06F9/38 , G06F9/48
CPC分类号： G06F9/52 , G06F9/3004 , G06F9/30087 , G06F9/4843
摘要： Multiple parallel passive threads of instructions coordinate access to shared resources using "active" and "proactive" semaphores. The active semaphores send messages to execution and/or control circuitry to cause the state of a thread to change. A thread can be placed in an inactive state by a thread scheduler in response to an unresolved dependency, which can be indicated by a semaphore. A thread state variable corresponding to the dependency is used to indicate that the thread is in inactive mode. When the dependency is resolved a message is passed to control circuitry causing the dependency variable to be cleared. In response to the cleared dependency variable the thread is placed in an active state. Execution can proceed on the threads in the active state. A proactive semaphore operates in a similar manner except that the semaphore is configured by the thread dispatcher before or after the thread is dispatched to the execution circuitry for execution.
摘要翻译：指令的多个并行被动线程使用“主动”和“主动”信号量协调对共享资源的访问。主动信号量将消息发送到执行和/或控制电路，以使线程的状态发生变化。线程调度程序可以响应未解决的依赖关系将线程置于无效状态，这可以由信号量指示。与依赖关系对应的线程状态变量用于指示线程处于非活动模式。当依赖关系被解析时，消息被传递给控制电路，导致依赖变量被清除。响应于清除的依赖变量，线程处于活动状态。处于活动状态的线程可执行。主动信号量以类似的方式运行，除了信号量由线程分派器在线程发送到执行电路执行之前或之后配置。

9. 发明申请

WO2006044978A2 LOOPING INSTRUCTIONS FOR A SINGLE INSTRUCTION, MULTIPLE DATA EXECUTION ENGINE 审中-公开
标题翻译：单次指令的循环指令，多个数据执行引擎
公开(公告)号：WO2006044978A2
公开(公告)日：2006-04-27
申请号：PCT/US2005037625
申请日：2005-10-13
申请人： INTEL CORP , DWYER MICHAEL , JIANG HONG
发明人： DWYER MICHAEL , JIANG HONG
IPC分类号： G06F9/32
CPC分类号： G06F9/30058 , G06F9/325 , G06F9/3885 , G06F9/3887
摘要： According to some embodiments, looping instructions are provided for a Single Instruction. Multiple Data (SIMD) execution engine. For example, when a first loop instruction is received at an execution engine information in an n-bit loop mask register may be copied to an n-bit wide, m-entry deep loop stack.
摘要翻译：根据一些实施例，为单个指令提供循环指令。多数据（SIMD）执行引擎。例如，当在执行引擎处接收到第一循环指令时，n位循环屏蔽寄存器中的信息可被复制到n位宽m入口深循环栈。

10. 发明申请

WO2006012070A3 CONDITIONAL INSTRUCTION FOR A SINGLE INSTRUCTION, MULTIPLE DATA EXECUTION ENGINE 审中-公开
标题翻译：一个指令，多个数据执行机构的条件指令
公开(公告)号：WO2006012070A3
公开(公告)日：2006-05-26
申请号：PCT/US2005021604
申请日：2005-06-17
申请人： INTEL CORP , DWYER MICHAEL , JIANG HONG , PIAZZA THOMAS
发明人： DWYER MICHAEL , JIANG HONG , PIAZZA THOMAS
IPC分类号： G06F9/38 , G06F15/00
CPC分类号： G06F9/3887 , G06F9/30036 , G06F9/30072 , G06F9/3885
摘要： According to some embodiments, a conditional Single Instruction, Multiple Data instruction is provided. For example, a first conditional instruction may be received at an n-channel SIMD execution engine. The first conditional instruction may be evaluated based on multiple channels of associated data, and the result of the evaluation may be stored in an n-bit conditional mask register. A second conditional instruction may then be received at the execution engine and the result may be copied from the conditional mask register to an n-bit wide, m-entry deep conditional stack.
摘要翻译：根据一些实施例，提供了条件单指令，多数据指令。例如，可以在n信道SIMD执行引擎处接收第一条件指令。可以基于相关数据的多个信道来评估第一条件指令，并且可以将评估结果存储在n位条件掩码寄存器中。然后可以在执行引擎处接收第二条件指令，并且可以将结果从条件屏蔽寄存器复制到n位宽的m入口深条件堆栈。

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