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1. 发明申请

WO2012158544A1 ELECTROMECHANICAL SYSTEMS OSCILLATOR WITH PIEZOELECTRIC CONTOUR MODE RESONATOR FOR MULTIPLE FREQUENCY GENERATION 审中-公开
标题翻译：电磁系统振荡器，具有用于多个频率发生的压电轮廓模式谐振器
公开(公告)号：WO2012158544A1
公开(公告)日：2012-11-22
申请号：PCT/US2012/037599
申请日：2012-05-11
申请人： QUALCOMM MEMS TECHNOLOGIES, INC. , KIM, Jonghae , LAN, Je-Hsiung , YUN, Changhan , LO, Chi Shun , NOWAK, Matthew
发明人： KIM, Jonghae , LAN, Je-Hsiung , YUN, Changhan , LO, Chi Shun , NOWAK, Matthew
IPC分类号： H03H9/24
CPC分类号： H03H9/2426 , H03H9/02228 , H03H9/2405 , H03H9/462 , H03H2009/241
摘要： Electromechanical systems resonator structures, devices, circuits, and systems are disclosed. In one aspect, an oscillator (1200) includes an active component (1204) and a passive component (1212) connected in a feedback configuration. The passive component (1212) includes one or more contour mode resonators (CMR). A CMR includes a piezoelectric layer (208) disposed between a first conductive layer (104a, 104b) and a second conductive layer (204a, 204b). The conductive layers include an input electrode and an output electrode. The passive component (1212) is configured to output a first resonant frequency and a second resonant frequency, which is an odd integer harmonic of the first resonant frequency. The active component (1204) is configured to output a signal including the first resonant frequency and the second resonant frequency. This output signal can be a substantially square wave signal, which can serve as a clock in various applications.
摘要翻译：公开了机电系统谐振器结构，器件，电路和系统。在一个方面，振荡器（1200）包括以反馈配置连接的有源部件（1204）和无源部件（1212）。无源部件（1212）包括一个或多个轮廓模式谐振器（CMR）。 CMR包括设置在第一导电层（104a，104b）和第二导电层（204a，204b）之间的压电层（208）。导电层包括输入电极和输出电极。无源部件（1212）被配置为输出第一谐振频率和第二谐振频率，其是第一谐振频率的奇整数谐波。有源部件（1204）被配置为输出包括第一谐振频率和第二谐振频率的信号。该输出信号可以是基本上为方波信号，其可以用作各种应用中的时钟。

2. 发明申请

WO2012148712A1 PIEZOELECTRIC RESONATORS AND FABRICATION PROCESSES 审中-公开
标题翻译：压电谐振器和制造工艺
公开(公告)号：WO2012148712A1
公开(公告)日：2012-11-01
申请号：PCT/US2012/033609
申请日：2012-04-13
申请人： QUALCOMM MEMS TECHNOLOGIES, INC. , LAN, Je-Hsiung , PARK, Sang-June , KIM, Jonghae , GOUSEV, Evgeni , NOWAK, Matthew , STEPHANOU, Philip J. , BLACK, Justin , PETERSEN, Kurt , GANAPATHI, Srinivasan
发明人： LAN, Je-Hsiung , PARK, Sang-June , KIM, Jonghae , GOUSEV, Evgeni , NOWAK, Matthew , STEPHANOU, Philip J. , BLACK, Justin , PETERSEN, Kurt , GANAPATHI, Srinivasan
IPC分类号： H03H3/007 , H03H9/24
CPC分类号： H03H3/0072 , H03H9/2447 , Y10T29/42
摘要： This disclosure provides implementations of electromechanical systems resonator structures, devices, apparatus, systems, and related processes. In one aspect, a sacrificial layer is deposited on an insulating substrate. A lower electrode layer is formed proximate the sacrificial layer. A piezoelectric layer is deposited on the lower electrode layer. An upper electrode layer is formed on the piezoelectric layer. At least a portion of the sacrificial layer is removed to define a cavity such that at least a portion of the lower electrode layer is spaced apart from the insulating substrate.
摘要翻译：本公开提供了机电系统谐振器结构，设备，装置，系统和相关过程的实现。在一个方面，牺牲层沉积在绝缘衬底上。在牺牲层附近形成下电极层。压电层沉积在下电极层上。在压电层上形成上电极层。去除牺牲层的至少一部分以限定空腔，使得下电极层的至少一部分与绝缘基板间隔开。

3. 发明申请

WO2011025897A1 TRANSFORMER SIGNAL COUPLING FOR FLIP-CHIP INTEGRATION 审中-公开
标题翻译：用于片式芯片整合的变压器信号耦合
公开(公告)号：WO2011025897A1
公开(公告)日：2011-03-03
申请号：PCT/US2010/046862
申请日：2010-08-26
申请人： QUALCOMM Incorporated , KIM, Jonghae , WANG, Feng , NOWAK, Matthew
发明人： KIM, Jonghae , WANG, Feng , NOWAK, Matthew
IPC分类号： H01L23/64 , H01L23/66 , H01L23/522
CPC分类号： H01L28/10 , H01F27/2804 , H01L21/50 , H01L23/5227 , H01L23/645 , H01L23/66 , H01L24/48 , H01L2223/6644 , H01L2223/6655 , H01L2224/16 , H01L2224/48091 , H01L2224/48227 , H01L2924/00014 , H01L2924/1305 , H01L2924/14 , H01L2924/1461 , H01L2924/19015 , H01L2924/19041 , H01L2924/19103 , H01L2924/30107 , H01L2924/3011 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： Methods and apparatuses for transformer signal coupling for flip-chip circuit assemblies are presented. A device for coupling dies in flip-chip circuit assembly may include a first die associated with a first fabrication process and a first inductor physically coupled to the first die, where the first inductor receives an RF input signal. The device may further include a second die associated with a second fabrication process, and a second inductor physically coupled to the second die, where the second inductor is positioned so the first inductor can inductively couple the RF signal in the second inductor. A method for providing an inductive coupling between dies may include fabricating a first inductor on a first die using a passive process, fabricating a second inductor on a second die using a semiconductor process, and assembling each die so the first and second inductor are configured as a transformer.
摘要翻译：提出了用于倒装芯片电路组件的变压器信号耦合的方法和装置。用于在倒装芯片电路组件中耦合管芯的装置可以包括与第一制造工艺相关联的第一管芯和物理耦合到第一管芯的第一电感器，其中第一电感器接收RF输入信号。该器件还可以包括与第二制造工艺相关联的第二管芯，以及物理耦合到第二管芯的第二电感器，其中第二电感器被定位成使得第一电感器可感应地耦合第二电感器中的RF信号。用于提供管芯之间的感应耦合的方法可以包括使用无源工艺在第一管芯上制造第一电感器，使用半导体工艺在第二管芯上制造第二电感器，以及组装每个管芯，使得第一和第二电感器被配置为变压器

4. 发明申请

WO2011044392A1 THREE DIMENSIONAL INDUCTOR AND TRANSFORMER 审中-公开
标题翻译：三维电感和变压器
公开(公告)号：WO2011044392A1
公开(公告)日：2011-04-14
申请号：PCT/US2010/051868
申请日：2010-10-07
申请人： QUALCOMM Incorporated , KIM, Jonghae , GU, Shiqun , HENDERSON, Brian Matthew , TOMS, Thomas R. , CHUA-EOAN, Lew G. , BAZARJANI, Seyfollah S. , NOWAK, Matthew
发明人： KIM, Jonghae , GU, Shiqun , HENDERSON, Brian Matthew , TOMS, Thomas R. , CHUA-EOAN, Lew G. , BAZARJANI, Seyfollah S. , NOWAK, Matthew
IPC分类号： H01L21/02 , H01L23/522 , H01F17/00 , H01L27/06 , H01L23/48
CPC分类号： H01L28/10 , H01F17/0013 , H01F19/04 , H01F2017/002 , H01L23/481 , H01L23/5227 , H01L27/0207 , H01L2224/16145 , H01L2924/3011
摘要： A three dimensional on-chip inductor, transformer and radio frequency amplifier are disclosed. The radio frequency amplifier includes a pair of transformers and a transistor. The transformers include at least two inductively coupled inductors. The inductors include a plurality of segments (704) of a first metal layer, a plurality of segments (706) of a second metal layer, a first inductor input (708) a second inductor input (710) and a plurality of through silicon vias (702) coupling the plurality of segments of the first metal layer and the plurality of segments of the second metal layer to form a continuous, non-intersecting path between the first inductor input and the second inductor input. The inductors can have a symmetric or asymmetric geometry. The first metal layer can be a metal layer in the back-end-of-line section of the chip. The second metal layer can be located in the redistributed design layer of the chip
摘要翻译：公开了三维片上电感器，变压器和射频放大器。射频放大器包括一对变压器和晶体管。变压器包括至少两个电感耦合电感器。电感器包括第一金属层的多个段（704），第二金属层的多个段（706），第一电感器输入端（708），第二电感器输入端（710）和多个通孔硅通孔（702），耦合所述第一金属层的所述多个段和所述第二金属层的所述多个段，以在所述第一电感器输入和所述第二电感器输入之间形成连续的，不相交的路径。电感器可以具有对称或不对称的几何形状。第一金属层可以是芯片的后端部分中的金属层。第二金属层可以位于芯片的再分布设计层中

5. 发明申请

WO2010135572A3 METHOD AND APPARATUS FOR PROVIDING THROUGH SILICON VIA (TSV) REDUNDANCY 审中-公开
公开(公告)号：WO2010135572A3
公开(公告)日：2010-11-25
申请号：PCT/US2010/035646
申请日：2010-05-20
申请人： QUALCOMM INCORPORATED , KIM, Jonghae , WANG, Feng , NOWAK, Matthew
发明人： KIM, Jonghae , WANG, Feng , NOWAK, Matthew
IPC分类号： H01L21/768 , H01L21/3205
摘要： An apparatus includes a first die having a first bus, a second die having a second bus stacked on the first die, a plurality of through silicon vias connecting the first bus to the second bus, and first control logic for sending data to indentified ones of the plurality of through silicon vias. Also, optionally, second control logic for determining a first set of the plurality of through silicon vias that are nonfunctional, wherein the second control logic is configured to send information to the first control logic identifying the first set of the plurality of through silicon vias or identifying a second set of through silicon vias that are functional. Also a method of sending signals through a plurality of through silicon vias.

6. 发明申请

WO2010091096A1 TECHNIQUES FOR PLACEMENT OF ACTIVE AND PASSIVE DEVICES WITHIN A CHIP 审中-公开
标题翻译：在芯片中放置主动和被动设备的技术
公开(公告)号：WO2010091096A1
公开(公告)日：2010-08-12
申请号：PCT/US2010/023070
申请日：2010-02-03
申请人： QUALCOMM INCORPORATED , TOMS, Thomas, R. , NOWAK, Matthew , KIM, Jonghae , GU, Shiqun , HENDERSON, Brian, Matthew
发明人： TOMS, Thomas, R. , NOWAK, Matthew , KIM, Jonghae , GU, Shiqun , HENDERSON, Brian, Matthew
IPC分类号： H01L27/06 , H01L21/768 , H01L23/48 , H01L21/02 , H01L21/98 , H01L23/498
CPC分类号： H01L27/0617 , H01L23/481 , H01L23/5223 , H01L23/5227 , H01L27/0688 , H01L28/10 , H01L28/40 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor die (300) includes a semiconductive substrate layer (302) with first and second sides, a metal layer adjacent the second side of the semiconductive substrate layer, one or more active devices (305) in an active layer (306) on the first side of the semiconductive substrate layer; and a passive device (310) in the metal layer in electrical communication with the active layer. The passive device can electrically couple to the active layer with through silicon vias (TSVs). (321,322).
摘要翻译：半导体管芯（300）包括具有第一和第二侧面的半导体衬底层（302），与半导体衬底层的第二侧相邻的金属层，在有源层（306）上的一个或多个有源器件（305）半导体基片层的第一面; 以及与所述有源层电连通的所述金属层中的无源器件（310）。无源器件可以通过硅通孔（TSV）电耦合到有源层。（321,322）。

7. 发明申请

WO2010048259A1 MAGNETIC TUNNEL JUNCTION AND METHOD OF FABRICATION 审中-公开
标题翻译：磁性隧道结和制造方法
公开(公告)号：WO2010048259A1
公开(公告)日：2010-04-29
申请号：PCT/US2009/061438
申请日：2009-10-21
申请人： QUALCOMM INCORPORATED , LI, Xia , KANG, Seung H. , ZHU, Xiaochun , LEE, Kangho , NOWAK, Matthew
发明人： LI, Xia , KANG, Seung H. , ZHU, Xiaochun , LEE, Kangho , NOWAK, Matthew
IPC分类号： H01L43/08 , H01L43/12
CPC分类号： H01L43/12 , H01L43/08
摘要： In a particular embodiment, a method of forming a magnetic tunnel junction (MTJ) device (200) includes applying a dielectric layer (240) to a surface, applying a metal layer (230) to the dielectric layer, and adding a cap layer (202) on the dielectric layer. The method also includes forming a magnetic tunnel junction (MTJ) stack (206) such that an electrode (210) of the MTJ stack is disposed on the metal layer and the cap layer contacts a side portion (232) of the metal layer. An adjustable depth to via may connect a top electrode of the MTJ stack to a top metal.
摘要翻译：在特定实施例中，形成磁性隧道结（MTJ）器件（200）的方法包括将电介质层（240）施加到表面，将金属层（230）施加到电介质层上，并且添加覆盖层 202）。该方法还包括形成磁隧道结（MTJ）堆叠（206），使得MTJ堆叠的电极（210）设置在金属层上，盖层接触金属层的侧部（232）。通孔的可调节深度可将MTJ叠层的顶部电极连接到顶部金属。

8. 发明申请

WO2010021981A1 CAPACITIVE MEMS-BASED DISPLAY WITH TOUCH POSITION SENSING 审中-公开
标题翻译：具有触摸位置感测功能的基于MEMS的电容显示器
公开(公告)号：WO2010021981A1
公开(公告)日：2010-02-25
申请号：PCT/US2009/054031
申请日：2009-08-17
申请人： QUALCOMM INCORPORATED , GU, Shiqun , NOWAK, Matthew
发明人： GU, Shiqun , NOWAK, Matthew
IPC分类号： G06F3/041
CPC分类号： G06F3/0412 , G06F3/044
摘要： A micro-electro-mechanical systems (MEMS) pixel for display and touch position sensing includes a substrate and a capacitive element. The capacitive element includes one or more pixels having a first conductive platelet above the substrate, and a second conductive platelet above and spaced apart from the first conductive platelet, the two platelets forming the capacitive element. A connection to each platelet provides for applying a voltage, wherein the platelet separation changes according to the applied voltage. A transparent dielectric plate, spaced apart from and positioned opposite the substrate, covers the at least one pixel. A capacitance sensing circuit attached to the connection to each platelet of the pixel senses changes in capacitance not resulting from the applied voltage.
摘要翻译：用于显示和触摸位置感测的微电子机械系统（MEMS）像素包括基板和电容元件。电容元件包括一个或多个像素，其具有在衬底上方的第一导电片，以及在第一导电片上方并与第一导电片形成间隔开的第二导电片，所述两片片形成电容元件。与每个血小板的连接提供施加电压，其中血小板分离根据所施加的电压而改变。与衬底间隔开并与衬底相对设置的透明电介质板覆盖至少一个像素。连接到与像素的每个血小板的连接的电容感测电路感测不是由施加电压引起的电容变化。

9. 发明申请

WO2010019889A1 CORROSION CONTROL OF STACKED INTEGRATED CIRCUITS 审中-公开
标题翻译：堆叠集成电路的腐蚀控制
公开(公告)号：WO2010019889A1
公开(公告)日：2010-02-18
申请号：PCT/US2009/053895
申请日：2009-08-14
申请人： QUALCOMM INCORPORATED , GU, Shiqun , NOWAK, Matthew
发明人： GU, Shiqun , NOWAK, Matthew
IPC分类号： H01L23/10 , H01L25/065 , H01L23/20
CPC分类号： H01L25/0657 , H01L25/50 , H01L2224/0554 , H01L2224/0557 , H01L2224/05571 , H01L2224/05573 , H01L2224/056 , H01L2224/13025 , H01L2224/16 , H01L2225/06513 , H01L2225/06527 , H01L2225/06541 , H01L2924/00014 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
摘要： A system and method prevent corrosive elements (or at- least the oxidizing agent) from making contact with metal connections at the interface between two layers of a stacked IC device (10). When layers are positioned in proximity to each other, a cavity is formed at the boundary of the planar surfaces of the layers. This cavity is bounded by a peripheral seal (110/113) between the layers. In one embodiment, a vacuum is created within the cavity thereby reducing the corrosive atmosphere within the cavity. In another embodiment, the cavity is filled with an inert gas, such as argon. Once the cavity has oxidizing elements reduced, the peripheral seal (110/113) can be encapsulated to prevent seepage of contaminants into the cavity.
摘要翻译：一种系统和方法可以防止腐蚀性元素（或至少是氧化剂）在层叠的IC器件（10）的两层之间的界面处与金属连接接触。当层彼此靠近地定位时，在层的平面表面的边界处形成空腔。该空腔由层之间的周边密封（110/113）限定。在一个实施例中，在空腔内产生真空，从而减小空腔内的腐蚀性气氛。在另一个实施例中，空腔填充惰性气体，例如氩气。一旦空腔的氧化元素减少，外围密封件（110/113）就可以被包封，以防止污染物渗入空腔。

10. 发明申请

WO2010011448A2 PREDICTIVE MODELING OF INTERCONNECT MODULES FOR ADVANCED ON-CHIP INTERCONNECT TECHNOLOGY 审中-公开
标题翻译：用于高级片上互连技术的互连模块的预测建模
公开(公告)号：WO2010011448A2
公开(公告)日：2010-01-28
申请号：PCT/US2009/047668
申请日：2009-06-17
申请人： QUALCOMM INCORPORATED , LI, Xia , ZHAO, Wei , CAO, Yu , GU, Shiqun , KANG, Seung, H. , NOWAK, Matthew
发明人： LI, Xia , ZHAO, Wei , CAO, Yu , GU, Shiqun , KANG, Seung, H. , NOWAK, Matthew
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： A computer program product estimates performance of an interconnect structure of a semiconductor integrated circuit (IC). The program product includes code executing on a computer to calculate at least one electrical characteristic of the interconnect structure based on input data accounting for multiple layers of the interconnect structure. The electrical characteristics can be capacitance, resistance, and/or inductance. The capacitance may be based upon multiple components, including a fringe capacitance component, a terminal capacitance component, and a coupling capacitance component.
摘要翻译：计算机程序产品估计半导体集成电路（IC）的互连结构的性能。程序产品包括在计算机上执行的代码，用于基于考虑到互连结构的多层的输入数据来计算互连结构的至少一个电特性。电气特性可以是电容，电阻和/或电感。电容可以基于多个分量，包括边缘电容分量，端子电容分量和耦合电容分量。

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