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1. 发明申请

WO2010062618A1 ESD PROTECTION FOR FIELD EFFECT TRANSISTORS OF ANALOG INPUT CIRCUITS 审中-公开
标题翻译：模拟输入电路的场效应晶体管的ESD保护
公开(公告)号：WO2010062618A1
公开(公告)日：2010-06-03
申请号：PCT/US2009/062254
申请日：2009-10-27
申请人： QUALCOMM Incorporated , BROWN, Gary, Lee, JR. , CICALINI, Alberto
发明人： BROWN, Gary, Lee, JR. , CICALINI, Alberto
IPC分类号： H03K17/081 , H01L27/02 , H03F1/52
CPC分类号： H03K17/08104 , H01L27/0248 , H03F2200/294 , H03F2200/451
摘要： During an ESD event, an ESD current flows from a ground node of a first ESD protection circuit and out of an integrated circuit to a terminal of a package that houses the integrated circuit. To improve ESD performance, a second ESD protection circuit is provided. A diode of the second ESD protection circuit is coupled between the ground node and the body of an input transistor of a Low Noise Amplifier (LNA). If the voltage on the ground node changes quickly during an ESD event (for example, due to a current spike flowing across a wire bond), then the diode charges the body of the transistor, thereby preventing a large gate-to-body voltage from developing across transistor. In some embodiments, another ground bond pad is provided and the second ESD protection circuit includes other diodes that charge or discharge other nodes during the ESD event to prevent transistor damage
摘要翻译：在ESD事件期间，ESD电流从第一ESD保护电路的接地节点流出集成电路到容纳集成电路的封装的端子。为了提高ESD性能，提供了第二个ESD保护电路。第二ESD保护电路的二极管耦合在接地节点和低噪声放大器（LNA）的输入晶体管的主体之间。如果在ESD事件期间接地节点上的电压变化很快（例如，由于电流尖峰流过引线键合），则二极管会对晶体管的体进行充电，从而防止大的门对电压跨晶体管开发。在一些实施例中，提供了另一个接地焊盘，并且第二ESD保护电路包括在ESD事件期间对其他节点充电或放电以防止晶体管损坏的其它二极管

2. 发明申请

WO2013012755A1 DYNAMIC DIVIDE BY 2 FREQUENCY DIVIDER WITH 25% DUTY CYCLE OUTPUT WAVEFORMS 审中-公开
标题翻译：具有25％占空比输出波形的2个频率分流器动态分配
公开(公告)号：WO2013012755A1
公开(公告)日：2013-01-24
申请号：PCT/US2012/046797
申请日：2012-07-13
申请人： QUALCOMM INCORPORATED , CICALINI, Alberto
发明人： CICALINI, Alberto
IPC分类号： H03K3/356 , H03K23/44
CPC分类号： H03K23/44 , H03K3/356139
摘要： Disclosed are frequency dividers, methods, apparatus, and other implementations, including a frequency divider that includes at least one input line to deliver at least one signal with a first frequency, a divider stage comprising multiple divider active components to produce output signals each with a second frequency equal to substantially half the first frequency, and an input stage electrically coupled to the divider stage to enable operation of the divider stage, the input stage including multiple additional active components. Each of the output signals is electrically coupled to an input of a different corresponding component of the multiple additional active components to electrically actuate the respective different corresponding components such that each of the multiple additional active components is periodically in an ON state while during the same time at least another of the multiple additional active components of the input stage is in an OFF state.
摘要翻译：公开了分频器，方法，装置和其他实现方式，包括分频器，其包括至少一个输入线以递送具有第一频率的至少一个信号，分频器级包括多个除法器有源部件以产生每个具有第二频率等于第一频率的大致一半，以及电耦合到分频器级以使分路器级能够操作的输入级，输入级包括多个额外的有源分量。每个输出信号电耦合到多个附加有源分量的不同对应分量的输入，以电致动相应的不同对应分量，使得多个附加有源分量中的每一个周期性处于导通状态，同时在同一时间输入级的多个附加有源部件中的至少另一个处于OFF状态。

3. 发明申请

WO2007118171A1 BIAS GENERATOR 审中-公开
标题翻译： BIAS发电机
公开(公告)号：WO2007118171A1
公开(公告)日：2007-10-18
申请号：PCT/US2007/066102
申请日：2007-04-05
申请人： QUALCOMM Incorporated , CICALINI, Alberto
发明人： CICALINI, Alberto
IPC分类号： G05F3/00
CPC分类号： G05F3/205
摘要： A bias generator comprises a first transistor and a second transistor having a control port connected to a control port of the first transistor and to an input port of the second transistor, where a second current through the second transistor is greater than a first current through the first transistor. The current through the bias generator is minimized by providing the different currents through the transistors having a similar size.
摘要翻译：偏置发生器包括第一晶体管和第二晶体管，其具有连接到第一晶体管的控制端口和第二晶体管的输入端口的控制端口，其中通过第二晶体管的第二电流大于通过第二晶体管的第一电流第一晶体管。通过提供通过具有相似尺寸的晶体管的不同电流来最小化通过偏置发生器的电流。

4. 发明申请

WO2007118167A2 METHOD AND APPARATUS FOR TUNING RESISTORS AND CAPACITORS 审中-公开
标题翻译：用于调谐电阻和电容器的方法和装置
公开(公告)号：WO2007118167A2
公开(公告)日：2007-10-18
申请号：PCT/US2007/066097
申请日：2007-04-05
申请人： QUALCOMM INCORPORATED , CICALINI, Alberto
发明人： CICALINI, Alberto
CPC分类号： H03H1/02 , H03H2210/021 , H03H2210/043
摘要： A two-step tuning process for resistors and capacitors in an integrated circuit is described. In the first step of the tuning process, an on-chip adjustable resistor is tuned based on an external resistor to obtain a tuned resistor. The value of the tuned resistor is accurate to within a target percentage determined by the external resistor and the design of the adjustable resistor. In the second step, an adjustable capacitor is tuned based on the tuned resistor and an accurate clock to obtain a tuned capacitor having an accurate value. The adjustable capacitor may be tuned such that an RC time constant for the tuned resistor and the tune capacitor is accurate to within a target percentage determined by the accurate clock and the design of the adjustable capacitor. The resistors and capacitors of other circuits on the integrated circuit may be adjusted based on the tuned resistor and the tuned capacitor, respectively.
摘要翻译：描述了集成电路中的电阻器和电容器的两步调谐过程。在调谐过程的第一步中，基于外部电阻器调整片上可调电阻以获得调谐电阻。调谐电阻的值精确到由外部电阻确定的目标百分比和可调电阻的设计之内。在第二步中，基于调谐电阻器和精确时钟来调节可调电容器以获得具有准确值的调谐电容器。可调整的可调电容器可以使得调谐电阻器和调谐电容器的RC时间常数精确到由精确时钟和可调电容器的设计确定的目标百分比之内。可以分别基于调谐电阻器和调谐电容器来调整集成电路上的其它电路的电阻器和电容器。

5. 发明申请

WO2012003480A3 PARALLEL PATH FREQUENCY DIVIDER CIRCUIT 审中-公开
公开(公告)号：WO2012003480A3
公开(公告)日：2012-01-05
申请号：PCT/US2011/042856
申请日：2011-07-01
申请人： QUALCOMM Incorporated , BROWN, Gary L. , CICALINI, Alberto , QIAO, Dongjiang
发明人： BROWN, Gary L. , CICALINI, Alberto , QIAO, Dongjiang
IPC分类号： H03L7/00 , H03K21/40
摘要： A parallel path frequency divider (PPFD) includes a low power frequency divider and a high speed latch. A first portion of an oscillating input signal present on an input node of the PPFD is communicated to the divider and a second portion is communicated to the latch. The divider generates a frequency divided enable signal that is communicated to the latch. The latch generates a divided down output signal based on the oscillating input signal and the enable signal. The output signal is insensitive to phase noise present on the enable signal as long as the phase noise on the enable signal is less than one-half of the period of oscillation of the oscillating input signal. Because the noise generated by the low power frequency divider is not propagated to the output signal generated by the PPFD, the PPFD generates low noise, frequency divided signals with relatively low power consumption.

6. 发明申请

WO2010148407A2 POWER AND IMPEDANCE MEASUREMENT CIRCUITS FOR A WIRELESS COMMUNICATION DEVICE 审中-公开
标题翻译：无线通信设备的功率和阻抗测量电路
公开(公告)号：WO2010148407A2
公开(公告)日：2010-12-23
申请号：PCT/US2010/039376
申请日：2010-06-21
申请人： QUALCOMM INCORPORATED , SEE, Puay Hoe , BALLANTYNE, Gary John , SAHOTA, Gurkanwal Singh , HADJICHRISTOS, Aristotele , CICALINI, Alberto
发明人： SEE, Puay Hoe , BALLANTYNE, Gary John , SAHOTA, Gurkanwal Singh , HADJICHRISTOS, Aristotele , CICALINI, Alberto
IPC分类号： H04B1/04
CPC分类号： H04B1/0458 , H03H7/40
摘要： Exemplary embodiments disclosed are directed to power and impedance measurement circuits that may be used to measure power and/or impedance are described. A measurement circuit may include a sensor and a computation unit. The sensor may sense (i) a first voltage signal across a series circuit coupled to a load to obtain a first sensed signal and (ii) a second voltage signal at a designated end of the series circuit to obtain a second sensed signal. The sensor may mix (i) a first version of the first sensed signal with a first version of the second sensed signal to obtain a first sensor output and (ii) a second version of the first sensed signal with a second version of the second sensed signal to obtain a second sensor output. The computation unit may determine the impedance and/or delivered power at the designated end of the series circuit based on the sensor outputs.
摘要翻译：所公开的示例性实施例涉及可用于测量功率和/或阻抗的功率和阻抗测量电路。测量电路可以包括传感器和计算单元。传感器可以感测（i）跨耦合到负载的串联电路的第一电压信号以获得第一感测信号，以及（ii）串联电路的指定端的第二电压信号以获得第二感测信号。传感器可以将（i）第一感测信号的第一版本与第二感测信号的第一版本混合以获得第一传感器输出，以及（ii）第一感测信号的第二版本，具有第二感测的第二版本信号以获得第二传感器输出。计算单元可以基于传感器输出来确定串联电路的指定端处的阻抗和/或传递功率。

7. 发明申请

WO2009089227A3 QUADRATURE RADIO FREQUENCY MIXER WITH LOW NOISE AND LOW CONVERSION LOSS 审中-公开
公开(公告)号：WO2009089227A3
公开(公告)日：2009-07-16
申请号：PCT/US2009/030234
申请日：2009-01-06
申请人： QUALCOMM INCORPORATED , CICALINI, Alberto
发明人： CICALINI, Alberto
IPC分类号： H03D7/14
摘要： In one embodiment of the invention, a method for convolution of signals is disclosed including generating four phased half duty cycle clocks each being out of phase by a multiple of ninety degrees from the others; coupling the four phased half duty cycle clocks into a four phase half duty cycle mixer; and switching switches in the four phase half duty cycle mixer in response to the four phased half duty cycle clocks to convolve a differential input signal with the four phased half duty cycle clocks to concurrently generate a differential in-phase output signal and a differential quadrature-phase output signal on a dual differential output port.

8. 发明申请

WO2020140019A1 ANTENNA AND DEVICE CONFIGURATIONS 审中-公开
公开(公告)号：WO2020140019A1
公开(公告)日：2020-07-02
申请号：PCT/US2019/068714
申请日：2019-12-27
申请人： QUALCOMM INCORPORATED
发明人： KIM, Jeongil Jay , CICALINI, Alberto , TASSOUDJI, Mohammad Ali , FABREGA SANCHEZ, Jorge , YANG, Taesik , WANG, Kevin Hsi-Huai
IPC分类号： H04B1/40
摘要： An electronic device includes a first antenna, a second antenna, and a device cover. The first antenna may be configured to transmit or receive signals at a first frequency, and the second antenna may be configured to transmit or receive signals at a second frequency. The device cover may be configured to enclose at least a portion of the device, the and may have a first thickness in a first area and a second thickness in a second area. The first area may be substantially aligned with a boresight of the first antenna, and the second area may be substantially aligned with a boresight of the second antenna. The first thickness may be different than the second thickness.

9. 发明申请

WO2016130714A1 A FULLY I/Q BALANCED QUADRATURE RADIO FREQUENCY MIXER WITH LOW NOISE AND LOW CONVERSION LOSS 审中-公开
标题翻译：完整的I / Q平衡低频无线电混频器，具有低噪声和低转换损耗
公开(公告)号：WO2016130714A1
公开(公告)日：2016-08-18
申请号：PCT/US2016/017404
申请日：2016-02-10
申请人： QUALCOMM INCORPORATED
发明人： WANG, Cheng-Han , CICALINI, Alberto , NGUYEN, Thinh Cat , VAHID FAR, Mohammad Bagher , RICHMOND, Jesse Aaron
IPC分类号： H03D7/14 , H03D7/16
CPC分类号： H03D7/145 , H03D7/1433 , H03D7/1441 , H03D7/1458 , H03D7/1466 , H03D7/165 , H03D2200/0027
摘要： A method, an apparatus, and a system product for mixing radio frequency signals are provided. In one aspect, the apparatus is configured to perform switching of switches based on first, second, third, and fourth phased half duty clock signals. The apparatus convolves a differential input signal on a differential input port with the first, second, third, and fourth phased half duty cycle clock signals to concurrently generate a differential in-phase output signal and a differential quadrature-phase output signal on a dual differential output port. The first, second, third, and fourth phased half duty cycle clock signals are of the same frequency and out of phase by a multiple of ninety degrees with respect to each other.
摘要翻译：提供了一种用于混合射频信号的方法，装置和系统产品。一方面，该装置被配置为基于第一，第二，第三和第四相位半占空时钟信号来执行开关的切换。该装置利用第一，第二，第三和第四相位半占空比时钟信号在差分输入端口上卷积差分输入信号，以同时产生差分同相输出信号和双差分上的差分正交相输出信号输出端口第一，第二，第三和第四相位半占空比时钟信号的频率相同，相位相差90度。

10. 发明申请

WO2022225718A1 MULTI-LINE INTERFACE FOR BOARD AND SUBSTRATE 审中-公开
公开(公告)号：WO2022225718A1
公开(公告)日：2022-10-27
申请号：PCT/US2022/023852
申请日：2022-04-07
申请人： QUALCOMM INCORPORATED
发明人： PARK, Sang-June , LUNZER, Eric , LIEN, Peter , CICALINI, Alberto
IPC分类号： H01R13/6588 , H01P5/00 , H01R12/71 , H01R13/6594 , H01L23/00 , H05K9/00 , H01R24/50 , H01R12/79 , H01R12/77 , H01R103/00 , H01R31/06
摘要： A device that includes a first board, a second board, and coaxial cable coupled to the first board and the second board. The coaxial cable includes a multi-line coaxial cable configured to provide at least two electrical paths for electrical currents between the first board and the second board. A first plug is coupled to the first board. A second plug is coupled to the second board. The coaxial cable includes a first receptable and a second receptable. The first receptable is configured to couple to the first plug. The second receptable is configured to couple to the second plug. The coaxial cable is configured to provide (i) a first electrical path for a first electrical current between the first board and the second board, and (ii) a second electrical path for a second electrical current between the first board and the second board.

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