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1. 发明申请

WO2011116316A3 METHOD AND APPARATUS FOR SUPPRESSING BITLINE COUPLING THROUGH MILLER CAPACITANCE TO A SENSE AMPLIFIER INTERSTITIAL NODE 审中-公开
公开(公告)号：WO2011116316A3
公开(公告)日：2011-09-22
申请号：PCT/US2011/029046
申请日：2011-03-18
申请人： QUALCOMM INCORPORATED , PHAN, Michael ThaiThanh , CHAI, Chiaming , GARG, Manish
发明人： PHAN, Michael ThaiThanh , CHAI, Chiaming , GARG, Manish
IPC分类号： G11C7/06
摘要： A sense amplifier circuit is implemented for suppressing Miller effect capacitive coupling. The amplifier circuit comprises a differential amplifier circuit having a first input, a first output interstitial node, a second input, a second output interstitial node, a third input to enable or disable the differential amplifier, and having an equalizer circuit coupled between the first output interstitial node and the second output interstitial node. The amplifier circuit also comprises a cross coupled latch circuit having a first latch input coupled to the first output interstitial node, a second latch input coupled to the second output interstitial node, a first latch output, and a second latch output, wherein during a first time period the first latch output and the second latch output are precharged, the differential amplifier circuit is disabled, and the equalizer circuit is enabled to suppress the Miller effect capacitive coupling on the sense amplifier inputs.

2. 发明申请

WO2013040066A1 ADAPTIVE READ WORDLINE VOLTAGE BOOSTING APPARATUS AND METHOD FOR MULTI-PORT SRAM 审中-公开
标题翻译：适用于多端口SRAM的WORDLINE电压升压装置和方法
公开(公告)号：WO2013040066A1
公开(公告)日：2013-03-21
申请号：PCT/US2012/054907
申请日：2012-09-12
申请人： QUALCOMM INCORPORATED , GARG, Manish , PHAN, Michael ThaiThanh , HOFF, David Paul , NGUYEN, Quan
发明人： GARG, Manish , PHAN, Michael ThaiThanh , HOFF, David Paul , NGUYEN, Quan
IPC分类号： G11C11/419 , G11C8/08 , G11C11/418
CPC分类号： G11C11/419 , G11C8/08 , G11C11/418
摘要： Embodiments of the invention are directed to systems and methods for adaptively boosting the supply voltage to an SRAM (Static Random Access Memory) (104) in response to process-voltage-temperature variations when needed. Embodiments include a critical path (114) that simulates a typical memory cell (104) and read-out circuit (102) in the SRAM. Applying a trigger signal to a word-line input port (123) of the critical path, and comparing the output (125) of the critical path to a reference-latch signal (127), provides an indication of when to boost the supply voltage to the read-out circuits of the SRAM.
摘要翻译：本发明的实施例涉及用于在需要时响应于过程电压 - 温度变化自适应地将SRAM的电源电压升高到SRAM（静态随机存取存储器）（104）的系统和方法。实施例包括模拟SRAM中的典型存储单元（104）和读出电路（102）的关键路径（114）。将触发信号施加到关键路径的字线输入端口（123），并将关键路径的输出（125）与参考锁存信号（127）进行比较，提供何时升压电源电压的指示到SRAM的读出电路。

3. 发明申请

WO2013040065A1 IMPROVING SRAM CELL WRITABILITY 审中-公开
标题翻译：改善SRAM单元的可写性
公开(公告)号：WO2013040065A1
公开(公告)日：2013-03-21
申请号：PCT/US2012/054906
申请日：2012-09-12
申请人： QUALCOMM Incorporated , GARG, Manish , PHAN, Michael ThaiThanh
发明人： GARG, Manish , PHAN, Michael ThaiThanh
IPC分类号： G11C7/04 , G11C8/16 , G11C11/413 , G11C11/417 , G11C11/418 , G11C29/02 , G11C29/24
CPC分类号： G11C7/04 , G11C8/16 , G11C11/413 , G11C11/417 , G11C11/418 , G11C29/02 , G11C29/021 , G11C29/028 , G11C29/24
摘要： Systems and methods for detecting and improving writeability of a static random access memory (SRAM) cell. A bias voltage value (114) corresponding to an operating condition, such as, a process, a voltage, or a temperature operation condition that indicates a cell write failure condition of an external SRAM array comprising the SRAM cell is generated (110). This bias voltage value is applied to word lines of SRAM cells in a model SRAM array (130). A first delay (164) for a trigger signal (124) rippled through the model SRAM array is detected and compared to a reference delay (122). A write assist indication (162) is generated if the first delay is greater than or equal to the reference delay. Based on the write assist indication, a write assist is provided to the SRAM cell.
摘要翻译：用于检测和改善静态随机存取存储器（SRAM）单元的可写性的系统和方法。产生对应于指示包括SRAM单元的外部SRAM阵列的单元写入故障状态的处理，电压或温度操作条件的操作条件的偏置电压值（110）（110）。该偏置电压值被施加到模型SRAM阵列中的SRAM单元的字线（130）。检测波形通过模型SRAM阵列的触发信号（124）的第一延迟（164）并将其与参考延迟（122）进行比较。如果第一延迟大于或等于参考延迟，则产生写辅助指示（162）。基于写入辅助指示，向SRAM单元提供写入辅助。

4. 发明申请

WO2013049763A1 METHOD AND APPARATUS OF REDUCING LEAKAGE POWER IN MULTIPLE PORT SRAM MEMORY CELL 审中-公开
标题翻译：减少多端口SRAM存储单元泄漏功率的方法和装置
公开(公告)号：WO2013049763A1
公开(公告)日：2013-04-04
申请号：PCT/US2012/058178
申请日：2012-09-30
申请人： QUALCOMM INCORPORATED , PHAN, Michael ThaiThanh , GARG, Manish , HOFF, David Paul
发明人： PHAN, Michael ThaiThanh , GARG, Manish , HOFF, David Paul
IPC分类号： G11C11/413
CPC分类号： G11C11/413 , G11C5/148
摘要： Systems and method for reducing leakage currents and power consumption in a memory array comprising memory cells, such as 8T SRAM cells. The memory array includes logic for dynamically placing a group of memory cells in the memory array in a reduced power state during sleep mode or inactive states of the group of memory cells, such that leakage parts are effectively eliminated. The memory array further includes logic for dynamically enabling a selected group of the memory cells during read or write access operations on the selected memory cells, wherein corresponding read or write bitlines are precharged before and after the respective rear or write operations.
摘要翻译：包括诸如8T SRAM单元的存储单元的存储器阵列中的减小泄漏电流和功耗的系统和方法。存储器阵列包括用于在睡眠模式或存储器单元组的非活动状态期间以降低功率状态动态地将一组存储器单元置于存储器阵列中的逻辑，从而有效地消除泄漏部分。存储器阵列还包括用于在对所选择的存储器单元进行读取或写入访问操作期间动态地启用所选存储器单元组的逻辑，其中相应的读取或写入位线在相应的后部或写入操作之前和之后被预充电。

5. 发明申请

WO2013040061A1 APPARATUS FOR SELECTIVE WORD-LINE BOOST ON A MEMORY CELL 审中-公开
标题翻译：在存储单元上选择性的字线升压的装置
公开(公告)号：WO2013040061A1
公开(公告)日：2013-03-21
申请号：PCT/US2012/054902
申请日：2012-09-12
申请人： QUALCOMM Incorporated , GARG, Manish , PHAN, Michael ThaiThanh
发明人： GARG, Manish , PHAN, Michael ThaiThanh
IPC分类号： G11C11/412 , G11C11/418 , G11C11/419 , G11C8/16 , G11C8/08
CPC分类号： G11C8/08 , G11C5/063 , G11C7/08 , G11C8/12 , G11C8/16 , G11C11/4085 , G11C11/412 , G11C11/418 , G11C11/419
摘要： Systems and methods for selectively boosting word-line (WL) voltage in a memory cell array. The method relies several embodiments to minimize energy costs associated with WL boost scheme. One embodiment generates a transient voltage boost rather than supply a DC voltage boost. The transient boost generation may be controlled on a cycle basis and can be disabled when the array is not accessed. Another embodiment allows the system to generate the transient voltage boost locally, near a WL driver and only during the cycles when it is needed. Localized boost voltage generation reduces the load capacitance that needs to be boosted to higher voltage. Another embodiment efficiently distributes the transient boost to the WL drivers.
摘要翻译：用于选择性地提高存储单元阵列中的字线（WL）电压的系统和方法。该方法依赖于几个实施例来最小化与WL升压方案相关联的能量成本。一个实施例产生瞬态升压而不是提供直流升压。瞬态升压生成可以以循环为基础进行控制，并且可以在不访问阵列时禁用。另一个实施例允许系统在WL驱动器附近本地产生瞬态电压升高，并且仅在需要时在周期期间产生。本地化的升压电压降低了需要升压到更高电压的负载电容。另一个实施例有效地将瞬态升压分配给WL驱动器。

6. 发明申请

WO2010085560A1 LOW LEAKAGE HIGH PERFORMANCE STATIC RANDOM ACCESS MEMORY CELL USING DUAL-TECHNOLOGY TRANSISTORS 审中-公开
标题翻译：低泄漏高性能静态随机访问存储器单元使用双技术晶体管
公开(公告)号：WO2010085560A1
公开(公告)日：2010-07-29
申请号：PCT/US2010/021652
申请日：2010-01-21
申请人： QUALCOMM INCORPORATED , GARG, Manish , CHAI, Chiaming , PHAN, Michael, Thai Thanh
发明人： GARG, Manish , CHAI, Chiaming , PHAN, Michael, Thai Thanh
IPC分类号： G11C8/08 , G11C11/408 , G11C11/419
CPC分类号： G11C11/419 , G11C8/08
摘要： A memory cell includes a storage element, a write circuit coupled to the storage element and a read circuit coupled to the storage element. At least a portion of the storage element and at least a portion of the write circuit are fabricated using a thicker functional gate oxide and at least a portion of the read circuit is fabricated using a thinner functional gate oxide.
摘要翻译：存储单元包括存储元件，耦合到存储元件的写入电路和耦合到存储元件的读取电路。使用较厚的功能栅极氧化物制造存储元件的至少一部分和写入电路的至少一部分，并且使用更薄的功能栅极氧化物制造读取电路的至少一部分。

7. 发明申请

WO2011081951A1 ADAPTIVE CLOCK GENERATORS, SYSTEMS, AND METHODS 审中-公开
标题翻译：自适应时钟发生器，系统和方法
公开(公告)号：WO2011081951A1
公开(公告)日：2011-07-07
申请号：PCT/US2010/060361
申请日：2010-12-14
申请人： QUALCOMM INCORPORATED , GARG, Manish , CHAI, Chiaming , BRIDGES, Jeffrey Todd
发明人： GARG, Manish , CHAI, Chiaming , BRIDGES, Jeffrey Todd
IPC分类号： H03K3/03 , H03K5/00
CPC分类号： H03K3/0315 , H03K2005/00058 , H03K2005/00215
摘要： Adaptive clock generators, systems, and related methods than can be used to generate a clock signal for a functional circuit to avoid or reduce performance margin are disclosed. In certain embodiments, a clock generator autonomously and adaptively generates a clock signal according to a delay path(s) provided in a delay circuit(s) relating to a selected delay path(s) in the functional circuit(s). The clock generator includes a delay circuit(s) adapted to receive an input signal and delay the input signal by an amount relating to a delay path(s) of a functional circuit(s) to produce an output signal. A feedback circuit is coupled to the delay circuit(s) and responsive to the output signal, wherein the feedback circuit is adapted to generate the input signal back to the delay circuit(s) in an oscillation loop configuration. The input signal can be used to provide a clock signal to the functional circuit(s).
摘要翻译：公开了可用于生成用于功能电路的时钟信号以避免或降低性能裕度的自适应时钟发生器，系统和相关方法。在某些实施例中，时钟发生器根据在与功能电路中所选择的延迟路径相关的延迟电路中提供的延迟路径来自主地且自适应地生成时钟信号。时钟发生器包括适于接收输入信号并将输入信号延迟与功能电路的延迟路径相关的量以产生输出信号的延迟电路。反馈电路耦合到延迟电路并响应于输出信号，其中反馈电路适于在振荡环路配置中产生回到延迟电路的输入信号。输入信号可用于向功能电路提供时钟信号。

8. 发明申请

WO2010068855A2 APPARATUS AND METHODS FOR ADAPTIVE THREAD SCHEDULING ON ASYMMETRIC MULTIPROCESSOR 审中-公开
标题翻译：用于不对称多路由器的自适应线程调度的装置和方法
公开(公告)号：WO2010068855A2
公开(公告)日：2010-06-17
申请号：PCT/US2009/067654
申请日：2009-12-11
申请人： QUALCOMM Incorporated , MORROW, Michael, William , GARG, Manish
发明人： MORROW, Michael, William , GARG, Manish
IPC分类号： G06F1/32
CPC分类号： G06F9/5094 , G06F1/329 , Y02D10/22 , Y02D10/24
摘要： Techniques for adaptive thread scheduling on a plurality of cores for reducing system energy are described. In one embodiment, a thread scheduler receives leakage current information associated with the plurality of cores. The leakage current information is employed to schedule a thread on one of the plurality of cores to reduce system energy usage. On chip calibration of the sensors is also described.
摘要翻译：描述了用于减少系统能量的用于多个核上的自适应线程调度的技术。在一个实施例中，线程调度器接收与多个核相关联的漏电流信息。泄漏电流信息用于在多个核心之一上调度线程以减少系统能量消耗。还描述了传感器的片上校准。

9. 发明申请

WO2007103748A1 DUAL-PATH, MULTIMODE SEQUENTIAL STORAGE ELEMENT 审中-公开
标题翻译：双通道，多模式序列存储元件
公开(公告)号：WO2007103748A1
公开(公告)日：2007-09-13
申请号：PCT/US2007/063104
申请日：2007-03-01
申请人： QUALCOMM Incorporated , GARG, Manish , HAMDEN, Fadi
发明人： GARG, Manish , HAMDEN, Fadi
IPC分类号： G01R31/3185 , G11C29/00 , H03K3/037
CPC分类号： G01R31/318541 , G01R31/318572 , G11C29/1201 , G11C29/32
摘要： A dual-path, multimode sequential storage element (SSE) (10) is described herein. In one example, the dual-path, multimode SSE comprises first (14) and second (12) sequential storage elements, a data input, a data output, and a selector mechanism (16). The first and second sequential storage elements (14, 12) each have an input and an output. The data input is coupled to the inputs of both sequential storage elements and is configured to accept data. The data output is coupled to the outputs of both sequential storage elements and is configured to output the data. The selector mechanism (16) is configured to select one of the sequential storage elements for passing the data from the data input to the data output. In one example, the first sequential storage element comprises a pulse-triggered storage element (14) and the second sequential storage element comprises a master-slave storage element (12).
摘要翻译：本文描述了双路径多模顺序存储元件（SSE）（10）。在一个示例中，双路多模SSE包括第一（14）和第二（12）个顺序存储元件，数据输入，数据输出和选择器机构（16）。第一和第二顺序存储元件（14,12）各自具有输入和输出。数据输入耦合到两个顺序存储元件的输入，并被配置为接受数据。数据输出耦合到两个顺序存储元件的输出，并被配置为输出数据。选择器机构（16）被配置为选择一个顺序存储元件，用于将数据从数据输入传送到数据输出。在一个示例中，第一顺序存储元件包括脉冲触发存储元件（14），并且第二顺序存储元件包括主从存储元件（12）。

10. 发明申请

WO2004051449A2 REGISTER FILE GATING TO REDUCE MICROPROCESSOR POWER DISSIPATION 审中-公开
标题翻译：寄存器文件降低微处理器功耗
公开(公告)号：WO2004051449A2
公开(公告)日：2004-06-17
申请号：PCT/IB2003/005608
申请日：2003-12-03
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , U.S. PHILIPS CORPORATION , TERECHKO, Andrei , GARG, Manish
发明人： TERECHKO, Andrei , GARG, Manish
IPC分类号： G06F1/32
CPC分类号： G06F9/30141 , G06F1/3203 , G06F1/3225 , G06F1/3237 , G06F1/3275 , G06F1/3287 , G06F9/30083 , G06F9/3012 , Y02D10/128 , Y02D10/14 , Y02D10/171
摘要： A circuit arrangement and method of controlling power dissipation utilize a register file (60) with power dissipation control capabilities through a banked register design coupled with enable logic (62, 82) that is configured to selectively disable unused banks (70) of registers by selectively gating off clock (74), address (76) and data (78) inputs supplied thereto.
摘要翻译：一种控制功率消耗的电路装置和方法利用具有功率消耗控制能力的寄存器文件（60），该寄存器文件（60）具有耦合到使能逻辑（62,82）的组合寄存器设计，其被配置为通过选择性地禁用寄存器的未使用库（70）选通提供给其的输入时钟（74），地址（76）和数据（78）。

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