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1. 发明申请

WO2010068855A2 APPARATUS AND METHODS FOR ADAPTIVE THREAD SCHEDULING ON ASYMMETRIC MULTIPROCESSOR 审中-公开
标题翻译：用于不对称多路由器的自适应线程调度的装置和方法
公开(公告)号：WO2010068855A2
公开(公告)日：2010-06-17
申请号：PCT/US2009/067654
申请日：2009-12-11
申请人： QUALCOMM Incorporated , MORROW, Michael, William , GARG, Manish
发明人： MORROW, Michael, William , GARG, Manish
IPC分类号： G06F1/32
CPC分类号： G06F9/5094 , G06F1/329 , Y02D10/22 , Y02D10/24
摘要： Techniques for adaptive thread scheduling on a plurality of cores for reducing system energy are described. In one embodiment, a thread scheduler receives leakage current information associated with the plurality of cores. The leakage current information is employed to schedule a thread on one of the plurality of cores to reduce system energy usage. On chip calibration of the sensors is also described.
摘要翻译：描述了用于减少系统能量的用于多个核上的自适应线程调度的技术。在一个实施例中，线程调度器接收与多个核相关联的漏电流信息。泄漏电流信息用于在多个核心之一上调度线程以减少系统能量消耗。还描述了传感器的片上校准。

2. 发明申请

WO2012006046A1 METHODS AND APPARATUS FOR CHANGING A SEQUENTIAL FLOW OF A PROGRAM USING ADVANCE NOTICE TECHNIQUES 审中-公开
标题翻译：使用提前通知技术更改程序的顺序流的方法和装置
公开(公告)号：WO2012006046A1
公开(公告)日：2012-01-12
申请号：PCT/US2011/042087
申请日：2011-06-28
申请人： QUALCOMM Incorporated , DIEFFENDERFER, James, Norris , MORROW, Michael, William
发明人： DIEFFENDERFER, James, Norris , MORROW, Michael, William
IPC分类号： G06F9/32 , G06F9/30 , G06F9/38
CPC分类号： G06F9/30058 , G06F9/30003 , G06F9/30101 , G06F9/3804 , G06F9/3842
摘要： A processor implements an apparatus and a method for providing advance notice of an indirect branch address. A target address generated by an instruction is automatically identified. A next program address is prepared based on a most current target address before an indirect branch instruction utilizing the most current target address is speculatively executed. The apparatus suitably employs a register for holding an instruction memory address that is specified by a program as a most current indirect address of an indirect branch instruction. The apparatus also employs a next program address selector that selects the most current indirect address from the register as the next program address for use in speculatively executing the indirect branch instruction.
摘要翻译：处理器实现用于提供间接分支地址的提前通知的装置和方法。自动识别由指令生成的目标地址。在推测性地执行利用最新目标地址的间接分支指令之前，基于最新的目标地址准备下一个程序地址。该装置适当地使用寄存器来保存由程序指定的指令存储器地址作为间接分支指令的最新间接地址。该装置还采用下一个程序地址选择器，其从寄存器中选择最新的间接地址作为用于推测性地执行间接分支指令的下一个程序地址。

3. 发明申请

WO2011084542A1 APPARATUSES, SYSTEMS, AND METHODS FOR REDUCING TRANSLATION LOOKASIDE BUFFER (TLB) LOOKUPS 审中-公开
标题翻译：用于减少翻译书签缓冲区（TLB）查询的设备，系统和方法
公开(公告)号：WO2011084542A1
公开(公告)日：2011-07-14
申请号：PCT/US2010/060612
申请日：2010-12-15
申请人： QUALCOMM INCORPORATED , MORROW, Michael, William
发明人： MORROW, Michael, William
IPC分类号： G06F12/10
CPC分类号： G06F12/1027 , G06F12/1036 , G06F12/145 , G06F2212/1028 , G06F2212/655 , G06F2212/681 , Y02D10/13
摘要： Circuits and related systems and methods for providing virtual address translation are disclosed. In one embodiment, a circuit comprises a comparator configured to receive as an input a current virtual address and a current attribute associated with the current virtual address, and a prior physical address and a prior virtual address each associated with the current attribute. The comparator is further configured to cause the prior physical address to be provided as a current physical address if the current virtual address matches the prior virtual address associated with the current attribute. As an example, the circuit may be a TLB suppression circuit configured to reduce TLB lookups. Reducing TLB lookups can reduce power dissipation. In this regard, the circuit may also be further configured to suppress a TLB lookup to reduce power dissipation when the current virtual address matches the prior virtual address.
摘要翻译：公开了用于提供虚拟地址转换的电路及相关系统和方法。在一个实施例中，电路包括比较器，其被配置为接收与当前虚拟地址相关联的当前虚拟地址和当前属性作为输入，以及与当前属性相关联的先前物理地址和先前虚拟地址。如果当前虚拟地址匹配与当前属性相关联的先前虚拟地址，则比较器还被配置为使得先前的物理地址被提供为当前物理地址。作为示例，电路可以是被配置为减少TLB查找的TLB抑制电路。减少TLB查找可以减少功耗。在这方面，电路还可以被配置为当当前虚拟地址与先前的虚拟地址匹配时，抑制TLB查找以减少功耗。

4. 发明申请

WO2010096633A1 METHODS AND APARATUS FOR LOW INTRUSION SNOOP INVALIDATION 审中-公开
标题翻译：低侵入性SNOOP无效的方法和方法
公开(公告)号：WO2010096633A1
公开(公告)日：2010-08-26
申请号：PCT/US2010/024693
申请日：2010-02-19
申请人： QUALCOMM INCORPORATED , MORROW, Michael, William , DIEFFENDERFER, Jame, Norris
发明人： MORROW, Michael, William , DIEFFENDERFER, Jame, Norris
IPC分类号： G06F12/08
CPC分类号： G06F12/0831 , G06F12/0808 , Y02D10/13
摘要： Efficient techniques are described for tracking a potential invalidation of a data cache entry in a data cache for which coherency is required. Coherency information is received that indicates a potential invalidation of a data cache entry. The coherency information in association with the data cache entry is retained to track the potential invalidation to the data cache entry. The retained coherency information is kept separate from state bits that are utilized in cache access operations. An invalidate bit, associated with a data cache entry, may be utilized to represents a potential invalidation of the data cache entry. The invalidate bit is set in response to the coherency information, to track the potential invalidation of the data cache entry. A valid bit associated with the data cache entry is set in response to the active invalidate bit and a memory synchronization command. The set invalidate bit is cleared after the valid bit has been cleared.
摘要翻译：描述了用于跟踪需要一致性的数据高速缓存中的数据高速缓存条目的潜在无效的高效技术。一致性信息被接收，指示数据高速缓存条目的潜在无效。与数据高速缓存条目相关联的一致性信息被保留以跟踪对数据高速缓存条目的潜在无效。保留的一致性信息与在缓存访问操作中使用的状态位分开。与数据高速缓存条目相关联的无效位可用于表示数据高速缓存条目的潜在无效。响应于一致性信息设置无效位以跟踪数据高速缓存条目的潜在无效。响应于活动无效位和存储器同步命令来设置与数据高速缓存条目相关联的有效位。置位无效位在有效位清零后清零。

5. 发明申请

WO2016039967A1 PREDICTING LITERAL LOAD VALUES USING A LITERAL LOAD PREDICTION TABLE, AND RELATED CIRCUITS, METHODS, AND COMPUTER-READABLE MEDIA 审中-公开
标题翻译：使用文献载荷预测表和相关电路，方法和计算机可读介质预测文本负载值
公开(公告)号：WO2016039967A1
公开(公告)日：2016-03-17
申请号：PCT/US2015/046517
申请日：2015-08-24
申请人： QUALCOMM INCORPORATED
发明人： MORROW, Michael, William
IPC分类号： G06F9/38
CPC分类号： G06F9/3861 , G06F9/30043 , G06F9/30167 , G06F9/3832
摘要： Predicting literal load values using a literal load prediction table, and related circuits, methods, and computer-readable media are disclosed. In one aspect, an instruction processing circuit provides a literal load prediction table containing one or more entries, each comprising an address and a literal load value. Upon detecting a literal load instruction in an instruction stream, the instruction processing circuit determines whether the literal load prediction table contains an entry having an address of the literal load instruction. If so, the instruction processing circuit provides the predicted literal load value stored in the entry to at least one dependent instruction. The instruction processing circuit subsequently determines whether the predicted literal load value matches the actual literal load value loaded by the literal load instruction. If a mismatch exists, the instruction processing circuit initiates a misprediction recovery. The at least one dependent instruction is re-executed using the actual literal load value.
摘要翻译：公开了使用文字负载预测表以及相关电路，方法和计算机可读介质来预测文字负载值。在一个方面，指令处理电路提供包含一个或多个条目的文字负载预测表，每个条目包括地址和文字负载值。在指令流中检测到文字加载指令时，指令处理电路确定文字负载预测表是否包含具有文字加载指令的地址的条目。如果是这样，则指令处理电路将存储在条目中的预测文字负载值提供给至少一个依赖指令。指令处理电路随后确定预测的文字负载值是否与文字加载指令加载的实际文字负载值相匹配。如果存在不匹配，则指令处理电路启动错误预测恢复。使用实际文字负载值重新执行至少一个依赖指令。

6. 发明申请

WO2017030691A1 PREDICTING MEMORY INSTRUCTION PUNTS IN A COMPUTER PROCESSOR USING A PUNT AVOIDANCE TABLE (PAT) 审中-公开
标题翻译：用计算机处理器预防内存指令（PUN）
公开(公告)号：WO2017030691A1
公开(公告)日：2017-02-23
申请号：PCT/US2016/042234
申请日：2016-07-14
申请人： QUALCOMM INCORPORATED
发明人： YEN, Luke , MORROW, Michael, William , SCHOTTMILLER, Jeffery, Michael , DIEFFENDERFER, James, Norris
IPC分类号： G06F9/38
CPC分类号： G06F9/3869 , G06F9/3004 , G06F9/3834 , G06F9/3842
摘要： Predicting memory instruction punts in a computer processor using a punt avoidance table (PAT) are disclosed. In one aspect, an instruction processing circuit accesses a PAT containing entries each comprising an address of a memory instruction. Upon detecting a memory instruction in an instruction stream, the instruction processing circuit determines whether the PAT contains an entry having an address of the memory instruction. If so, the instruction processing circuit prevents the detected memory instruction from taking effect before at least one pending memory instruction older than the detected memory instruction, to preempt a memory instruction punt. In some aspects, the instruction processing circuit may determine, upon execution of a pending memory instruction, whether a hazard associated with the detected memory instruction has occurred. If so, an entry for the detected memory instruction is generated in the PAT.
摘要翻译：公开了使用平底逃避表（PAT）预测计算机处理器中的存储器指令平移。在一个方面，指令处理电路访问包含条目的PAT，每个条目包括存储器指令的地址。在检测到指令流中的存储器指令时，指令处理电路确定PAT是否包含具有存储器指令地址的条目。如果是这样，则指令处理电路防止检测到的存储器指令在比检测到的存储器指令之前的至少一个未决存储器指令之前生效，以抢占存储器指令punt。在一些方面，指令处理电路可以在执行待决存储器指令时确定是否已经发生与检测到的存储器指令相关联的危险。如果是，则在PAT中生成检测到的存储器指令的条目。

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