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1. 发明申请

WO2022177779A1 BACK END OF LINE (BEOL) PROCESS CORNER SENSING 审中-公开
公开(公告)号：WO2022177779A1
公开(公告)日：2022-08-25
申请号：PCT/US2022/015689
申请日：2022-02-08
申请人： QUALCOMM INCORPORATED
发明人： MARIMUTHU, Saravanan , LU, De , SHARMA, Baldeo Sharan , PARKAR, Peeyush Kumar , NARAYANAN, Venkat , LI, Rui , ZAYNOUN, Samy Shafik Tawfik , CHEN, Min , KIDD, David , PATIL, Amit
IPC分类号： G01R31/30 , G01R31/28
摘要： Aspects of the disclosure are directed to sensing integrated circuit (IC) Back End Of Line (BEOL) process corners. In one aspect, an apparatus for sensing IC BEOL process corners includes a ring oscillator including a plurality of ring oscillator stages configured to generate an output waveform with a frequency state; and a shield net circuit including a plurality of shield net stages corresponding to the plurality of ring oscillator stages, the shield net circuit having a toggle input. And, a method includes generating an output waveform with a frequency state using a ring oscillator that includes a plurality of ring oscillator stages; modifying a plurality of ring oscillator stage time delays through a coupling between a plurality of shield net stages and the plurality of ring oscillator stages; and selecting the frequency state using a toggle input of a shield net circuit which includes the plurality of shield net stages.

2. 发明申请

WO2019164627A1 METHOD AND APPARATUS FOR DIFFERENTIAL POWER ANALYSIS (DPA) RESILIENCE SECURITY IN CRYPTOGRAPHY PROCESSORS 审中-公开
公开(公告)号：WO2019164627A1
公开(公告)日：2019-08-29
申请号：PCT/US2019/014858
申请日：2019-01-24
申请人： QUALCOMM INCORPORATED
发明人： RAMARAJU, Ravindraraj , VATTIKONDA, Rakesh , SINHAROY, Samrat , LU, De , PANG, Bo
IPC分类号： H04L9/00
摘要： In certain aspects, a circuit includes a dynamic differential logic gate having first and second outputs, and a first static differential logic gate having first and second outputs, and first and second inputs coupled to the first and second outputs, respectively, of the dynamic differential logic gate. The dynamic differential logic gate is configured to receive a clock signal and to preset both the first and second outputs of the dynamic differential logic gate to a first preset value during a first phase of the clock signal. The first static differential logic gate is configured to preset both the first and second outputs of the first static differential logic gate to a second preset value when the first preset value is input to both the first and second inputs of the first static differential logic gate.

3. 发明申请

WO2018048606A1 APPARATUS AND METHOD FOR EMPLOYING MUTUALLY EXCLUSIVE WRITE AND READ CLOCK SIGNALS IN SCAN CAPTURE MODE FOR TESTING DIGITAL INTERFACES 审中-公开
标题翻译：用于测试数字接口的扫描捕获模式中采用数字独占写入和读取时钟信号的装置和方法
公开(公告)号：WO2018048606A1
公开(公告)日：2018-03-15
申请号：PCT/US2017/047764
申请日：2017-08-21
申请人： QUALCOMM INCORPORATED
发明人： ZAFAR, Bilal , VATTIKONDA, Rakesh , LU, De , NARAYANAN, Venkatasubramanian , ZAMANI, Masoud , FANG, Joseph
IPC分类号： G01R31/3185
CPC分类号： G01R31/31727 , G01R31/31704 , G01R31/3177 , G01R31/318552 , G11C7/22
摘要： An apparatus and method of employing mutually exclusive write and read clocks in scan capture mode for testing digital interfaces. The apparatus includes a first circuit and a first clock generator configured to generate a first clock signal for transferring a test sample from an input to an output of the first circuit in response to the first clock signal during each of a first set of scan capture cycles; a second circuit and a second clock generator configured to generate a second clock signal for transferring the test sample from an input to an output of the second circuit in response to the second clock signal during each of a second set of scan capture cycle; the first clock signal being suppressed during each scan capture cycle of the second set, and the second clock signal being suppressed during each scan capture cycle of the first set.
摘要翻译：在扫描捕获模式中采用互斥的写入和读取时钟来测试数字接口的装置和方法。该装置包括第一电路和第一时钟发生器，被配置为在第一组扫描捕获周期中的每一个扫描捕获周期期间响应于第一时钟信号而生成用于将测试样本从输入传输到第一电路的输出的第一时钟信号 ; 第二电路和第二时钟发生器，被配置为在第二组扫描捕获周期中的每一个期间响应于第二时钟信号而生成用于将测试样本从输入传送到第二电路的输出的第二时钟信号; 第一时钟信号在第二组的每个扫描捕获周期期间被抑制，并且第二时钟信号在第一组的每个扫描捕获周期期间被抑制。

4. 发明申请

WO2018005086A1 HIGH SPEED VOLTAGE LEVEL SHIFTER 审中-公开
标题翻译：高速电压电平转换器
公开(公告)号：WO2018005086A1
公开(公告)日：2018-01-04
申请号：PCT/US2017/037338
申请日：2017-06-13
申请人： QUALCOMM INCORPORATED
发明人： NARAYANAN, Venkat , VATTIKONDA, Rakesh , LU, De , VILANGUDIPITCHAI, Ramaprasath , SINHAROY, Samrat , CHEN, Rui
IPC分类号： H03K3/356 , H03K19/0185 , H03K19/096
CPC分类号： H03K19/018521 , H03K3/356121 , H03K3/356191 , H03K19/0013 , H03K19/01855 , H03K19/0963
摘要： In one embodiment, a voltage level shifter (810) includes a first p-type metal-oxide-semiconductor transistor (835) having a gate configured to receive an input signal (D) in a first power domain, and a second PMOS transistor (840), wherein the first and second PMOS transistors are coupled in series between a supply voltage (vddout) of a second power domain and a node (820). The voltage level shifter also includes an inverter (850) having an input coupled to the node and an output (Z) coupled to a gate of the second PMOS transistor, and a first n-type metal-oxide-semiconductor transistor (830) having a gate configured to receive the input signal in the first power domain, wherein the first NMOS transistor is coupled between the node and a ground.
摘要翻译：在一个实施例中，电压电平移位器（810）包括第一p型金属氧化物半导体晶体管（835），其具有被配置为接收第一功率域和第二PMOS晶体管（840），其中第一和第二PMOS晶体管串联耦合在第二电源域的电源电压（vddout）和节点（820）之间。电压电平移位器还包括反相器（850）和第一n型金属氧化物半导体晶体管（830），第一n型金属氧化物半导体晶体管（830）具有耦合到节点的输入和耦合到第二PMOS晶体管的栅极的输出（Z）栅极，被配置为在第一电源域中接收输入信号，其中第一NMOS晶体管耦合在节点和地之间。

5. 发明申请

WO2018005085A1 HIGH SPEED VOLTAGE LEVEL SHIFTER 审中-公开
标题翻译：高速电压电平转换器
公开(公告)号：WO2018005085A1
公开(公告)日：2018-01-04
申请号：PCT/US2017/037335
申请日：2017-06-13
申请人： QUALCOMM INCORPORATED
发明人： NARAYANAN, Venkat , VATTIKONDA, Rakesh , LU, De , VILANGUDIPITCHAI, Ramaprasath , SINHAROY, Samrat , CHEN, Rui
IPC分类号： H03K3/012 , H03K3/356
摘要： A voltage level shifter includes a first NOR gate (250) having a first input (252) configured to receive a first input signal (D_N) in a first power domain, a second input (255) configured to receive an enable signal (ENB) in a second power domain, a third input (257), and an output (Z). The voltage level shifter also includes a second NOR gate (220) having a first input (222) configured to receive a second input signal (D) in the first power domain, a second input (225) configured to receive the enable signal in the second power domain, a third input (227) coupled to the output of the first NOR gate, and an output (Z_N) coupled to the third input of the first NOR gate. The first and second NOR gates are powered by a supply voltage of the second power domain.
摘要翻译：电压电平移位器包括具有被配置为在第一电力域中接收第一输入信号（D_N）的第一输入端（252）的第一或非门（250），被配置为在第一输入端以在第二电力域，第三输入（257）和输出（Z）中接收使能信号（ENB）。所述电压电平移位器还包括第二NOR门（220），所述第二NOR门具有被配置为在所述第一电力域中接收第二输入信号（D）的第一输入（222），被配置为在所述第一电力域中接收所述使能信号第二电源域，耦合到第一或非门的输出的第三输入（227）以及耦合到第一或非门的第三输入的输出（Z_N）。第一和第二NOR门由第二电源域的电源供电。

6. 发明申请

WO2022164633A1 TRUE SINGLE PHASE CLOCK (TSPC) BASED LATCH ARRAY 审中-公开
公开(公告)号：WO2022164633A1
公开(公告)日：2022-08-04
申请号：PCT/US2022/012108
申请日：2022-01-12
申请人： QUALCOMM INCORPORATED
发明人： LI, Rui , LU, De , NARAYANAN, Venkat
IPC分类号： G11C19/28 , H03K3/356
摘要： A latch array including a row of master latches coupled to columns of slave latches. Each master latch includes an OR-AND-Inverter (OAI) gate cross-coupled with a NAND gate to receive and latch an input data, and each slave latch includes an AND-OR-Inverter (AOl) gate cross-coupled with a NOR gate to receive and latch the data from, the master latch, and an inverter including an input coupled to the AOT gate and an output to produce an output data based on the input data. Alternatively, each master latch includes an AND-OR-Inverter (AOI) gate cross-coupled with a NOR gate to receive and latch an input data, and each slave latch includes an OR-AND-Inverter (OAI) gate cross-coupled with a NAND gate to receive and latch the data from the master latch, and an inverter including an input coupled to the OAI gate and an output to produce an output data.

7. 发明申请

WO2018013299A1 APPARATUS FOR DESIGN FOR TESTABILITY OF MULTIPORT REGISTER ARRAYS 审中-公开
标题翻译：用于多端口寄存器阵列的测试设计的设备
公开(公告)号：WO2018013299A1
公开(公告)日：2018-01-18
申请号：PCT/US2017/038347
申请日：2017-06-20
申请人： QUALCOMM INCORPORATED
发明人： VATTIKONDA, Rakesh , SINHAROY, Samrat , LU, De
IPC分类号： G01R31/3185 , H03K3/037
CPC分类号： H03K3/0372 , G01R31/31704 , G01R31/31723 , G01R31/318541
摘要： In an aspect of the disclosure, a method and an apparatus are provided. The apparatus is a register array including first and second flip-flop latch arrays. The first flip-flop latch array includes a first set of master latches, a first set of slave latches coupled to the first set of master latches, and a first address port. The second flip-flop latch array includes a second set of master latches, a second set of slave latches coupled to the second set of master latches, and a second address port. The register array includes an address counter, coupled to the first flip-flop latch array and the second flip-flop latch array. The address counter is shared by the first flip-flop latch array and the second flip-flop latch array and configured to address, in parallel in a test mode, the first flip-flop latch array through the first address port and the second flip-flop latch array through the second address port.
摘要翻译：在本公开的一个方面中，提供了一种方法和装置。该装置是包括第一和第二触发器锁存器阵列的寄存器阵列。第一触发器锁存器阵列包括第一组主锁存器，耦合到第一组主锁存器的第一组从锁存器以及第一地址端口。第二触发器锁存器阵列包括第二组主锁存器，耦合到第二组主锁存器的第二组从锁存器以及第二地址端口。寄存器阵列包括耦合到第一触发器锁存器阵列和第二触发器锁存器阵列的地址计数器。地址计数器由第一触发器锁存器阵列和第二触发器锁存器阵列共享，并被配置为通过第一地址端口和第二触发器锁存器阵列并行地在测试模式下寻址第一触发器锁存器阵列，通过第二个地址端口触发锁存器阵列。

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