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    • 3. 发明申请
    • APPARATUS FOR DESIGN FOR TESTABILITY OF MULTIPORT REGISTER ARRAYS
    • 用于多端口寄存器阵列的测试设计的设备
    • WO2018013299A1
    • 2018-01-18
    • PCT/US2017/038347
    • 2017-06-20
    • QUALCOMM INCORPORATED
    • VATTIKONDA, RakeshSINHAROY, SamratLU, De
    • G01R31/3185H03K3/037
    • H03K3/0372G01R31/31704G01R31/31723G01R31/318541
    • In an aspect of the disclosure, a method and an apparatus are provided. The apparatus is a register array including first and second flip-flop latch arrays. The first flip-flop latch array includes a first set of master latches, a first set of slave latches coupled to the first set of master latches, and a first address port. The second flip-flop latch array includes a second set of master latches, a second set of slave latches coupled to the second set of master latches, and a second address port. The register array includes an address counter, coupled to the first flip-flop latch array and the second flip-flop latch array. The address counter is shared by the first flip-flop latch array and the second flip-flop latch array and configured to address, in parallel in a test mode, the first flip-flop latch array through the first address port and the second flip-flop latch array through the second address port.
    • 在本公开的一个方面中,提供了一种方法和装置。 该装置是包括第一和第二触发器锁存器阵列的寄存器阵列。 第一触发器锁存器阵列包括第一组主锁存器,耦合到第一组主锁存器的第一组从锁存器以及第一地址端口。 第二触发器锁存器阵列包括第二组主锁存器,耦合到第二组主锁存器的第二组从锁存器以及第二地址端口。 寄存器阵列包括耦合到第一触发器锁存器阵列和第二触发器锁存器阵列的地址计数器。 地址计数器由第一触发器锁存器阵列和第二触发器锁存器阵列共享,并被配置为通过第一地址端口和第二触发器锁存器阵列并行地在测试模式下寻址第一触发器锁存器阵列, 通过第二个地址端口触发锁存器阵列。
    • 5. 发明申请
    • HIGH SPEED VOLTAGE LEVEL SHIFTER
    • 高速电压电平转换器
    • WO2018005085A1
    • 2018-01-04
    • PCT/US2017/037335
    • 2017-06-13
    • QUALCOMM INCORPORATED
    • NARAYANAN, VenkatVATTIKONDA, RakeshLU, DeVILANGUDIPITCHAI, RamaprasathSINHAROY, SamratCHEN, Rui
    • H03K3/012H03K3/356
    • A voltage level shifter includes a first NOR gate (250) having a first input (252) configured to receive a first input signal (D_N) in a first power domain, a second input (255) configured to receive an enable signal (ENB) in a second power domain, a third input (257), and an output (Z). The voltage level shifter also includes a second NOR gate (220) having a first input (222) configured to receive a second input signal (D) in the first power domain, a second input (225) configured to receive the enable signal in the second power domain, a third input (227) coupled to the output of the first NOR gate, and an output (Z_N) coupled to the third input of the first NOR gate. The first and second NOR gates are powered by a supply voltage of the second power domain.
    • 电压电平移位器包括具有被配置为在第一电力域中接收第一输入信号(D_N)的第一输入端(252)的第一或非门(250),被配置为在第一输入端 以在第二电力域,第三输入(257)和输出(Z)中接收使能信号(ENB)。 所述电压电平移位器还包括第二NOR门(220),所述第二NOR门具有被配置为在所述第一电力域中接收第二输入信号(D)的第一输入(222),被配置为在所述第一电力域中接收所述使能信号 第二电源域,耦合到第一或非门的输出的第三输入(227)以及耦合到第一或非门的第三输入的输出(Z_N)。 第一和第二NOR门由第二电源域的电源供电。