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1. 发明申请

WO1994021038A1 VARIABLE IMPEDANCE CIRCUIT PROVIDING REDUCED DISTORTION 审中-公开
标题翻译：可变阻抗电路提供减少的失真
公开(公告)号：WO1994021038A1
公开(公告)日：1994-09-15
申请号：PCT/US1994002005
申请日：1994-02-18
申请人： MOTOROLA INC.
发明人： MOTOROLA INC. , BOCKELMAN, David, E. , STENGEL, Robert, E. , CORNETT, Kenneth, D.
IPC分类号： H03H07/00
CPC分类号： H03H7/06
摘要： An electronic circuit (300) includes first (302) and second (304) variable impedance devices coupled together. The fist (302) and second (304) variable impedance devices are designed such that each exhibits a transfer function which is substantially inverse with respect to the other about the operating point of the electronic circuit. This provides for an electronic circuit which exhibits verly low distortion characteristics. Circuits such as tunable filters, voltage-controlled oscillators (VCOs), receivers, etc. will benefit from using an electronic circuit (300) which exhibits such low distortion characteristics.
摘要翻译：电子电路（300）包括耦合在一起的第一（302）和第二（304）可变阻抗器件。第一（302）和第二（304）可变阻抗装置被设计成使得每个展现出相对于另一个关于电子电路的工作点基本上相反的传递函数。这提供了显示出非常低的失真特性的电子电路。诸如可调谐滤波器，压控振荡器（VCO），接收器等的电路将受益于使用具有这种低失真特性的电子电路（300）。

2. 发明申请

WO2003041276A2 CASCADED DELAY LOCKED LOOP CIRCUIT 审中-公开
标题翻译： CASCADED延迟锁定环路
公开(公告)号：WO2003041276A2
公开(公告)日：2003-05-15
申请号：PCT/US2002/033935
申请日：2002-10-23
申请人： MOTOROLA, INC.
发明人： JUAN, Jui-Kuo , STENGEL, Robert, E. , MARTIN, Frederick, L. , BOCKELMAN, David, E.
IPC分类号： H03L
CPC分类号： H03L7/16 , H03L7/07 , H03L7/0812 , H03L7/14 , H03L2207/08
摘要： A delay locked loop frequency synthesizer in several embodiments uses a primary delay line element (24) and one or more secondary delay elements (162 164, 270, 310). In one embodiment, a main delay line (24) is used to coarsely select a frequency output while a secondary delay element (162 164, 270, 310), either passive or active, is used to increase the resolution of the primary delay line (24). In the passive embodiment, a coarse and fine frequency selection is possible by selecting components from the output taps of the main delay line (24) as a driving signal for the passive secondary delay element (310) to provide the coarse adjustment and selecting an output from the secondary delay element (310) to provide the fine selection.
摘要翻译：在几个实施例中，延迟锁定环频率合成器使用主延迟线元件（24）和一个或多个辅助延迟元件（162 164,270,310）。在一个实施例中，主延迟线（24）用于粗略地选择频率输出，而使用无源或有源的辅助延迟元件（162 164,270,310）来增加主延迟线的分辨率 24）。在被动实施例中，通过从主延迟线（24）的输出抽头中选择分量作为被动次级延迟元件（310）的驱动信号来提供粗调和选择输出，可以进行粗略和精细的频率选择从第二延迟元件（310）提供精细选择。

3. 发明申请

WO2003012871A1 COMPOUND SEMICONDUCTOR DEVICES AND SILICON DEVICES 审中-公开
标题翻译：化合物半导体器件和硅器件
公开(公告)号：WO2003012871A1
公开(公告)日：2003-02-13
申请号：PCT/US2002/015107
申请日：2002-05-14
申请人： MOTOROLA, INC.
发明人： HECK, Joseph, P. , BOCKELMAN, David, E. , STENGEL, Robert, E.
IPC分类号： H01L27/06
CPC分类号： H01L21/8221 , H01L21/02381 , H01L21/02488 , H01L21/02505 , H01L21/02513 , H01L21/02521 , H01L21/8258 , H01L27/0605 , H01L27/0688 , H01L27/15 , H01L2924/00011 , H01S5/021 , H01S5/0261 , H01S2301/173 , H03F1/18 , H01L2224/80001
摘要： High quality epitaxial layers of monocrystalline materials (66) can be grown overlying monocrystalline substrates (52) such as large silicon wafers by forming a compliant substrate for growing the monocrystalline layers. Devices(56) may be formed in the silicon wafer prior to growing the high quality epitaxial layers. Then, to achieve the formation of a compliant substrate, an accommodating buffer layer (65) is grown on silicon wafer. The accommodating buffer layer is a layer of monocrystalline oxide spaced apart from the silicon wafer by an amorphous interface layer (62) of silicon oxide. The amorphous interface layer dissipates strain and permits the growth of a high quality monocrystalline oxide accommodating buffer layer. The accommodating buffer layer is lattice matched to both the underlying silicon wafer and the overlying monocrystalline material layer. Compound devices (68) are then formed on the overlying monocrystalline layer. Any lattice mismatch between the accommodating buffer layer and the underlying silicon substrate is taken care of by the amorphous interface layer. In addition, formation of a compliant substrate may include utilizing surfactant enhanced epitaxy, epitaxial growth of single crystal silicon onto single crystal oxide, and epitaxial growth of Zintl phase materials. Silicon devices and circuits (e.g., CMOS circuits) in the silicon wafer are wired (70) to the compound devices (e.g., MESFETs, HBTs, HEMTs, PHEMTs, etc.), forming an electrical connection therebetween.
摘要翻译：通过形成用于生长单晶层的顺应性衬底，可以将单晶材料（66）的高质量外延层生长在覆盖单晶衬底（52），例如大硅晶片上。在生长高质量外延层之前，可以在硅晶片中形成器件（56）。然后，为了形成顺应性衬底，在硅晶片上生长容纳缓冲层（65）。容纳缓冲层是通过氧化硅的非晶界面层（62）与硅晶片间隔开的单晶氧化物层。非晶界面层消耗应变并允许高质量单晶氧化物容纳缓冲层的生长。容纳缓冲层与下面的硅晶片和上覆的单晶材料层晶格匹配。然后在覆盖的单晶层上形成复合器件（68）。通过非晶界面层处理容纳缓冲层和底层硅衬底之间的任何晶格失配。此外，顺应性衬底的形成可以包括利用表面活性剂增强的外延，将单晶硅外延生长到单晶氧化物上，以及Zintl相材料的外延生长。硅晶片中的硅器件和电路（例如，CMOS电路）被连线（70）到复合器件（例如，MESFET，HBT，HEMT，PHEMT等），在它们之间形成电连接。

4. 发明申请

WO1995006955A1 A TWISTED-PAIR PLANAR CONDUCTOR LINE OFF-SET STRUCTURE 审中-公开
标题翻译：一个双绞线平面导体线偏移结构
公开(公告)号：WO1995006955A1
公开(公告)日：1995-03-09
申请号：PCT/US1994009426
申请日：1994-08-18
申请人： MOTOROLA, INC.
发明人： MOTOROLA, INC. , BOCKELMAN, David, E.
IPC分类号： H01K01/02
CPC分类号： H01P3/081 , H01L23/528 , H01L23/66 , H01L2223/6627 , H01L2924/0002 , H01L2924/1903 , H01L2924/3011 , H05K1/0228 , H05K1/0245 , H05K9/0039 , H05K2201/097 , H05K2201/10689 , H01L2924/00
摘要： A twisted-pair conductor line structure is formed on a substrate (22) having insulated conductive layers (10, 11). The conductive layers are used to form first, second, third, and fourth conductive planar segments (16). A first conductive link (44) joins the first and second planar conductive segments to provide a first signal path. Similarly, a second conductive link (46) joins the third and fourth planar conductive segments to provide a second signal path. The first and second conductive links are operatively arranged to form a twist (17) in the first and second signal paths, such that the resulting magnetic fields (57, 59) around the twisted conductive segments will be opposite to each other for cancelling each other out, in order to reduce the magnetic field radiation to the surrounding environment. Two such twisted-pair conductor lines are placed such that their twisted portions are off-set from each other.
摘要翻译：在具有绝缘导电层（10,11）的基板（22）上形成双绞导体线结构。导电层用于形成第一，第二，第三和第四导电平面段（16）。第一导电连接（44）连接第一和第二平面导电段以提供第一信号路径。类似地，第二导电连接（46）连接第三和第四平面导电段以提供第二信号路径。第一和第二导电连接件被可操作地布置成在第一和第二信号路径中形成扭转（17），使得围绕扭转的导电段的所得到的磁场（57,59）将彼此相对以抵消彼此出来，以减少对周围环境的磁场辐射。两根这样的双绞线导体线被放置成使得它们的扭曲部彼此偏离。

5. 发明申请

WO2003063435A1 DELAY LOCKED LOOP SYNTHESIZER WITH MULTIPLE OUTPUTS AND DIGITAL MODULATION 审中-公开
标题翻译：具有多个输出和数字调制的延迟锁定合成器
公开(公告)号：WO2003063435A1
公开(公告)日：2003-07-31
申请号：PCT/US2003/001304
申请日：2003-01-15
申请人： MOTOROLA, INC.
发明人： STENGEL, Robert, E. , HECK, Joseph, P. , BOCKELMAN, David, E.
IPC分类号： H04L25/00
CPC分类号： H03L7/0812 , H03K7/04 , H03K2005/00019 , H03L7/16 , H04L27/0008
摘要： A delay locked loop circuit (200) in which multiple outputs are produced. A single delay line (24) is shared among multiple tap selection circuits (256A, 265B, 265C). Fixed phase shifts (412) can be introduced between multiple outputs. A modulating signal can be used in the tap selection processing to produce digital amplitude, frequency and/or phase modulation.
摘要翻译：一种产生多个输出的延迟锁定环路（200）。单个延迟线（24）在多个抽头选择电路（256A，265B，265C）之间共享。可以在多个输出之间引入固定相移（412）。调制信号可用于抽头选择处理以产生数字幅度，频率和/或相位调制。

6. 发明申请

WO2002065668A1 INTELLIGENT REPEATER AND METHOD TO PROVIDE INCREASED SIGNALING 审中-公开
标题翻译：智能重发器和提供增加信号的方法
公开(公告)号：WO2002065668A1
公开(公告)日：2002-08-22
申请号：PCT/US2002/003270
申请日：2002-02-04
申请人： MOTOROLA, INC., A CORPORATION OF THE STATE OF DELAWARE
发明人： BOCKELMAN, David, E.
IPC分类号： H04B7/15
CPC分类号： H04B7/155
摘要： A system and method are disclosed to provide increased signaling in a communications system. A repeater system (10) is operable to receive and store operating characteristic data from a communications unit (14, 16, 18), the repeater (12) transmitting at least some of the stored operating characteristic data during a detected break in transmission.
摘要翻译：公开了一种在通信系统中提供增加的信令的系统和方法。中继器系统（10）可操作以从通信单元（14,16,18）接收和存储操作特性数据，所述中继器（12）在检测到的传输中断期间传送所存储的操作特性数据中的至少一些。

7. 发明申请

WO1995006945A1 A VERTICALLY TWISTED-PAIR PLANAR CONDUCTOR LINE STRUCTURE 审中-公开
标题翻译：一种垂直对绞平面导体线结构
公开(公告)号：WO1995006945A1
公开(公告)日：1995-03-09
申请号：PCT/US1994009373
申请日：1994-08-18
申请人： MOTOROLA, INC.
发明人： MOTOROLA, INC. , BOCKELMAN, David, E.
IPC分类号： H01B11/02
CPC分类号： H01P3/081 , H01L2223/6627 , H01L2924/1903 , H05K1/0216
摘要： A twisted-pair conductor line structure is formed on a substrate (22) having insulated conductive layers (31, 32). The conductive layers are used to form first, second, third, and fourth conductive planar segments (40, 41, 42, 43). A first conductive link (44) joins the first and second planar conductive segments to provide a first signal path. Similarly, a second conductive link (46) joins the third and fourth planar conductive segments to provide a second signal path. The first and second conductive links are operatively arranged to form a twist (17) in the first and second signal paths, such that the resulting magnetic fields (57, 59) around the twisted conductive segments will be opposite to each other for cancelling each other out, in order to reduce the magnetic field radiation to the surrounding environment.
摘要翻译：在具有绝缘导电层（31,32）的基板（22）上形成双绞导体线结构。导电层用于形成第一，第二，第三和第四导电平面段（40,41,42,43）。第一导电连接（44）连接第一和第二平面导电段以提供第一信号路径。类似地，第二导电连接（46）连接第三和第四平面导电段以提供第二信号路径。第一和第二导电连接件被可操作地布置成在第一和第二信号路径中形成扭转（17），使得围绕扭转的导电段的所得到的磁场（57,59）将彼此相对以抵消彼此出来，以减少对周围环境的磁场辐射。

8. 发明申请

WO2002065687A1 DIRECT DIGITAL SYNTHESIZER BASED ON DELAY LINE WITH SORTED TAPS 审中-公开
标题翻译：基于延迟线的直接数字合成器
公开(公告)号：WO2002065687A1
公开(公告)日：2002-08-22
申请号：PCT/US2002/003804
申请日：2002-02-05
申请人： MOTOROLA, INC.
发明人： BOCKELMAN, David, E.
IPC分类号： H04L7/00
CPC分类号： G06F1/022 , G06F1/10 , H03K5/133 , H03L7/0812 , H03L7/16
摘要： A digital frequency synthesizer includes a clock which produces a clock signal oscillating at a fixed frequency and a delay line which receives the clock signal and which produces therefrom a plurality of phase shifted clock signals oscillating at the fixed frequency. Each phase shifted clock signal is shifted in phase with respect to the clock signal and with respect to the other phase shifted clock signals. A look-up table receives an address value related to an ideal phase shifted clock signal oscillating at the fixed frequency and outputs a tap address related to the address value. A selection circuit receives the plurality of phase shifted clock signals and the tap address and outputs one of the phase shifted clock signals in response thereto. A sampling circuit samples at least a portion of the one phase shifted clock signal output by the selection circuit and outputs the sampled portion to form at least a part of an oscillator signal having a desired frequency.
摘要翻译：数字频率合成器包括产生以固定频率振荡的时钟信号的时钟和接收时钟信号的延迟线，并且由此产生以固定频率振荡的多个相移时钟信号。每个相移的时钟信号相对于时钟信号和相对于另一个相移时钟信号同相移位。查找表接收与以固定频率振荡的理想相移时钟信号相关的地址值，并输出与地址值相关的抽头地址。选择电路接收多个相移时钟信号和抽头地址，并响应于此输出一个相移时钟信号。采样电路对由选择电路输出的一个相移时钟信号的至少一部分进行采样，并输出采样部分以形成具有期望频率的振荡器信号的至少一部分。

9. 发明申请

WO1996001433A1 CHARACTERIZING A DIFFERENTIAL CIRCUIT 审中-公开
标题翻译：表征差分电路
公开(公告)号：WO1996001433A1
公开(公告)日：1996-01-18
申请号：PCT/US1995007561
申请日：1995-06-13
申请人： MOTOROLA INC.
发明人： MOTOROLA INC. , BOCKELMAN, David, E. , EISENSTADT, William, R.
IPC分类号： G01R23/20
CPC分类号： G01R31/3167 , G01R1/06772 , G01R27/28
摘要： A method and apparatus is provided for characterizing a differential circuit. A measurement system (200) is used to introduce input signals to the differential circuit and to measure corresponding output signals. Particularly, an input differential wave is introduced into the differential circuit (1010) while correspondingly measuring a differential output wave (1020) and a first common mode output wave (1030). Similarly, an input common mode wave is introduced (1040) while measuring a second differential output wave (1050) and a second common mode output wave (1060).
摘要翻译：提供了用于表征差分电路的方法和装置。测量系统（200）用于将输入信号引入差分电路并测量相应的输出信号。特别地，输入差分波被引入差分电路（1010），同时相应地测量差分输出波（1020）和第一共模输出波（1030）。类似地，在测量第二差分输出波（1050）和第二共模输出波（1060）的同时引入输入共模波（1040）。

10. 发明申请

WO1995006946A1 A HORIZONTALLY TWISTED-PAIR PLANAR CONDUCTOR LINE STRUCTURE 审中-公开
标题翻译：一种水平对绞平面导线结构
公开(公告)号：WO1995006946A1
公开(公告)日：1995-03-09
申请号：PCT/US1994010004
申请日：1994-08-31
申请人： MOTOROLA INC.
发明人： MOTOROLA INC. , BOCKELMAN, David, E. , WEISMAN, Douglas, H.
IPC分类号： H01B11/02
CPC分类号： H05K9/0039 , H01L23/49838 , H01L23/5386 , H01L2223/6638 , H01L2924/0002 , H01L2924/3011 , H04B3/32 , H05K1/0228 , H05K1/0245 , H05K2201/097 , H05K2201/10689 , H01L2924/00
摘要： A twisted-pair conductor line structure is formed on a substrate (22) having insulated conductive layers (10, 11). The conductive layers are used to form first, second, third, and fourth conductive planar segments (16). A first conductive link (17) joins the first and second planar conductive segments to provide a first signal path. Similarly, a second conductive link (17) joins the third and fourth planar conductive segments to provide a second signal path. The first and second conductive links are operatively arranged to form a twist (17) in the first and second signal paths, such that the resulting magnetic fields (57, 59) around the twisted conductive segments will be opposite to each other for cancelling each other out, in order to reduce the magnetic field radiation to the surrounding environment.
摘要翻译：在具有绝缘导电层（10,11）的基板（22）上形成双绞导体线结构。导电层用于形成第一，第二，第三和第四导电平面段（16）。第一导电连接（17）连接第一和第二平面导电段以提供第一信号路径。类似地，第二导电连接（17）连接第三和第四平面导电段以提供第二信号路径。第一和第二导电连接件被可操作地布置成在第一和第二信号路径中形成扭转（17），使得围绕扭转的导电段的所得到的磁场（57,59）将彼此相对以抵消彼此出来，以减少对周围环境的磁场辐射。

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