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1. 发明申请

WO2015156905A1 SOFT POST PACKAGE REPAIR OF MEMORY DEVICES 审中-公开
标题翻译：软件包修复内存设备
公开(公告)号：WO2015156905A1
公开(公告)日：2015-10-15
申请号：PCT/US2015/015481
申请日：2015-02-11
申请人： MICRON TECHNOLOGY, INC.
发明人： WILSON, Alan, J. , WRIGHT, Jeffrey
IPC分类号： G11C29/04 , G11C8/08
CPC分类号： G11C29/76 , G11C7/24 , G11C11/408 , G11C11/4087 , G11C11/418 , G11C17/16 , G11C17/18 , G11C29/04 , G11C29/70 , G11C29/789 , G11C29/806 , G11C29/838 , G11C2029/4402
摘要： Apparatus and methods for soft post package repair are disclosed. One such apparatus can include memory cells in a package, volatile memory configured to store defective address data responsive to entering a soft post-package repair mode, a match logic circuit and a decoder. The match logic circuit can generate a match signal indicating whether address data corresponding to an address to be accessed matches the defective address data stored in the volatile memory. The decoder can select a first group of the memory cells to be accessed instead of a second group of the memory cells responsive to the match signal indicating that the address data corresponding to the address to be accessed matches the defective address data stored in the volatile memory. The second group of the memory cells can correspond to a replacement address associated with other defective address data stored in non-volatile memory of the apparatus.
摘要翻译：公开了软包装修复的装置和方法。一种这样的设备可以包括封装中的存储器单元，易失性存储器被配置为响应于进入软件后封装修复模式，匹配逻辑电路和解码器而存储有缺陷的地址数据。匹配逻辑电路可以产生指示与要访问的地址相对应的地址数据是否与存储在易失性存储器中的缺陷地址数据相匹配的匹配信号。解码器可以响应于匹配信号来选择要访问的存储器单元的第一组而不是第二组，所述匹配信号指示对应于要访问的地址的地址数据与存储在易失性存储器中的缺陷地址数据相匹配。存储器单元的第二组可对应于与存储在该装置的非易失性存储器中的其他缺陷地址数据相关联的替换地址。

2. 发明申请

WO2007015773A2 MEMORY DEVICE AND METHOD HAVING MULTIPLE ADDRESS, DATA AND COMMAND BUSES 审中-公开
标题翻译：具有多个地址，数据和命令总线的存储器件和方法
公开(公告)号：WO2007015773A2
公开(公告)日：2007-02-08
申请号：PCT/US2006/027494
申请日：2006-07-13
申请人： MICRON TECHNOLOGY, INC. , CULLUM, James , WRIGHT, Jeffrey
发明人： CULLUM, James , WRIGHT, Jeffrey
IPC分类号： G11C8/00
CPC分类号： G11C8/12 , G11C7/1012 , G11C11/408 , G11C11/4096 , G11C2207/107
摘要： A dynamic random access memory ("DRAM") device includes a pair of internal address buses that are selectively coupled to an external address bus by an address multiplexer, and a pair of internal data buses that are selectively coupled to an external data bus by a data multiplexer. The DRAM device also includes a bank multiplexer for each bank of memory cells that selectively couples one of the internal address buses and one of the internal data buses to the respective bank of memory cells. Select signals generated by a command decoder cause the multiplexers to select alternate internal address and data buses responsive to each memory command received by the command decoder.
摘要翻译：动态随机存取存储器（“DRAM”）器件包括一对内部地址总线，其通过地址多路复用器选择性地耦合到外部地址总线，以及一对内部数据总线，其通过以下方式选择性地耦合到外部数据总线数据多路复用器。 DRAM设备还包括用于每一组存储器单元的存储体多路复用器，其将内部地址总线和内部数据总线中的一个选择性地耦合到相应存储单元组。选择由命令解码器产生的信号使得多路复用器响应于命令解码器接收的每个存储器命令来选择备用的内部地址和数据总线。

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