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1. 发明申请

WO2006039684A1 STRAINED GETTERING LAYERS FOR SEMICONDUCTOR PROCESSES 审中-公开
标题翻译：用于半导体工艺的应变取向层
公开(公告)号：WO2006039684A1
公开(公告)日：2006-04-13
申请号：PCT/US2005/035595
申请日：2005-10-03
申请人： MASSACHUSETTS INSTITUTE OF TECHNOLOGY , PITERA, Arthur, J. , FITZGERALD, Eugene, A.
发明人： PITERA, Arthur, J. , FITZGERALD, Eugene, A.
IPC分类号： H01L21/762
CPC分类号： H01L21/26506 , C30B25/20 , C30B33/00 , H01L21/3221 , H01L21/3226 , H01L21/76254
摘要： A method and structure for forming semiconductor structures using tensilely strained gettering layers. The method includes forming a donor wafer comprising a tensilely strained gettering layer disposed over a substrate, and at least one material layer disposed over the tensilely strained gettering layer. Additionally, the donor wafer may possess a particle-confining region proximate the tensilely strained layer. The method can also include introducing particles into the donor wafer to a depth below the surface, and accumulating at least some particles within the tensilely strained gettering layer. Next, the method can include initiating a cleaving action so as to separate at least one of the material layers form the substrate. The tensilely strained gettering layer may accumulate particles and/or point defects and reduce the implantation dose and thermal budget required for cleaving.
摘要翻译：使用拉伸应变吸气层形成半导体结构的方法和结构。该方法包括形成供体晶片，其包括设置在基板上的拉伸变应性吸收层，以及设置在拉伸应变吸气层上的至少一个材料层。另外，施主晶片可以具有靠近拉伸应变层的颗粒约束区域。该方法还可以包括将颗粒引入供体晶片中至表面下方的深度，并且在拉伸变应的吸气层内积聚至少一些颗粒。接下来，该方法可以包括引发切割作用，以分离至少一个材料层形成基底。拉伸应变的吸气层可能积聚颗粒和/或点缺陷，并减少切割所需的注射剂量和热预算。

2. 发明申请

WO2009151979A2 HIGH-EFFICIENCY SOLAR CELL STRUCTURES AND METHODS 审中-公开
标题翻译：高效太阳能电池结构与方法
公开(公告)号：WO2009151979A2
公开(公告)日：2009-12-17
申请号：PCT/US2009/045596
申请日：2009-05-29
申请人： 4POWER, LLC , FITZGERALD, Eugene, A. , PITERA, Arthur, J. , RINGEL, Steven, A.
发明人： FITZGERALD, Eugene, A. , PITERA, Arthur, J. , RINGEL, Steven, A.
IPC分类号： H01L31/0392
CPC分类号： H01L31/184 , H01L31/02008 , H01L31/02167 , H01L31/0304 , H01L31/0336 , H01L31/0735 , H01L31/075 , H01L31/076 , Y02E10/544 , Y02E10/548
摘要： Solar cells include a substrate consisting essentially of silicon, a first junction disposed over the substrate, the first junction comprising at least one III- V material and having a threading dislocation density of less than approximately 10 7 cm -2 , and a cap layer disposed over the first junction, the cap layer comprising silicon. Methods for forming solar cells include forming, over a substrate, a first junction comprising at least one III- V material and having a threading dislocation density of less than approximately 10 7 cm -2 , and forming, over the first junction, a cap layer comprising silicon, wherein the substrate consists essentially of silicon.
摘要翻译：太阳能电池包括基本上由硅组成的衬底，设置在衬底上的第一结，第一结包括至少一个III-V材料并且具有小于约107cm -2的穿透位错密度，以及覆盖层第一结，盖层包括硅。用于形成太阳能电池的方法包括在衬底上形成包含至少一种III-V材料并且具有小于约107cm -2的穿透位错密度的第一结，并且在第一接合部上形成包括硅，其中所述衬底基本上由硅组成。

3. 发明申请

WO2006007394A2 STRAINED TRI-CHANNEL LAYER FOR SEMICONDUCTOR-BASED ELECTRONIC DEVICES 审中-公开
标题翻译：用于基于半导体的电子器件的应变三通道层
公开(公告)号：WO2006007394A2
公开(公告)日：2006-01-19
申请号：PCT/US2005/021281
申请日：2005-06-16
申请人： MASSACHUSETTS INSTITUTE OF TECHNOLOGY , GUPTA, Saurabh , LEE, Minjoo, Larry , FITZGERALD, Eugene, A.
发明人： GUPTA, Saurabh , LEE, Minjoo, Larry , FITZGERALD, Eugene, A.
IPC分类号： H01L29/78 , H01L29/10 , H01L27/092
CPC分类号： H01L21/823807 , H01L29/1054 , H01L29/4916 , H01L29/4925 , H01L29/495 , H01L29/4966
摘要： A semiconductor-based structure includes a substrate layer, a compressively strained semiconductor layer adjacent to the substrate layer to provide a channel for a component, and a tensilely strained semiconductor layer disposed between the substrate layer and the compressively strained semiconductor layer. A method for making an electronic device includes providing, on a straininducing substrate, a first tensilely strained layer, forming a compressively strained layer on the first tensilely strained layer, and forming a second tensilely strained layer on the compressively strained layer. The first and second tensilely strained layers can be formed of silicon, and the compressively strained layer can be formed of silicon and germanium.
摘要翻译：基于半导体的结构包括衬底层，与衬底层相邻的压缩应变半导体层以提供用于部件的沟道，以及布置在衬底层和压缩应变半导体层之间的拉伸应变半导体层。一种制造电子器件的方法包括在应变消除衬底上提供第一拉伸应变层，在第一拉伸应变层上形成压缩应变层，以及在压缩应变层上形成第二拉伸应变层。第一和第二拉伸应变层可以由硅形成，并且压缩应变层可以由硅和锗形成。

4. 发明申请

WO2004073044A2 INTEGRATED SEMICONDUCTOR DEVICE AND METHOD TO MAKE SAME 审中-公开
标题翻译：集成半导体器件及其制造方法
公开(公告)号：WO2004073044A2
公开(公告)日：2004-08-26
申请号：PCT/US2004/004254
申请日：2004-02-13
申请人： MASSACHUSETTS INSTITUTE OF TECHNOLOGY , CHENG, Zhiyuan , FITZGERALD, Eugene, A. , ANTONIADIS, Dimitri, A.
发明人： CHENG, Zhiyuan , FITZGERALD, Eugene, A. , ANTONIADIS, Dimitri, A.
IPC分类号： H01L
CPC分类号： H01L29/785 , H01L29/66628 , H01L29/66795 , H01L29/7842 , H01L29/78687
摘要： A multiple-gate FET structure includes a semiconductor substrate. A gate region is formed on the semiconductor substrate. The gate region comprises a gate portion and a channel portion. The gate portion has at least two opposite vertical surfaces adjacent to the channel portion. A source region abuts the gate region at one end, and a drain diffusion region abuts the gate region at the other end.
摘要翻译：多栅极FET结构包括半导体衬底。在半导体衬底上形成栅区。栅极区域包括栅极部分和沟道部分。栅极部分具有与通道部分相邻的至少两个相对的垂直表面。源极区域在一端邻接栅极区域，漏极扩散区域在另一端邻接栅极区域。

5. 发明申请

WO2007067589A2 INSULATED GATE DEVICES AND METHOD OF MAKING SAME 审中-公开
标题翻译：绝缘闸门装置及其制造方法
公开(公告)号：WO2007067589A2
公开(公告)日：2007-06-14
申请号：PCT/US2006/046493
申请日：2006-12-05
申请人： MASSACHUSETTS INSTITUTE OF TECHNOLOGY , LEE, Minjoo, Larry , FITZGERALD, Eugene, A.
发明人： LEE, Minjoo, Larry , FITZGERALD, Eugene, A.
IPC分类号： H01L23/28
CPC分类号： H01L27/0605 , H01L21/8252 , H01L29/2003 , H01L29/432 , H01L29/513 , H01L29/517 , H01L29/66522 , H01L29/802 , H01L2924/0002 , H01L2924/00
摘要： Structures and devices, and methods of making such structures and devices, including a gate dielectric layer are provided. A semiconductor structure can include a semiconductor channel layer including a nitride-free semiconductor layer and a gate dielectric layer including a group Ill-nitride layer, wherein the gate dielectric layer is disposed over the semiconductor channel layer. A method of making a semiconductor device structure is also provided. The method includes providing a semiconductor channel layer including a nitride-free semiconductor layer and providing a gate dielectric layer including a group Ill-nitride layer, wherein the gate dielectric layer is disposed over the semiconductor channel layer. A metal-insulator-semiconductor field effect transistor (MISFIT) device structure can include a semiconductor channel layer including a nitride- free semiconductor layer and a gate dielectric layer comprising a group Ill-nitride layer, wherein the gate dielectric layer is disposed over the semiconductor channel layer. The MISFIT may include a gate electrode disposed over the gate dielectric. The MISFIT may include a source and drain region separated by the semiconductor channel layer.
摘要翻译：提供了包括栅介质层的结构和器件以及制造这种结构和器件的方法。半导体结构可以包括包括无氮化物半导体层的半导体沟道层和包括III族氮化物层的栅极电介质层，其中栅极电介质层设置在半导体沟道层上。还提供了制造半导体器件结构的方法。该方法包括提供包括无氮化物的半导体层的半导体沟道层，并提供包括III族氮化物层的栅介质层，其中栅极电介质层设置在半导体沟道层上。金属 - 绝缘体 - 半导体场效应晶体管（MISFIT）器件结构可以包括包括无氮化物半导体层的半导体沟道层和包括III族氮化物层的栅极电介质层，其中栅极电介质层设置在半导体通道层。 MISFIT可以包括设置在栅极电介质上的栅电极。 MISFIT可以包括由半导体沟道层分离的源极和漏极区域。

6. 发明申请

WO2004073043A2 SEMICONDUCTOR-ON-INSULATOR ARTICLE AND METHOD OF MAKING SAME 审中-公开
标题翻译：半导体绝缘体制品及其制造方法
公开(公告)号：WO2004073043A2
公开(公告)日：2004-08-26
申请号：PCT/US2004/004253
申请日：2004-02-13
申请人： MASSACHUSETTS INSTITUTE OF TECHNOLOGY , CHENG, Zhiyuan , FITZGERALD, Eugene, A.
发明人： CHENG, Zhiyuan , FITZGERALD, Eugene, A.
IPC分类号： H01L
CPC分类号： H01L21/76245 , H01L21/02378 , H01L21/02381 , H01L21/02439 , H01L21/02447 , H01L21/0245 , H01L21/02488 , H01L21/02502 , H01L21/02513 , H01L21/02521 , H01L21/02532
摘要： A semiconductor structure includes a substrate. A first semiconductor layer is formed on the substrate and being converted into a porous layer. The porous layer is further oxidized to form a buried oxide layer.
摘要翻译：半导体结构包括基板。在衬底上形成第一半导体层并将其转变成多孔层。多孔层被进一步氧化以形成掩埋氧化物层。

7. 发明申请

WO2006135906A2 ELECTRO-ABSORPTION MODULATOR DEVICE AND METHODS FOR FABRICATING THE SAME 审中-公开
标题翻译：电吸收式调制器装置及其制造方法
公开(公告)号：WO2006135906A2
公开(公告)日：2006-12-21
申请号：PCT/US2006/023050
申请日：2006-06-13
申请人： MASSACHUSETTS INSTITUTE OF TECHNOLOGY , DOHRMAN, Carl , FITZGERALD, Eugene, A. , GUPTA, Saurabh
发明人： DOHRMAN, Carl , FITZGERALD, Eugene, A. , GUPTA, Saurabh
IPC分类号： G02F1/017 , H01L29/15
CPC分类号： B82Y20/00 , G02F1/017 , G02F2001/0157 , G02F2001/01791
摘要： An electro-absorption light intensity modulator device includes a first and a second layer. The first layer includes a first insulator layer, and the second layer is disposed relative to the first layer to provide a light-absorbing optical confinement region. The light-absorbing optical confinement region includes at least one quantum- confined structure. The quantum-confined structure possesses dimensions such that, upon an application of an electric field in the quantum-confined structure, light absorption is at least partially due to a transition of at least one carrier between a valence state and a conduction state of the quantum-confined structure. A method of fabricating an electro-absorption light intensity modulator device includes providing a first layer including a first insulator layer, and disposing a second layer relative to the first layer to provide the light-absorbing optical confinement region.
摘要翻译：电吸收光强度调制器装置包括第一层和第二层。第一层包括第一绝缘体层，并且第二层相对于第一层设置以提供光吸收光限制区域。光吸收光限制区域包括至少一个量子限制结构。量子限制结构具有这样的维度，使得在量子限制结构中施加电场时，光吸收至少部分是由于至少一个载流子在数量态与导电状态之间的过渡有限的结构。一种制造电吸收光强度调制器件的方法包括提供包括第一绝缘体层的第一层和相对于第一层设置第二层以提供光吸收光限制区域。

8. 发明申请

WO2006039715A1 SEMICONDUCTOR DEVICES HAVING BONDED INTERFACES AND METHODS FOR MAKING THE SAME 审中-公开
标题翻译：具有粘合界面的半导体器件及其制造方法
公开(公告)号：WO2006039715A1
公开(公告)日：2006-04-13
申请号：PCT/US2005/035828
申请日：2005-10-03
申请人： MASSACHUSETTS INSTITUTE OF TECHNOLOGY , ISAACSON, David, M. , TARASCHI, Gianni , FITZGERALD, Eugene, A.
发明人： ISAACSON, David, M. , TARASCHI, Gianni , FITZGERALD, Eugene, A.
IPC分类号： H01L21/336 , C30B25/18
CPC分类号： H01L29/1054 , C30B25/18 , H01L21/187 , H01L21/823807 , H01L29/4916 , H01L29/4925 , H01L29/495 , H01L29/4966 , H01L29/78
摘要： A semiconductor-based structure includes first, second, and intermediate layers, with the intermediate layer bonded directly to the first layer, and in contact with the second layer. Parallel to the bonded interface, the lattice spacing of the second layer is different than the lattice spacing of the first layer, though first and second layers are each formed of essentially the same semiconductor. A method for making a semiconductor-based structure includes directly bonding a first layer to an intermediate layer, and providing a second layer in contact with the intermediate layer.
摘要翻译：基于半导体的结构包括第一，第二和中间层，中间层直接结合到第一层，并与第二层接触。平行于键合界面，第二层的晶格间距与第一层的晶格间隔不同，尽管第一和第二层各自由基本上相同的半导体形成。制造基于半导体的结构的方法包括将第一层直接结合到中间层，以及提供与中间层接触的第二层。

9. 发明申请

WO2004093223A2 INTEGRATED THIN FILM BATTERIES ON SILICON INTEGRATED CIRCUITS 审中-公开
标题翻译：硅集成电路集成薄膜电池
公开(公告)号：WO2004093223A2
公开(公告)日：2004-10-28
申请号：PCT/US2004/011350
申请日：2004-04-13
申请人： MASSACHUSETTS INSTITUTE OF TECHNOLOGY , ARIEL, Nava , FITZGERALD, Eugene, A. , SADOWAY, Donald, R. , CEDER, Gerbrand
发明人： ARIEL, Nava , FITZGERALD, Eugene, A. , SADOWAY, Donald, R. , CEDER, Gerbrand
IPC分类号： H01M6/00
CPC分类号： H01M10/0562 , H01M4/0428 , H01M4/386 , H01M6/185 , H01M6/40 , H01M10/0436 , H01M10/052 , H01M10/0585 , H01M10/425 , H01M2004/021 , H01M2300/0071 , Y10T29/49108 , Y10T29/49115
摘要： A solid-state battery including at least one thin film layer, and method for making same.
摘要翻译：包括至少一个薄膜层的固态电池及其制造方法。

10. 发明申请

WO2010098876A2 DIGITAL METAMORPHIC ALLOYS FOR GRADED BUFFERS 审中-公开
标题翻译：用于分级缓冲器的数字变形合金
公开(公告)号：WO2010098876A2
公开(公告)日：2010-09-02
申请号：PCT/US2010/000591
申请日：2010-02-26
申请人： MASSACHUSETTS INSTITUTE OF TECHNOLOGY , LEE, Kenneth, E. , FITZGERALD, Eugene, A.
发明人： LEE, Kenneth, E. , FITZGERALD, Eugene, A.
IPC分类号： H01L21/20
CPC分类号： H01L21/02543 , H01L21/02395 , H01L21/02461 , H01L21/02463 , H01L21/02507 , H01L21/0251 , H01L21/0262 , Y10T428/2495
摘要： Digital metamorphic alloy (DMA) buffer structures for transitioning from a bottom crystalline layer to a lattice mismatched top crystalline layer, and methods for manufacturing such layers are described. In some embodiments, a layered crystalline structure includes a first layer of a first crystalline material having a fist in-plane lattice constant and a second layer of a second crystalline material disposed over the first layer and having a second in-plane lattice constant that is lattice mismatched with the first crystalline material. Multiple sets of buffer layers may be disposed between the first layer and the second layer. Each set is a digital metamorphic alloy including a buffer layer of a third crystalline material and a buffer layer of a fourth crystalline material where an effective in-plane lattice constant of each set falls between the first lattice of the first layer and the second lattice constant of the second layer.
摘要翻译：描述了用于从底部晶体层向晶格失配顶部晶体层转变的数字变质合金（DMA）缓冲结构，以及用于制造这种层的方法。在一些实施例中，层状晶体结构包括具有第一面内晶格常数的第一晶体材料的第一层和设置在第一层上且具有第二面内晶格常数的第二晶体材料的第二层，晶格与第一晶体材料不匹配。多组缓冲层可以设置在第一层和第二层之间。每组是包括第三晶体材料的缓冲层和第四晶体材料的缓冲层的数字变质合金，其中每组的有效面内晶格常数落入第一层的第一晶格和第二晶格常数之间的第二层。

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