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1. 发明申请

WO2004095564A1 METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE WITH A BIPOLAR TRANSISTOR 审中-公开
标题翻译：用双极晶体管制造半导体器件的方法
公开(公告)号：WO2004095564A1
公开(公告)日：2004-11-04
申请号：PCT/IB2004/050497
申请日：2004-04-23
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , MAGNEE, Petrus, H., C. , HUETING, Raymond, J., E. , MELAI, Joost , IN 'T ZANDT, Michael, A., A. , DONKERS, Johannes, J., T., M.
发明人： MAGNEE, Petrus, H., C. , HUETING, Raymond, J., E. , MELAI, Joost , IN 'T ZANDT, Michael, A., A. , DONKERS, Johannes, J., T., M.
IPC分类号： H01L21/331
CPC分类号： H01L29/66242 , H01L21/76895 , H01L29/7378
摘要： Method of manufacturing a semiconductor device with a bipolar transistor, in which method, on a surface (3) of a silicon body comprising a surface layer (2) of a first conductivity type lying on a heavily doped contact layer (6) of the same, first conductivity type, a first layer of semiconductor material (8) is formed in which layer the base (21) is to be formed. In this method, a mask (9) is formed on the first layer of semiconductor material at the location of the base to be formed, after which non-covered parts of the first layer of semiconductor material are successively etched away and replaced by a layer of doped amorphous or polycrystalline silicon. Next, the mask is removed, whereby a window (17) is formed at the location of the base in which a second layer of semiconductor material (19) of the first conductivity type is deposited for forming the emitter (20) of the transistor. Thus a transistor is formed, the base of which is contacted by a highly conductive base contact (15) formed in the layer of doped amorphous or polycrystalline silicon.
摘要翻译：制造具有双极性晶体管的半导体器件的方法，在该方法中，在硅体的表面（3）上，该硅体包括位于其上的重掺杂接触层（6）上的第一导电类型的表面层（2），第一导电型，形成第一半导体材料层（8），其中将形成基底（21）。在该方法中，在要形成的基底的位置处，在第一半导体材料层上形成掩模（9），之后将第一半导体材料层的未覆盖部分相继蚀刻掉，并由层的掺杂非晶或多晶硅。接下来，去除掩模，由此在基底的位置处形成窗口（17），在该位置沉积第一导电类型的第二半导体材料层（19）以形成晶体管的发射极（20）。因此，形成晶体管，其基极由形成在掺杂的非晶或多晶硅层中的高导电性基极接触（15）接触。

2. 发明申请

WO2004057654A3 METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE 审中-公开
公开(公告)号：WO2004057654A3
公开(公告)日：2004-07-08
申请号：PCT/IB2003/006017
申请日：2003-12-16
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , INTERUNIVERSITAIR MICROELEKTRONICA CENTRUM VZW , MAGNEE, Petrus, H., C. , DONKERS, Johannes, J., T., M. , SHI, Xiaoping
发明人： MAGNEE, Petrus, H., C. , DONKERS, Johannes, J., T., M. , SHI, Xiaoping
IPC分类号： H01L21/20
摘要： Method of manufacturing a semiconductor device, in which on a region of silicon oxide (5) situated next to a region of monocrystalline silicon (4) at the surface (3) of a semiconductor body (1), a non-monocrystalline auxiliary layer (8) is formed. The auxiliary layer is formed in two steps. In the first step, the silicon body is heated in an atmosphere comprising a gaseous arsenic compound; in the second step it is heated in an atmosphere comprising a gaseous silicon compound instead of said arsenic compound. Thus, the regions of silicon oxide are provided with an amorphous or polycrystalline silicon seed layer in a self-aligned manner.

3. 发明申请

WO2003100845A1 METHOD OF FABRICATION SIGE HETEROJUNCTION BIPOLAR TRANSISTOR 审中-公开
标题翻译：制造异常双极晶体管的方法
公开(公告)号：WO2003100845A1
公开(公告)日：2003-12-04
申请号：PCT/IB2003/002034
申请日：2003-05-27
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , MAGNEE, Petrus, H., C. , DONKERS, Johannes, J., T., M.
发明人： MAGNEE, Petrus, H., C. , DONKERS, Johannes, J., T., M.
IPC分类号： H01L21/331
CPC分类号： H01L29/66242
摘要： The present invention provides for a method of fabricating a semiconductor device comprising a non-selectively grown SiGe(C) heterojunction bipolar transistor including the steps of forming an insulating layer (12, 40) on a substrate and providing a layer structure including a conductive layer (14, 42) on the insulating layer (12, 40), etching a transistor area opening (12, 44) through the conductive layer (14, 42), depositing a SiGe base layer (24, 46) on the inner wall of the transistor area opening (22, 44) and forming an insulator (32, 52) on an upper surface so as to fill the transistor area opening wherein prior to the filling step, a nitride layer (30, 50) is formed as an inner layer of the transistor area opening (22, 44).
摘要翻译：本发明提供一种制造半导体器件的方法，该半导体器件包括非选择性生长的SiGe（C）异质结双极晶体管，包括以下步骤：在衬底上形成绝缘层（12,40），并提供包括导电层（14,42），通过所述导电层（14,42）蚀刻晶体管区域开口（12,44），在所述绝缘层（12,40）的内壁上沉积SiGe基底层（24,46）所述晶体管区域开口（22,44）并且在上表面上形成绝缘体（32,52）以便填充晶体管区域开口，其中在填充步骤之前，将氮化物层（30,50）形成为内部晶体管区域开口（22,44）的层。

4. 发明申请

WO2005059989A1 METHOD TO REDUCE SEEDLAYER TOPOGRAPHY IN BICMOS PROCESS 审中-公开
标题翻译：减少BICMOS工艺中SEEDLAYER TOPOGRAPHY的方法
公开(公告)号：WO2005059989A1
公开(公告)日：2005-06-30
申请号：PCT/IB2004/052742
申请日：2004-12-09
申请人： KONINKLIJKE PHILIPS ELECTRONICS, N.V. , U.S. PHILIPS CORPORATION , DONKERS, Johannes J.T.M. , MAGNEE, Petrus, H., C. , KUNNEN, Eddy , NEUILLY, Francois, I.
发明人： DONKERS, Johannes J.T.M. , MAGNEE, Petrus, H., C. , KUNNEN, Eddy , NEUILLY, Francois, I.
IPC分类号： H01L21/331
CPC分类号： H01L21/8249 , H01L29/66242 , H01L29/66272
摘要： A method for forming an epitaxial base layer in a bipolar device. The method comprises the steps of: providing a structure having a field isolation oxide region (12) adjacent to an active silicon region (10); forming a silicon nitride/silicon stack (14, 16) above the field isolation oxide region (12), wherein the silicon nitride/silicon stack (14, 16) includes a top layer of silicon (14) and a bottom layer of silicon nitride (16); performing an etch to the silicon nitride/silicon stack (14, 16) to form a stepped seed layer, wherein the top layer of silicon is etched laterally at the same time the bottom layer of silicon nitride is etched; and growing an Si/SiGe/Si stack (20) over the stepped seed layer and active region (10).
摘要翻译：一种在双极器件中形成外延基底层的方法。该方法包括以下步骤：提供具有与有源硅区域（10）相邻的场隔离氧化物区域（12）的结构; 在所述场隔离氧化物区域（12）上形成氮化硅/硅堆叠（14,16），其中所述氮化硅/硅堆叠（14,16）包括硅顶层（14）和底层氮化硅（16）; 对所述氮化硅/硅堆叠（14,16）进行蚀刻以形成阶梯式种子层，其中在蚀刻所述底层氮化硅的同时侧向蚀刻所述硅顶层; 以及在所述阶梯式种子层和有源区域（10）上生长Si / SiGe / Si堆叠（20）。

5. 发明申请

WO2005064687A1 SEMICONDUCTOR DEVICE COMPRISING A PN-HETEROJUNCTION 审中-公开
标题翻译：包含PN异常的半导体器件
公开(公告)号：WO2005064687A1
公开(公告)日：2005-07-14
申请号：PCT/IB2004/052864
申请日：2004-12-20
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , HURKX, Godefridus, A., M. , AGARWAL, Prabhat , BALKENENDE, Abraham, R. , MAGNEE, Petrus, H., C. , WAGEMANS, Melanie, M., H. , BAKKERS, Erik, P., A., M. , HIJZEN, Erwin, A.
发明人： HURKX, Godefridus, A., M. , AGARWAL, Prabhat , BALKENENDE, Abraham, R. , MAGNEE, Petrus, H., C. , WAGEMANS, Melanie, M., H. , BAKKERS, Erik, P., A., M. , HIJZEN, Erwin, A.
IPC分类号： H01L29/861
CPC分类号： H01L29/8611 , B82Y10/00 , H01L29/045 , H01L29/0665 , H01L29/0673 , H01L29/0676 , H01L29/2003 , H01L29/66136 , H01L29/66219 , H01L2924/0002 , H01L2924/00
摘要： An electric device is disclosed comprising a pn-heterojunction (4) formed by a nanowire (3) of 111-V semiconductor material and a semiconductor body (1) comprising a group IV semiconductor material. The nanowire (3) is positioned in direct contact with the surface (2) of the semiconductor body (1) and has a first conductivity type, the semiconductor body (1) has a second conductivity type opposite to the first conductivity type, the nanowire (3) forming with the semiconductor body (1) a pn-heterojunction (4). The nanowire of III-V semiconductor material can be used as a diffusion source (5) of dopant atoms into the semiconductor body. The diffused group III atoms and/or the group V atoms from the III-V material are the dopant atoms forming a region (6) in the semiconductor body in direct contact with the nanowire (3).
摘要翻译：公开了一种电子器件，其包括由111-V半导体材料的纳米线（3）形成的pn异质结（4）和包含IV族半导体材料的半导体本体（1）。纳米线（3）与半导体本体（1）的表面（2）直接接触并且具有第一导电类型，半导体本体（1）具有与第一导电类型相反的第二导电类型，纳米线（3）与半导体本体（1）形成pn异质结（4）。 III-V族半导体材料的纳米线可以用作半导体本体中掺杂剂原子的扩散源（5）。来自III-V材料的扩散的III族原子和/或V族原子是在半导体本体中与纳米线（3）直接接触形成区域（6）的掺杂剂原子。

6. 发明申请

WO2006011069A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：WO2006011069A1
公开(公告)日：2006-02-02
申请号：PCT/IB2005/052263
申请日：2005-07-07
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , HURKX, Godefridus, A., M. , AGARWAL, Prabhat , BALKENENDE, Abraham, R. , MAGNEE, Petrus, H., C. , WAGEMANS, Melanie, M., H. , BAKKERS, Erik, P., A., M. , HIJZEN, Erwin
发明人： HURKX, Godefridus, A., M. , AGARWAL, Prabhat , BALKENENDE, Abraham, R. , MAGNEE, Petrus, H., C. , WAGEMANS, Melanie, M., H. , BAKKERS, Erik, P., A., M. , HIJZEN, Erwin
IPC分类号： H01L29/08
CPC分类号： H01L29/0804 , B82Y10/00 , H01L29/0665 , H01L29/0673 , H01L29/0676 , H01L29/0821 , H01L29/7378 , Y10S977/936
摘要： The invention relates to a semiconductor device (10) with a semiconductor body (12) comprising a bipolar transistor with an emitter region, a base region and a collector region (1, 2, 3) of, respectively, a first conductivity type, a second conductivity type opposite to the first conductivity type, and the first conductivity type. One of the emitter or collector regions (1, 3) comprises a nanowire (30). The base region (2) has been formed from a layer (20) at the surface of the semiconductor body (12); the other one (3, 1) of the emitter or collector regions (1, 3) has been formed in the semiconductor body (12) below the base region (2). The emitter or collector region (1, 3) comprising the nanowire (30) has been provided on the surface of the semiconductor body (12) such that its longitudinal axis extends perpendicularly to the surface.
摘要翻译：本发明涉及具有半导体本体（12）的半导体器件（10），该半导体器件（12）包括分别具有第一导电类型的发射极区，基极区和集电极区（1,2,3）的双极晶体管，与第一导电类型相反的第二导电类型和第一导电类型。发射极或集电极区域（1,3）中的一个包括纳米线（30）。基底区域（2）由半导体本体（12）表面的层（20）形成; 发射极或集电极区域（1,3）中的另一个（3,1）已经形成在基极区域（2）下方的半导体本体（12）中。包括纳米线（30）的发射极或集电极区域（1,3）已经设置在半导体本体（12）的表面上，使得其纵向轴线垂直于该表面延伸。

7. 发明申请

WO2005104232A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SUCH A DEVICE 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：WO2005104232A1
公开(公告)日：2005-11-03
申请号：PCT/IB2005/051293
申请日：2005-04-20
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V., , VAN NOORT, Wibo, D. , MAGNEE, Petrus, H., C. , NANVER, Lis, K. , DETCHEVERRY, Celine, J. , HAVENS, Ramon, J.
发明人： VAN NOORT, Wibo, D. , MAGNEE, Petrus, H., C. , NANVER, Lis, K. , DETCHEVERRY, Celine, J. , HAVENS, Ramon, J.
IPC分类号： H01L27/08
CPC分类号： H01L27/08 , H01L27/0641
摘要： The invention relates to a semiconductor device (10) comprising a semiconductor body (1) with a high-ohmic semiconductor substrate (2) which is covered with a dielectric layer (3, 4) containing charges, on which dielectric layer one or more passive electronic components (20) comprising conductor tracks (20) are provided, wherein, at the location of the passive elements (20), a region (5) is present at the interface between the semiconductor substrate (2) and the dielectric layer (3, 4), as a result of which the conductivity of an electrically conducting channel induced in the device (10) by the charges is limited at the location of the region (5). According to the invention, the region (5) is formed by deposition and comprises a semi-insulating material. As a result, the device (10) has a very low high-frequency power loss because the inversion channel is formed in the semi-insulating region (5). The device (10) further allows for a higher temperature budget and hence for the integration of active semiconductor elements (8) into the semiconductor body (1). A very suitable semi-insulating material for the region (5) is SiC, SIPOS or POLYDOX.
摘要翻译：本发明涉及一种半导体器件（10），其包括具有高欧姆半导体衬底（2）的半导体本体（1），所述半导体本体（1）被包含电荷的介电层（3,4）覆盖，电介质层上有一个或多个被动提供了包括导体轨道（20）的电子部件（20），其中在无源元件（20）的位置处，在半导体衬底（2）和电介质层（3）之间的界面处存在区域（5），4），其结果是，通过电荷在器件（10）中感应的导电沟道的导电性被限制在区域（5）的位置。根据本发明，区域（5）通过沉积形成并且包括半绝缘材料。结果，由于在半绝缘区域（5）中形成反转沟道，所以器件（10）具有非常低的高频功率损耗。器件（10）还允许更高的温度预算，并且因此用于将有源半导体元件（8）集成到半导体本体（1）中。用于区域（5）的非常合适的半绝缘材料是SiC，SIPOS或POLYDOX。

8. 发明申请

WO2009133506A3 MEMS DEVICE AND MANUFACTURING METHOD 审中-公开
公开(公告)号：WO2009133506A3
公开(公告)日：2009-11-05
申请号：PCT/IB2009/051685
申请日：2009-04-24
申请人： NXP B.V. , MAGNEE, Petrus, H., C.
发明人： MAGNEE, Petrus, H., C.
IPC分类号： B81C1/00
摘要： A method of forming a MEMS device, in which a MEMS device portion (20) is formed as a patterned portion of the silicon layer (14) of an SOI substrate (10,12,14). The MEMS device portion (20) is covered with a sacrificial layer (22) and a cap layer (26), so that further processing above or around the MEMS device can be implemented using standard CMOS processing, to form integrated circuit components (30). The MEMS device is completed by forming an opening (33) in the base layer (10) of the SOI substrate beneath the MEMS device portion and using the opening to remove the insulator layer of the SOI substrate and the sacrificial layer, thereby providing a space above and below the MEMS device portion. The opening in the base layer is closed with a further substrate (34).

9. 发明申请

WO2002059978A1 POWER BIPOLAR TRANSISTOR 审中-公开
标题翻译：电力双极晶体管
公开(公告)号：WO2002059978A1
公开(公告)日：2002-08-01
申请号：PCT/IB2001/002655
申请日：2001-12-19
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V.
发明人： MAGNEE, Petrus, H., C. , HUIZING, Hendrik, G. A. , VAN RIJS, Freerk
IPC分类号： H01L29/732
CPC分类号： H01L29/7322 , H01L29/0692 , H01L29/0821
摘要： The present invention relates to semi-conductor device comprising: a substrate (2); a first semi-conducting region (4) of a first conductive type adjacent to the substrate and provided with a first contact part arranged on the side of the device situated opposite the substrate; a second semi-conducting region (14) of a second opposite conductive type the centre line of which extends in the form of a polygon, which region has a first junction to the first semi-conducting region and which is provided with a second contact part arranged on the side of the device situated opposite the substrate; a third semi-conducting region (18) of the same conductive type as the first semi-conducting region, the centre line of which extends in the form of a polygon, which region has a first junction to the second semi-conducting region and which is provided with a third contact part arranged on the side of the device situated opposite the substrate.
摘要翻译：本发明涉及半导体器件，包括：衬底（2）; 第一导电类型的第一半导体区域（4），其邻近所述衬底并且设置有布置在所述器件的与所述衬底相对的侧面上的第一接触部分; 第二相对导电类型的第二半导体区域（14），其中心线以多边形的形式延伸，该区域具有到第一半导电区域的第一结，并且设置有第二接触部分布置在位于与衬底相对的装置的侧面上; 与第一半导电区域相同的导电类型的第三半导体区域（18），其中心线以多边形的形式延伸，该区域具有到第二半导电区域的第一结，并且设置有设置在与衬底相对的装置的侧面上的第三接触部分。

10. 发明申请

WO2003043089A1 A FIELD EFFECT TRANSISTOR SEMICONDUCTOR DEVICE 审中-公开
标题翻译：场效应晶体管半导体器件
公开(公告)号：WO2003043089A1
公开(公告)日：2003-05-22
申请号：PCT/IB2002/004759
申请日：2002-11-13
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V.
发明人： HUETING, Raymond, J., E. , SLOTBOOM, Jan, W. , MAGNEE, Petrus, H., C.
IPC分类号： H01L29/06
CPC分类号： H01L29/7813 , H01L29/0653 , H01L29/405 , H01L29/407 , H01L29/408 , H01L29/4236 , H01L29/66696 , H01L29/66727 , H01L29/7395 , H01L29/7722 , H01L29/7787 , H01L29/7803 , H01L29/7806 , H01L29/7824 , H01L29/7825 , H01L29/812 , H01L29/8122
摘要： A field effect transistor semiconductor device (1) comprises a source region (33), a drain region (14) and a drain drift region (11), the device having a field shaping region (20) adjacent the drift region (11) and arranged such that, in use, when a voltage is applied between the source (33) and drain (14) regions and the device is non-conducting, a substantially constant electric field is generated in the field shaping region (20) and accordingly in the adjacent drift region (11). The field shaping region (20), which may be intrinsic semiconductor, is arranged to function as a capacitor dielectric region (20) between a first capacitor electrode region (21) and a second capacitor electrode region (22), the first and second capacitor electrode regions (21, 22) being adjacent respective ends of the dielectric region (20) and having different electron energy barriers. The first and second capacitor electrode regions (21, 22) may be opposite conductivity semiconductor regions, or they may be a semiconductor region (21) and a Schottky barrier region (224, Figure 4). The device may be an insulated gate device (1, 13, 15, 17, 171, 172, 19, 12) particularly suitable for high or low voltage DC power applications, or a Schottky gate device (181, 182, 183) particularly suitable for RF applications.
摘要翻译：场效应晶体管半导体器件（1）包括源极区（33），漏极区（14）和漏极漂移区（11），该器件具有与漂移区（11）相邻的场整形区（20）和被布置为使得在使用中，当在源极（33）和漏极（14）区域之间施加电压并且器件不导通时，在场成形区域（20）中产生基本恒定的电场，因此在相邻的漂移区域（11）。可以将本征半导体的场成形区域（20）布置成用作第一电容器电极区域（21）和第二电容器电极区域（22）之间的电容器介电区域（20），第一和第二电容器电极区域（21,22）与电介质区域（20）的相应端部相邻并且具有不同的电子能量势垒。第一和第二电容器电极区域（21,22）可以与导电半导体区域相反，或者它们可以是半导体区域（21）和肖特基势垒区域（224，图4）。该器件可以是特别适用于高压或低压DC电源应用的绝缘栅极器件（1,13,15,17,171,172,19,12），或特别合适的肖特基栅极器件（181,182,183）用于射频应用。

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