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1. 发明申请

WO2004044766A3 DEVICE FOR PARALLEL DATA PROCESSING AS WELL AS A CAMERA SYSTEM COMPRISING SUCH A DEVICE 审中-公开
标题翻译：用于并行数据处理的装置，作为包含这种装置的相机系统
公开(公告)号：WO2004044766A3
公开(公告)日：2005-03-31
申请号：PCT/IB0350018
申请日：2003-11-06
申请人： KONINKL PHILIPS ELECTRONICS NV , SEVAT LEONARDUS H M , KLEIHORST RICHARD P , NIEUWLAND ANDRE K
发明人： SEVAT LEONARDUS H M , KLEIHORST RICHARD P , NIEUWLAND ANDRE K
IPC分类号： G06F15/80 , G06F17/00 , H04N5/225 , H04N5/335 , H04N9/04
CPC分类号： H04N5/335
摘要： The invention relates to a device for parallel data processing, a DSP. The device according to the invention comprises a processor matrix (100) in which processors (103) are arranged in rows (101) and columns (102). Furthermore, the device (100) comprises first and second external data ports (107, 108). The rows (101) arranged in a stepwise manner and the columns are arranged in a stepwise manner. The processors (103) have a first processor data port (104), which is connected with one of the first external data ports (107) by means of first essentially straight connection. The processors (103) further comprise a second processor data port (105), which is connected with one of the second external data ports (108) by means of an essentially straight second connection (110). The first connection (107) and the second connection (108) are oriented substantially orthogonal to each other. A problem associated with conventional DSPs is that the connections to and from the processors within the DSP take up large amounts of silicon area. By arranging both rows and columns of the DSP according to the invention in a stepwise manner the connections may be essentially straight, thus minimizing their lengths and thus the surface area occupied.
摘要翻译：本发明涉及一种用于并行数据处理的设备，一种DSP。根据本发明的装置包括处理器矩阵（100），其中处理器（103）被布置成行（101）和列（102）。此外，设备（100）包括第一和第二外部数据端口（107,108）。行（101）以逐步方式布置并且列以逐步的方式布置。处理器（103）具有第一处理器数据端口（104），其通过第一基本上直的连接与第一外部数据端口（107）中的一个连接。处理器（103）还包括第二处理器数据端口（105），其通过基本上直的第二连接（110）与第二外部数据端口（108）之一连接。第一连接（107）和第二连接（108）彼此基本正交。与常规DSP相关的一个问题是与DSP内部的处理器的连接占用大量的硅面积。通过按照本发明以逐步的方式布置DSP的行和列，连接可以是基本上直的，从而使其长度最小化并因此使占用的表面积最小化。

2. 发明申请

WO2005106667A3 ERROR CORRECTION IN AN ELECTRONIC CIRCUIT 审中-公开
标题翻译：电子电路中的错误校正
公开(公告)号：WO2005106667A3
公开(公告)日：2006-03-02
申请号：PCT/IB2005051351
申请日：2005-04-26
申请人： KONINKL PHILIPS ELECTRONICS NV , NIEUWLAND ANDRE K , WIELAGE PAUL , KLEIHORST RICHARD P
发明人： NIEUWLAND ANDRE K , WIELAGE PAUL , KLEIHORST RICHARD P
IPC分类号： G06F11/00 , G06F11/10 , G11C7/22 , G11C7/24 , G11C11/406
CPC分类号： G06F11/1008 , G11C7/22 , G11C7/24 , G11C11/406 , G11C2211/4062
摘要： An electronic circuit has a data producing circuit (12), such as a matrix of memory cells. A capture circuit (14) has an input coupled to the data producing circuit (10) for capturing the data signals after allowing a selected part of the data producing circuit to drive the input of the capture circuit. An error detection circuit (15) detects errors in the captured data signals. In response to detection of an error in particular data signals, the error detection circuit causes recapture of the particular data signals, allowing the data producing circuit (10) to drive the data signals at the input of the capture circuit (14) during a second time interval until recapture, the second time interval having a longer duration than the first time interval. This makes it possible to select the duration of the first time interval allowing for average driving speed of circuit parts (e.g. memory cells), without using a duration designed to account for worst case driving speed that may occur due to spread. Errors caused by spread are corrected by rereading with an increased time interval for driving the input of the capture circuit. Preferably, the duration of the first time interval is regulated so that on average a predetermined error rate occurs.
摘要翻译：电子电路具有诸如存储器单元的矩阵的数据产生电路（12）。捕获电路（14）具有耦合到数据产生电路（10）的输入端，用于在允许数据产生电路的选定部分驱动捕获电路的输入之后捕获数据信号。误差检测电路（15）检测捕获的数据信号中的错误。响应于检测到特定数据信号中的错误，误差检测电路引起特定数据信号的再捕获，允许数据产生电路（10）在第二个时钟期间驱动捕获电路（14）的输入处的数据信号时间间隔直到重新捕获，第二时间间隔具有比第一时间间隔更长的持续时间。这使得可以选择允许电路部分（例如存储器单元）的平均驱动速度的第一时间间隔的持续时间，而不使用设计为考虑由于扩展可能发生的最坏情况驱动速度的持续时间。由扩展引起的错误通过用于驱动捕获电路的输入的增加的时间间隔进行重新读取来校正。优选地，调整第一时间间隔的持续时间，使得平均发生预定的错误率。

3. 发明申请

WO2005015415A3 DECODER CIRCUIT 审中-公开
标题翻译：解码器电路
公开(公告)号：WO2005015415A3
公开(公告)日：2005-05-12
申请号：PCT/IB2004051404
申请日：2004-08-05
申请人： KONINKL PHILIPS ELECTRONICS NV , KLEIHORST RICHARD P , VAN DIJK VICTOR E S , NIEUWLAND ANDRE K
发明人： KLEIHORST RICHARD P , VAN DIJK VICTOR E S , NIEUWLAND ANDRE K
IPC分类号： G06F13/40
CPC分类号： G06F13/4072 , Y02D10/14 , Y02D10/151
摘要： A decoder circuit, for example a dual-rail decoder, receives input signals (43) from the end of a communications bus (not shown). The parity is calculated over the data wires (Do, D1, D2, D3) using exclusive OR gates (45, 47 and 49). The calculated data parity signal (51) is compared with a transmitted parity signal (53) (shown as "carry") in an exclusive OR gate (55). Rather than connecting the control signal (57) from the exclusive OR gate (55) directly to the multiplexers (590, 591, 592, 593), the control signal (57) is instead connected to a gating circuit (71). The gating circuit (71), for example a AND gate, receives the control signal (57) as a first input signal. The gating circuit (71) also receives a second input signal in the form of a gating control signal (73). The gating control signal (73) is delayed by a predetermined amount, for example corresponding to the worst case delay of the signals in the input data signals (43). Thus, the gating control signal (73) does not control the gating circuit until such time as all of the data signals are valid, ie until the last transition on the data signal (43) has occurred, thereby preventing glitches and reducing power consumption in the decoder circuit.
摘要翻译：解码器电路，例如双轨解码器，从通信总线（未示出）的末端接收输入信号（43）。使用异或门（45,47和49）在数据线（Do，D1，D2，D3）上计算奇偶校验。将计算出的数据奇偶校验信号（51）与异或门（55）中的发送奇偶校验信号（53）（示为“进位”）进行比较。不是将控制信号（57）从异或门（55）直接连接到多路复用器（590,591,592,593），而是将控制信号（57）连接到门控电路（71）。门控电路（71）（例如与门）接收控制信号（57）作为第一输入信号。选通电路（71）还接收门控控制信号（73）形式的第二输入信号。选通控制信号（73）被延迟预定量，例如对应于输入数据信号（43）中信号的最差情况延迟。因此，选通控制信号（73）不控制门控电路，直到所有数据信号有效，即直到数据信号（43）上的最后一个转换发生为止，从而防止毛刺和降低功耗解码电路。

4. 发明申请

WO03005219A2 MULTIPROCESSOR SYSTEM AND METHOD FOR OPERATING A MULTIPROCESSOR SYSTEM 审中-公开
标题翻译：用于操作多处理器系统的多处理器系统和方法
公开(公告)号：WO03005219A2
公开(公告)日：2003-01-16
申请号：PCT/IB0202337
申请日：2002-06-20
申请人： KONINKL PHILIPS ELECTRONICS NV , KANG I-CHIH , GANGWAL OM P , NIEUWLAND ANDRE K
发明人： KANG I-CHIH , GANGWAL OM P , NIEUWLAND ANDRE K
IPC分类号： G06F9/38 , G06F9/46 , G06F9/52 , G06F15/16 , G06F15/177 , H04L7/00
CPC分类号： G06F5/12 , G06F9/52 , G06F2205/102
摘要： A multiprocessor system according to the invention comprises at least a dedicated processor (1, 6) and a further processor (1, 3), and a memory (1, 5) shared by the processors. The shared memory (1, 5) and processors (1, 6, 1, 3) are coupled to an interconnect ion network (1, 7). The processors are arranged for transferring data to each other via a buffer (2, 1) in accordance with a synchronization protocol. The dedicated processor (1, 3) comprises facilities for administrating information relating to the synchronization protocol and a copy of at least part of this information is maintained in the shared memory (2, 1).
摘要翻译：根据本发明的多处理器系统至少包括由处理器共享的专用处理器（1,6）和另外的处理器（1,3）以及存储器（1,5）。共享存储器（1,5）和处理器（1,6,1,3）被耦合到互连离子网络（1,7）。处理器被安排用于根据同步协议经由缓冲器（2,1）将数据彼此传送。专用处理器（1,3）包括用于管理与同步协议有关的信息的设施，并且该信息的至少一部分的副本被保存在共享存储器（2,1）中。

5. 发明申请

WO2007017839A2 TESTING OF AN INTEGRATED CIRCUIT THAT CONTAINS SECRET INFORMATION 审中-公开
标题翻译：包含秘密信息的集成电路的测试
公开(公告)号：WO2007017839A2
公开(公告)日：2007-02-15
申请号：PCT/IB2006052748
申请日：2006-08-09
申请人： KONINKL PHILIPS ELECTRONICS NV , NIEUWLAND ANDRE K , GOEL SANDEEPKUMAR , MARINISSEN ERIK J , VERMEULEN HUBERTUS G H , VRANKEN HENDRIKUS P E
发明人： NIEUWLAND ANDRE K , GOEL SANDEEPKUMAR , MARINISSEN ERIK J , VERMEULEN HUBERTUS G H , VRANKEN HENDRIKUS P E
IPC分类号： G01R31/317
CPC分类号： G01R31/318541 , G01R31/31719
摘要： An integrated circuit (10) comprises a scan chain (14) with parallel inputs and outputs coupled to a functional circuit (12a-c). A scan chain modifying circuit (43, 47, 70a-c) is provided coupled to the scan chain (14). When testing is authorized the scan chain modifying circuit operates in a mode wherein a normal shift path is provided through the scan chain. When testing is not authorized the scan chain modifying circuit (43, 47, 70a-c) operates to effect spontaneous dynamic changes in the shift path, which dynamically vary the length of the shift path between external terminals of the integrated circuit while shifting takes place. In an embodiment the dynamical variations are controlled by a running key comparison. In other embodiments running key comparison is used to disable transfer through the scan chain and/or operation of functional circuits.
摘要翻译：集成电路（10）包括具有耦合到功能电路（12a-c）的并行输入和输出的扫描链（14）。扫描链修改电路（43,47,70a-c）被提供为耦合到扫描链（14）。当测试被授权时，扫描链修改电路以其中通过扫描链提供正常移位路径的模式操作。当测试未被授权时，扫描链修改电路（43,47,70a-c）操作以实现移位路径中的自发动态变化，其在移位发生时动态地改变集成电路的外部端子之间的移位路径的长度。在一个实施例中，动态变化由运行键比较来控制。在其他实施例中，运行密钥比较被用于禁止通过扫描链的传输和/或功能电路的操作。

6. 发明申请

WO2006059269A2 ELECTRONIC DEVICE HAVING LOGIC CIRCUITRY AND METHOD FOR DESIGNING LOGIC CIRCUITRY 审中-公开
标题翻译：具有逻辑电路的电子器件和用于设计逻辑电路的方法
公开(公告)号：WO2006059269A2
公开(公告)日：2006-06-08
申请号：PCT/IB2005053932
申请日：2005-11-28
申请人： KONINKL PHILIPS ELECTRONICS NV , NIEUWLAND ANDRE K , HEIJMEN THEODORUS G A
发明人： NIEUWLAND ANDRE K , HEIJMEN THEODORUS G A
IPC分类号： H03K19/007
CPC分类号： H03K19/00338 , H03K19/00392
摘要： An electronic device with logic circuitry (LC) is provided. The logic circuitry (LC) comprises at least one electronic unit (EU), in particular one logic gate with a first electronic component (ECl) for performing logic operations; and at least one second electronic component (EC2) for improving the soft-error sensitivity of the logic circuitry (LC). The first and the second electronic component (ECl, EC2) are implemented with substantially the same logical function. The second electronic component (EC2) is redundant. In addition, the inputs of the first and the second electronic component (ECl, E2) are coupled and the outputs of the first and the second electronic component (ECl, E2) are coupled, respectively.
摘要翻译：提供具有逻辑电路（LC）的电子设备。逻辑电路（LC）包括至少一个电子单元（EU），特别是具有用于执行逻辑操作的第一电子部件（EC1）的一个逻辑门; 和至少一个第二电子元件（EC2），用于改善逻辑电路（LC）的软错误灵敏度。第一和第二电子部件（EC1，EC2）以基本上相同的逻辑功能来实现。第二个电子元件（EC2）是多余的。另外，第一和第二电子部件（EC1，E2）的输入端被耦合，并且第一和第二电子部件（EC1，E2）的输出端分别被耦合。

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