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1. 发明申请

WO2005106667A3 ERROR CORRECTION IN AN ELECTRONIC CIRCUIT 审中-公开
标题翻译：电子电路中的错误校正
公开(公告)号：WO2005106667A3
公开(公告)日：2006-03-02
申请号：PCT/IB2005051351
申请日：2005-04-26
申请人： KONINKL PHILIPS ELECTRONICS NV , NIEUWLAND ANDRE K , WIELAGE PAUL , KLEIHORST RICHARD P
发明人： NIEUWLAND ANDRE K , WIELAGE PAUL , KLEIHORST RICHARD P
IPC分类号： G06F11/00 , G06F11/10 , G11C7/22 , G11C7/24 , G11C11/406
CPC分类号： G06F11/1008 , G11C7/22 , G11C7/24 , G11C11/406 , G11C2211/4062
摘要： An electronic circuit has a data producing circuit (12), such as a matrix of memory cells. A capture circuit (14) has an input coupled to the data producing circuit (10) for capturing the data signals after allowing a selected part of the data producing circuit to drive the input of the capture circuit. An error detection circuit (15) detects errors in the captured data signals. In response to detection of an error in particular data signals, the error detection circuit causes recapture of the particular data signals, allowing the data producing circuit (10) to drive the data signals at the input of the capture circuit (14) during a second time interval until recapture, the second time interval having a longer duration than the first time interval. This makes it possible to select the duration of the first time interval allowing for average driving speed of circuit parts (e.g. memory cells), without using a duration designed to account for worst case driving speed that may occur due to spread. Errors caused by spread are corrected by rereading with an increased time interval for driving the input of the capture circuit. Preferably, the duration of the first time interval is regulated so that on average a predetermined error rate occurs.
摘要翻译：电子电路具有诸如存储器单元的矩阵的数据产生电路（12）。捕获电路（14）具有耦合到数据产生电路（10）的输入端，用于在允许数据产生电路的选定部分驱动捕获电路的输入之后捕获数据信号。误差检测电路（15）检测捕获的数据信号中的错误。响应于检测到特定数据信号中的错误，误差检测电路引起特定数据信号的再捕获，允许数据产生电路（10）在第二个时钟期间驱动捕获电路（14）的输入处的数据信号时间间隔直到重新捕获，第二时间间隔具有比第一时间间隔更长的持续时间。这使得可以选择允许电路部分（例如存储器单元）的平均驱动速度的第一时间间隔的持续时间，而不使用设计为考虑由于扩展可能发生的最坏情况驱动速度的持续时间。由扩展引起的错误通过用于驱动捕获电路的输入的增加的时间间隔进行重新读取来校正。优选地，调整第一时间间隔的持续时间，使得平均发生预定的错误率。

2. 发明申请

WO2004044766A2 DEVICE FOR PARALLEL DATA PROCESSING AS WELL AS A CAMERA SYSTEM COMPRISING SUCH A DEVICE 审中-公开
标题翻译：用于并行数据处理的装置，作为包含这种装置的相机系统
公开(公告)号：WO2004044766A2
公开(公告)日：2004-05-27
申请号：PCT/IB2003/050018
申请日：2003-11-06
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , SEVAT, Leonardus, H., M. , KLEIHORST, Richard, P. , NIEUWLAND, Andre, K.
发明人： SEVAT, Leonardus, H., M. , KLEIHORST, Richard, P. , NIEUWLAND, Andre, K.
IPC分类号： G06F17/00
CPC分类号： H04N5/335
摘要： The invention relates to a device for parallel data processing, a DSP. The device according to the invention comprises a processor matrix (100) in which processors (103) are arranged in rows (101) and columns (102). Furthermore, the device (100) comprises first and second external data ports (107, 108). The rows (101) arranged in a stepwise manner and the columns are arranged in a stepwise manner. The processors (103) have a first processor data port (104), which is connected with one of the first external data ports (107) by means of first essentially straight connection. The processors (103) further comprise a second processor data port (105), which is connected with one of the second external data ports (108) by means of an essentially straight second connection (110). The first connection (107) and the second connection (108) are oriented substantially orthogonal to each other. A problem associated with conventional DSPs is that the connections to and from the processors within the DSP take up large amounts of silicon area. By arranging both rows and columns of the DSP according to the invention in a stepwise manner the connections may be essentially straight, thus minimizing their lengths and thus the surface area occupied.
摘要翻译：本发明涉及一种用于并行数据处理的设备，一种DSP。根据本发明的装置包括处理器矩阵（100），其中处理器（103）被布置成行（101）和列（102）。此外，设备（100）包括第一和第二外部数据端口（107,108）。行（101）以逐步方式布置并且列以逐步的方式布置。处理器（103）具有第一处理器数据端口（104），其通过第一基本上直的连接与第一外部数据端口（107）中的一个连接。处理器（103）还包括第二处理器数据端口（105），其通过基本上直的第二连接（110）与第二外部数据端口（108）之一连接。第一连接（107）和第二连接（108）彼此基本正交。与常规DSP相关的一个问题是与DSP内部的处理器的连接占用大量的硅面积。通过按照本发明以逐步的方式布置DSP的行和列，连接可以是基本上直的，从而使其长度最小化并因此使占用的表面积最小化。

3. 发明申请

WO2003088311A1 DATA COMMUNICATION BUS 审中-公开
标题翻译：数据通信总线
公开(公告)号：WO2003088311A1
公开(公告)日：2003-10-23
申请号：PCT/IB2003/001311
申请日：2003-04-01
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , ROSSI, Daniele , KLEIHORST, Richard, P. , NIEUWLAND, Andre, K. , VAN DIJK, Victor, E., S.
发明人： ROSSI, Daniele , KLEIHORST, Richard, P. , NIEUWLAND, Andre, K. , VAN DIJK, Victor, E., S.
IPC分类号： H01L
CPC分类号： H04L25/49
摘要： An electronic device has a data communication bus (200) mounted on a semiconductor substrate (120). The data communication bus (200) has a first conductor (102), a second conductor (104), a third conductor (106) and afourth conductor (108). The conductors have been reordered and the distances (l 1 , l 2 , l 3 ) between two neighboring conductors have been recalculated on the basis of the correlation between the data-bits conveyed by the conductors of the data communication bus (200), e.g. the number of times that the two transitions on two conductors have a predetermined value out of the total number of transitions on that conductor pair. Consequently, a data communication bus (200) is obtained in which the power consumption resulting from the charging of the cross-coupling capacitance between two neighboring conductors is reduced.
摘要翻译：电子设备具有安装在半导体衬底（120）上的数据通信总线（200）。数据通信总线（200）具有第一导体（102），第二导体（104），第三导体（106）和第二导体（108）。这些导体已被重新排序，并且基于由数据通信总线（200）的导体传送的数据位之间的相关性（例如，数据通信总线200）之间的相关性，已经重新计算了两个相邻导体之间的距离（11,1,23）。在两个导体上的两个跃迁的次数在该导体对上的总转换次数中具有预定值。因此，获得数据通信总线（200），其中由两个相邻导体之间的交叉耦合电容充电所产生的功耗减小。

4. 发明申请

WO2007017838A1 TESTING OF AN INTEGRATED CIRCUIT THAT CONTAINS SECRET INFORMATION 审中-公开
标题翻译：包含秘密信息的集成电路的测试
公开(公告)号：WO2007017838A1
公开(公告)日：2007-02-15
申请号：PCT/IB2006/052746
申请日：2006-08-09
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , MARINISSEN, Erik, J. , GOEL, Sandeepkumar , NIEUWLAND, Andre, K. , VERMEULEN, Hubertus, G., H. , VRANKEN, Hendrikus, P., E.
发明人： MARINISSEN, Erik, J. , GOEL, Sandeepkumar , NIEUWLAND, Andre, K. , VERMEULEN, Hubertus, G., H. , VRANKEN, Hendrikus, P., E.
IPC分类号： G01R31/317 , G01R31/3185
CPC分类号： G01R31/31719 , G01R31/318533
摘要： An integrated circuit (10) comprises a functional circuit (12a-c) that contain information that must be secured against unauthorized access. The integrated circuit comprises a test access circuit (14, 16) coupled to the functional circuit (12a-c), and a plurality of fuse elements (18) coupled to the test access circuit (14, 16). The fuse elements (18) are connected in a circuit configuration that makes the functional circuit (12a-c) consistently accessible via the test access circuit (14, 16) only when first fuse elements (18) of the plurality are in a blown state and second fuse elements (18) of the plurality are in a not-blown state. As a result the integrated circuit can be tested after selectively blowing all of the first fuse elements (18). After testing at least part of the second fuse elements (18) is blown. As a result, a person that does not know which fuse elements are first fuse elements and which are second fuse elements is presented with difficulties to restore the integrated circuit to a state where test access with the danger of access to the secured information is possible.
摘要翻译：集成电路（10）包括功能电路（12a-c），其包含必须防止未授权访问的信息。集成电路包括耦合到功能电路（12a-c）的测试访问电路（14,16）和耦合到测试访问电路（14,16）的多个熔丝元件（18）。保险丝元件（18）以仅在多个第一熔丝元件（18）处于吹制状态时通过测试存取电路（14,16）可一致地访问的电路配置连接并且多个的第二熔丝元件（18）处于未吹塑状态。结果，可以在选择性地吹扫所有第一熔丝元件（18）之后测试集成电路。在测试之后，至少部分第二熔丝元件（18）被吹塑。结果，不知道哪些熔丝元件是第一熔丝元件并且是第二熔丝元件的人被呈现难以将集成电路恢复到具有访问安全信息的危险的测试访问是可能的状态。

5. 发明申请

WO2005106667A2 ERROR CORRECTION IN AN ELECTRONIC CIRCUIT 审中-公开
标题翻译：电子电路中的错误校正
公开(公告)号：WO2005106667A2
公开(公告)日：2005-11-10
申请号：PCT/IB2005/051351
申请日：2005-04-26
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , NIEUWLAND, Andre, K. , WIELAGE, Paul , KLEIHORST, Richard, P.
发明人： NIEUWLAND, Andre, K. , WIELAGE, Paul , KLEIHORST, Richard, P.
IPC分类号： G06F11/00
CPC分类号： G06F11/1008 , G11C7/22 , G11C7/24 , G11C11/406 , G11C2211/4062
摘要： An electronic circuit has a data producing circuit (12), such as a matrix of memory cells. A capture circuit (14) has an input coupled to the data producing circuit (10) for capturing the data signals after allowing a selected part of the data producing circuit to drive the input of the capture circuit. An error detection circuit (15) detects errors in the captured data signals. In response to detection of an error in particular data signals, the error detection circuit causes recapture of the particular data signals, allowing the data producing circuit (10) to drive the data signals at the input of the capture circuit (14) during a second time interval until recapture, the second time interval having a longer duration than the first time interval. This makes it possible to select the duration of the first time interval allowing for average driving speed of circuit parts (e.g. memory cells), without using a duration designed to account for worst case driving speed that may occur due to spread. Errors caused by spread are corrected by rereading with an increased time interval for driving the input of the capture circuit. Preferably, the duration of the first time interval is regulated so that on average a predetermined error rate occurs.
摘要翻译：电子电路具有诸如存储器单元的矩阵的数据产生电路（12）。捕获电路（14）具有耦合到数据产生电路（10）的输入端，用于在允许数据产生电路的选定部分驱动捕获电路的输入之后捕获数据信号。误差检测电路（15）检测捕获的数据信号中的错误。响应于检测到特定数据信号中的错误，误差检测电路引起特定数据信号的再捕获，允许数据产生电路（10）在第二个时钟期间驱动捕获电路（14）的输入处的数据信号时间间隔直到重新捕获，第二时间间隔具有比第一时间间隔更长的持续时间。这使得可以选择允许电路部分（例如存储器单元）的平均驱动速度的第一时间间隔的持续时间，而不使用设计为考虑由于扩展可能发生的最坏情况驱动速度的持续时间。由扩展引起的错误通过用于驱动捕获电路的输入的增加的时间间隔进行重新读取来校正。优选地，调整第一时间间隔的持续时间，使得平均发生预定的错误率。

6. 发明申请

WO2005015415A3 DECODER CIRCUIT 审中-公开
标题翻译：解码器电路
公开(公告)号：WO2005015415A3
公开(公告)日：2005-05-12
申请号：PCT/IB2004051404
申请日：2004-08-05
申请人： KONINKL PHILIPS ELECTRONICS NV , KLEIHORST RICHARD P , VAN DIJK VICTOR E S , NIEUWLAND ANDRE K
发明人： KLEIHORST RICHARD P , VAN DIJK VICTOR E S , NIEUWLAND ANDRE K
IPC分类号： G06F13/40
CPC分类号： G06F13/4072 , Y02D10/14 , Y02D10/151
摘要： A decoder circuit, for example a dual-rail decoder, receives input signals (43) from the end of a communications bus (not shown). The parity is calculated over the data wires (Do, D1, D2, D3) using exclusive OR gates (45, 47 and 49). The calculated data parity signal (51) is compared with a transmitted parity signal (53) (shown as "carry") in an exclusive OR gate (55). Rather than connecting the control signal (57) from the exclusive OR gate (55) directly to the multiplexers (590, 591, 592, 593), the control signal (57) is instead connected to a gating circuit (71). The gating circuit (71), for example a AND gate, receives the control signal (57) as a first input signal. The gating circuit (71) also receives a second input signal in the form of a gating control signal (73). The gating control signal (73) is delayed by a predetermined amount, for example corresponding to the worst case delay of the signals in the input data signals (43). Thus, the gating control signal (73) does not control the gating circuit until such time as all of the data signals are valid, ie until the last transition on the data signal (43) has occurred, thereby preventing glitches and reducing power consumption in the decoder circuit.
摘要翻译：解码器电路，例如双轨解码器，从通信总线（未示出）的末端接收输入信号（43）。使用异或门（45,47和49）在数据线（Do，D1，D2，D3）上计算奇偶校验。将计算出的数据奇偶校验信号（51）与异或门（55）中的发送奇偶校验信号（53）（示为“进位”）进行比较。不是将控制信号（57）从异或门（55）直接连接到多路复用器（590,591,592,593），而是将控制信号（57）连接到门控电路（71）。门控电路（71）（例如与门）接收控制信号（57）作为第一输入信号。选通电路（71）还接收门控控制信号（73）形式的第二输入信号。选通控制信号（73）被延迟预定量，例如对应于输入数据信号（43）中信号的最差情况延迟。因此，选通控制信号（73）不控制门控电路，直到所有数据信号有效，即直到数据信号（43）上的最后一个转换发生为止，从而防止毛刺和降低功耗解码电路。

7. 发明申请

WO2003003232A3 DATA PROCESSING APPARATUS AND A METHOD OF SYNCHRONIZING A FIRST AND A SECOND PROCESSING MEANS IN A DATA PROCESSING APPARATUS 审中-公开
公开(公告)号：WO2003003232A3
公开(公告)日：2003-01-09
申请号：PCT/IB2002/002417
申请日：2002-06-20
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , NIEUWLAND, Andre, K. , LIPPENS, Paul, E., R. , GANGWAL, Om, P.
发明人： NIEUWLAND, Andre, K. , LIPPENS, Paul, E., R. , GANGWAL, Om, P.
IPC分类号： G06F9/46
摘要： A data processing apparatus according to the invention comprising at least a first (1.2) and a second processing means (1.3). The first processing means being capable of providing data by writing tokens in a buffer means (2.1) which are readable by the second processing means for further processing. The processing means are assigned a first and a second synchronization counter. The first synchronization counter (writec) is modifiable by the first processing means (2.1)and is readable by the second processing means (1.3). The second synchronization counter (readc) is modifiable by the second processing means (1.3), and readable by the first processing means (1.2). The first synchronization counter (writec) is indicative for a number of tokens being written by the first processing means (1.2). The second synchronization counter (readc) is indicative for a number of tokens being read by the second processing means (1.3).

8. 发明申请

WO2005088467A1 DATA COMMUNICATION MODULE PROVIDING FAULT TOLERANCE AND INCREASED STABILITY 审中-公开
标题翻译：数据通信模块提供故障容限和增加的稳定性
公开(公告)号：WO2005088467A1
公开(公告)日：2005-09-22
申请号：PCT/IB2005/050657
申请日：2005-02-23
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , NIEUWLAND, Andre, K.
发明人： NIEUWLAND, Andre, K.
IPC分类号： G06F13/12
CPC分类号： G06F11/10 , G06F13/4068
摘要： A module for transmitting sets of data bits to another module via a communication bus using dual-rail encoding is provided that has a reduced switching activity. The module comprises bus invert coding means adapted to compare a set of data bits with a preceding set of data bits to determine an indication of the number of transitions required to transmit the set of data bits; invert the set of data bits prior to transmission if it is determined that the number of transitions required to transmit the set of data bits is greater than half the total number of bits in the set of data bits; and provide an indication of whether the set of data bits has been inverted; the module also comprising means adapted to generate respective copies of the data bits in the set of data bits; and means adapted to transmit to the other module, via the communication bus, the set of data bits, their respective copies and the indication of whether the set of data bits has been inverted.
摘要翻译：提供了一种用于通过使用双轨编码的通信总线将数据位组发送到另一模块的模块，其具有降低的交换活动。该模块包括总线反转编码装置，适于将一组数据比特与前一组数据比特进行比较，以确定发送数据比特组所需的转换次数的指示; 如果确定发送该组数据位所需的转换次数大于该组数据位中的总位数的一半，则在发送之前反转数据位集合; 并提供该组数据位是否被反转的指示; 该模块还包括适于产生该组数据比特中的数据比特的相应拷贝的装置; 以及适于经由所述通信总线向所述另一个模块发送所述数据位集合，它们各自的副本以及所述数据位组是否已被反转的指示的装置。

9. 发明申请

WO2005088465A1 DATA COMMUNICATION USING FAULT TOLERANT ERROR CORRECTING CODES AND HAVING REDUCED GROUND BOUNCE 审中-公开
标题翻译：数据通信使用故障容错更正代码并减少接地电压
公开(公告)号：WO2005088465A1
公开(公告)日：2005-09-22
申请号：PCT/IB2005/050656
申请日：2005-02-23
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , KLEIHORST, Richard, P. , NIEUWLAND, Andre, K. , METRA, Cecilia , VAN DIJK, Victor, E., S.
发明人： KLEIHORST, Richard, P. , NIEUWLAND, Andre, K. , METRA, Cecilia , VAN DIJK, Victor, E., S.
IPC分类号： G06F13/00
CPC分类号： H04L1/0043 , H04L2001/0094
摘要： There is provided a first module for transmitting a plurality of data bits to a second module via a communication bus with reduced ground bounce, the first module comprising means adapted to generate respective copies of the data bits; means adapted to invert the respective copies of the data bits; and means adapted to transmit, via the communication bus, the plurality of data bits and their respective inverted copies to the second module. A parity signal and an inverted copy thereof may also be transmitted between the first module and the second module.
摘要翻译：提供了一种用于经由具有减少的接地反弹的通信总线将多个数据位发送到第二模块的第一模块，所述第一模块包括适于生成数据位的相应副本的装置; 用于反转所述数据位的各个副本的装置; 以及适于经由所述通信总线将所述多个数据位及其各自的反转副本发送到所述第二模块的装置。奇偶信号及其反转副本也可以在第一模块和第二模块之间传输。

10. 发明申请

WO2005015415A2 DECODER CIRCUIT 审中-公开
标题翻译：解码器电路
公开(公告)号：WO2005015415A2
公开(公告)日：2005-02-17
申请号：PCT/IB2004/051404
申请日：2004-08-05
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , KLEIHORST, Richard, P. , VAN DIJK, Victor, E., S. , NIEUWLAND, Andre, K.
发明人： KLEIHORST, Richard, P. , VAN DIJK, Victor, E., S. , NIEUWLAND, Andre, K.
IPC分类号： G06F13/40
CPC分类号： G06F13/4072 , Y02D10/14 , Y02D10/151
摘要： A decoder circuit, for example a dual-rail decoder, receives input signals (43) from the end of a communications bus (not shown). The parity is calculated over the data wires (D o , D 1 , D 2 , D 3 ) using exclusive OR gates (45, 47 and 49). The calculated data parity signal (51) is compared with a transmitted parity signal (53) (shown as "carry") in an exclusive OR gate (55). Rather than connecting the control signal (57) from the exclusive OR gate (55) directly to the multiplexers (590, 591, 592, 593), the control signal (57) is instead connected to a gating circuit (71). The gating circuit (71), for example a AND gate, receives the control signal (57) as a first input signal. The gating circuit (71) also receives a second input signal in the form of a gating control signal (73). The gating control signal (73) is delayed by a predetermined amount, for example corresponding to the worst case delay of the signals in the input data signals (43). Thus, the gating control signal (73) does not control the gating circuit until such time as all of the data signals are valid, ie until the last transition on the data signal (43) has occurred, thereby preventing glitches and reducing power consumption in the decoder circuit.
摘要翻译：解码器电路（例如双轨解码器）从通信总线（未示出）的末端接收输入信号（43）。使用数据线（D 0，D 1，D 2，D 3，D 3）计算奇偶性异或门（45,47和49）。所计算的数据奇偶校验信号（51）与异或门（55）中的发送奇偶校验信号（53）（显示为“进位”）进行比较。控制信号（57）不是连接来自异或门（55）的控制信号（57）到多路复用器（590,591,592,593），而是连接到选通电路（71）。选通电路（71），例如与门，接收控制信号（57）作为第一输入信号。选通电路（71）还以选通控制信号（73）的形式接收第二输入信号。选通控制信号（73）被延迟预定量，例如对应于输入数据信号（43）中的信号的最坏情况延迟。因此，选通控制信号（73）不控制选通电路，直到所有数据信号有效，即直到数据信号（43）的最后一次转换已经发生，从而防止毛刺和减少功耗解码器电路。

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