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1. 发明申请

WO2005031858A1 SELF-ALIGNED V0-CONTACT FOR CELL SIZE REDUCTION OF FERAM DEVICES 审中-公开
标题翻译：自对准的V0接触用于细胞尺寸减少FERAM器件
公开(公告)号：WO2005031858A1
公开(公告)日：2005-04-07
申请号：PCT/SG2004/000273
申请日：2004-08-31
申请人： INFINEON TECHNOLOGIES AG , LIAN, Jingyu , NAGEL, Nicolas , GERNHARDT, Stefan , BRUCHHAUS, Rainer , HILLIGER, Andreas , WELLHAUSEN, Uwe
发明人： LIAN, Jingyu , NAGEL, Nicolas , GERNHARDT, Stefan , BRUCHHAUS, Rainer , HILLIGER, Andreas , WELLHAUSEN, Uwe
IPC分类号： H01L21/8246
CPC分类号： H01L21/76897 , H01L28/55
摘要： An FeRAM (400) comprising includes a ferroelectric material (211) sandwiched between a top electrode (207) and a bottom electrode (209). A V0-contact (405) provides an electrical connection with an underlying CS-contact (223). The V0-contact is aligned using the bottom electrode. A liner layer (403) covers a sidewall of the bottom electrode and provides a stop to an etch a hole forming the V0-contact. A method is utilized to form a V0-contact in an FeRAM. An Fe capacitor of the FeRAM is encapsulated, a bottom electrode is etched, a liner layer is deposited covering a sidewall of the bottom electrode, and a hole is etched for the V0-contact until the etching is stopped by the liner layer.
摘要翻译：包括夹在顶电极（207）和底电极（209）之间的铁电材料（211）的FeRAM（400）。 V0触点（405）提供与底层CS触点（223）的电连接。使用底部电极对齐V0触点。衬垫层（403）覆盖底部电极的侧壁，并且提供对形成V0接触的孔的蚀刻的停止。一种利用FeRAM形成V0接触的方法。 FeRAM的Fe电容器被封装，蚀刻底部电极，沉积覆盖底部电极的侧壁的衬层，并且蚀刻用于V0接触的孔，直到蚀刻被衬垫层停止。

2. 发明申请

WO2005008751A1 MULTI-LAYER BARRIER ALLOWING RECOVERY ANNEAL FOR FERROELECTRIC CAPACITORS 审中-公开
标题翻译：多层障碍物允许用于电容电容器的恢复电极
公开(公告)号：WO2005008751A1
公开(公告)日：2005-01-27
申请号：PCT/SG2004/000192
申请日：2004-07-02
申请人： INFINEON TECHNOLOGIES AG , HILLIGER, Andreas , LIAN, Jingyu , NAGEL, Nicolas , BRUCHHAUS, Rainer , GERNHARDT, Stefan , WELLHAUSEN, Uwe , MOON, Bum-Ki , HORNIK, Karl
发明人： HILLIGER, Andreas , LIAN, Jingyu , NAGEL, Nicolas , BRUCHHAUS, Rainer , GERNHARDT, Stefan , WELLHAUSEN, Uwe , MOON, Bum-Ki , HORNIK, Karl
IPC分类号： H01L21/02
CPC分类号： H01G4/1245 , H01G4/33 , H01L28/57
摘要： A multi-layer barrier (115) for a ferroelectric capacitor (101) includes an outdiffusion barrier layer (115a) permeable to both hydrogen and oxygen. The outdiffusion barrier (115a) layer covers the ferroelectric (103) of the capacitor. Oxygen passes through the outdiffusion barrier layer into the ferroelectric during an oxygen anneal in order to repair damage to the ferroelectric caused during etching. The outdiffusion barrier layer reduces the decomposition of the ferroelectric by blocking molecules leaving the ferroelectric during the oxygen anneal. The multi-layer barrier also includes a hydrogen barrier layer (115b) deposited on the outdiffusion barrier layer after repair of the ferroelectric by the oxygen anneal. The hydrogen barrier layer allows the multi-layer barrier to block the passage of hydrogen into the ferroelectric during back-end processes.
摘要翻译：用于铁电电容器（101）的多层势垒（115）包括可渗透氢和氧的扩散阻挡层（115a）。扩散阻挡层（115a）层覆盖电容器的铁电体（103）。在氧退火期间，氧气通过外扩散阻挡层进入铁电体，以便修复在蚀刻期间引起的铁电体损坏。扩散阻挡层通过在氧退火期间阻挡离开铁电体的分子来减少铁电体的分解。多层阻挡层还包括通过氧退火修复铁电体之后沉积在外扩散阻挡层上的氢阻挡层（115b）。氢阻挡层允许多层屏障在后端工艺期间阻止氢气进入铁电体。

3. 发明申请

WO2005017980A1 METHODS AND APPARATUS FOR PROCESSING SEMICONDUCTOR DEVICES BY GAS ANNEALING 审中-公开
标题翻译：用于通过气体退火处理半导体器件的方法和装置
公开(公告)号：WO2005017980A1
公开(公告)日：2005-02-24
申请号：PCT/SG2004/000200
申请日：2004-07-06
申请人： INFINEON TECHNOLOGIES AG , WELLHAUSEN, Uwe
发明人： WELLHAUSEN, Uwe
IPC分类号： H01L21/00
CPC分类号： H01L21/324 , H01L21/3003 , H01L21/67109 , H01L27/11502 , H01L27/11507
摘要： An annealing apparatus comprises a first chamber and a second chamber. A wafer can be located between the chambers, with a first of its surfaces in the first chamber and a second of its surfaces in the second chamber. Different gases are fed to the two chambers, so that, during an annealing step, the components proximate the two chambers are exposed to different gaseous atmospheres. Gas can penetrate from the top and bottom chambers into the wafer, but interdiffusion is blocked by a diffusion blocker layer (e.g. Si 3 N 4 ) within the wafer (e.g. separating CMOS devices from ferrocapacitor devices). If one of the gases is active in a thermal treatment (e.g. a hydrogen-rich gas for performing a CMOS device fabrication step), then the other gas may be inert, so that certain regions of the wafer are not subjected to the treatment step.
摘要翻译：退火设备包括第一室和第二室。晶片可以位于室之间，其第一腔室中的第一表面和第二腔室中的第二表面的第二表面。不同的气体被馈送到两个室，使得在退火步骤期间，靠近两个室的部件暴露于不同的气体气氛。气体可以从顶部和底部腔室穿透进入晶片，但是相互扩散被晶片内的扩散阻挡层（例如Si 3 N 4）阻挡（例如，从CMOS电路器件分离CMOS器件）。如果其中一种气体在热处理（例如用于进行CMOS器件制造步骤的富氢气体）中是有活性的，则其它气体可以是惰性的，使得晶片的某些区域不经受处理步骤。

4. 发明申请

WO2004090949A1 SUPPRESSION OF ELECTRODE RE-CRYSTALLISATION IN A FERROCAPACITOR 审中-公开
标题翻译：抑制FERROCAPACITOR中的电极重结晶
公开(公告)号：WO2004090949A1
公开(公告)日：2004-10-21
申请号：PCT/SG2004/000086
申请日：2004-04-08
申请人： INFINEON TECHNOLOGIES AG , GERNHARDT, Stefan , LIAN, Jingyu , BRUCHHAUS, Rainer , HILLIGER, Andreas , NAGEL, Nicolas , WELLHAUSEN, Uwe
发明人： GERNHARDT, Stefan , LIAN, Jingyu , BRUCHHAUS, Rainer , HILLIGER, Andreas , NAGEL, Nicolas , WELLHAUSEN, Uwe
IPC分类号： H01L21/02
CPC分类号： H01L28/55 , H01L28/60
摘要： An electrode (1) of a ferrocapacitor formed by an etching process is treated by oxygen implantation to reduce the size of crystal domains (15) in side regions (11) of the electrode (1). Subsequently a cover layer (3) is deposited over the side wall of the electrode to protect the ferrocapacitor in subsequent process steps. Later in the fabrication process the ferrocapacitor is subject to heat treatments, but due to the reduced size of the crystal domains (15) the growth of the crystal domains in the side regions (11) of the electrode is more homogenous, and causes reduced stresses in the cover layer (3), leading to a reduced risk of the cover layer (3) failing to protect the ferrocapacitor.
摘要翻译：通过氧注入处理通过蚀刻工艺形成的二茂铁电极的电极（1），以减小电极（1）的侧面区域（11）中的晶体畴（15）的尺寸。随后，在电极的侧壁上沉积覆盖层（3），以在随后的工艺步骤中保护铁电体电容器。在制造过程中，铁电体经受热处理，但是由于晶体畴的尺寸减小（15），电极的侧面区域（11）中的晶体畴的生长更均匀，导致应力降低在覆盖层（3）中，导致覆盖层（3）不能保护铁电体的风险降低。

5. 发明申请

WO2004077438A2 PROCESS OF FORMING A FERROELECTRIC MEMORY INTEGRATED CIRCUIT 审中-公开
标题翻译：形成电磁记忆集成电路的过程
公开(公告)号：WO2004077438A2
公开(公告)日：2004-09-10
申请号：PCT/EP2004001695
申请日：2004-02-20
申请人： INFINEON TECHNOLOGIES AG , HILLIGER ANDREAS , WELLHAUSEN UWE
发明人： HILLIGER ANDREAS , WELLHAUSEN UWE
IPC分类号： G11C20060101 , G11C11/22 , H01L21/00 , H01L21/02 , H01L21/768 , H01L21/8242 , H01L21/8246 , H01L27/108 , H01L27/115 , G11C
CPC分类号： H01L28/55 , G11C11/22 , H01L21/76829 , H01L21/76831 , H01L21/76832 , H01L27/11502 , H01L28/65 , H01L28/75
摘要： A memory cell having a capacitor with top and bottom electrodes with a dielectric layer between is described. The bottom electrode is coupled to a first diffusion region of a transistor by a bottom electrode plug. A dielectric layer covers the capacitor. Above the dielectric layer is a first barrier layer. A via is created in the dielectric layer in which a plug is formed to couple to the second diffusion region. The via comprises substantially vertical sidewalls. A second barrier layer lines the sidewalls of the via. A conductive material is then deposited on the substrate, filling the via to form the plug. By providing the first and second barrier layers, the diffusion of hydrogen which can adversely impact the capacitor is reduced, thereby improving the reliability.
摘要翻译：描述了具有具有介电层之间的顶部和底部电极的电容器的存储单元。底部电极通过底部电极插塞耦合到晶体管的第一扩散区域。电介质层覆盖电容器。电介质层之上是第一阻挡层。在其中形成有插塞以耦合到第二扩散区域的电介质层中形成通孔。通孔包括基本垂直的侧壁。第二阻挡层对通孔的侧壁进行排列。然后将导电材料沉积在衬底上，填充通孔以形成插头。通过设置第一和第二阻挡层，可以减小可能不利地影响电容器的氢的扩散，从而提高可靠性。

6. 发明申请

WO2004077438A3 PROCESS OF FORMING A FERROELECTRIC MEMORY INTEGRATED CIRCUIT 审中-公开
公开(公告)号：WO2004077438A3
公开(公告)日：2004-09-10
申请号：PCT/EP2004/001695
申请日：2004-02-20
申请人： INFINEON TECHNOLOGIES AG , HILLIGER, Andreas , WELLHAUSEN, Uwe
发明人： HILLIGER, Andreas , WELLHAUSEN, Uwe
IPC分类号： H01L21/8246
摘要： A memory cell (540) having a capacitor with top (548) and bottom (546) electrodes with a dielectric layer (549) between is described. The bottom electrode (546) is coupled to a first diffusion region (538) of a transistor (542) by a bottom electrode plug (574). A dielectric layer (529) covers the capacitor. Above the dielectric layer (529) is a first barrier layer (587). A via (693) is created in the dielectric layer in which a plug is formed to couple to the second diffusion region (539). The via (693) comprises substantially vertical sidewalls. A second barrier layer (692) lines the sidewalls of the via (693). A conductive material is then deposited on the substrate, filling the via to form the plug. By providing the first and second barrier layers, the diffusion of hydrogen which can adversely impact the capacitor is reduced, thereby improving the reliability.

7. 发明申请

WO2004051743A2 RADIATION PROTECTION IN INTEGRATED CIRCUITS 审中-公开
标题翻译：集成电路中的辐射防护
公开(公告)号：WO2004051743A2
公开(公告)日：2004-06-17
申请号：PCT/EP0313411
申请日：2003-11-28
申请人： INFINEON TECHNOLOGIES AG , WELLHAUSEN UWE , NAGEL NICOLAS , BRUCHHAUS RAINER , GERNHARDT STEFAN
发明人： WELLHAUSEN UWE , NAGEL NICOLAS , BRUCHHAUS RAINER , GERNHARDT STEFAN
IPC分类号： G06F1/04 , H01L21/02 , H01L23/00 , H01L23/552 , H01L27/115 , H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L23/552 , H01L27/11502 , H01L28/57 , H01L2924/0002 , H01L2924/00
摘要： Reduced radiation damage to an IC feature is disclosed. At least a portion of the feature which is sensitive to radiation is covered by a radiation protection layer. The radiation protection layer protects the feature from being damaged to radiation during, for example, processing of the IC. In one embodiment, the radiation protection layer comprises a noble metal, oxides, alloys, or compounds thereof.
摘要翻译：公开了降低对IC特征的辐射损伤。对辐射敏感的特征的至少一部分被辐射防护层覆盖。辐射防护层在例如IC的处理期间保护特征不被辐射损坏。在一个实施例中，辐射防护层包括贵金属，氧化物，合金或其化合物。

8. 发明申请

WO2005008771A1 METHOD OF FORMING A CONTACT HOLE WITH A BARRIER LAYER IN A DEVICE AND RESULTING DEVICE 审中-公开
标题翻译：在设备和结构设备中形成具有障碍层的接触孔的方法
公开(公告)号：WO2005008771A1
公开(公告)日：2005-01-27
申请号：PCT/SG2004/000203
申请日：2004-07-06
申请人： INFINEON TECHNOLOGIES AG , HILLIGER, Andreas , GERNHARDT, Stefan , WELLHAUSEN, Uwe , HORNIK, Karl
发明人： HILLIGER, Andreas , GERNHARDT, Stefan , WELLHAUSEN, Uwe , HORNIK, Karl
IPC分类号： H01L21/8246
CPC分类号： H01L23/5226 , H01L21/76802 , H01L21/76831 , H01L27/11502 , H01L28/57 , H01L2924/0002 , H01L2924/00
摘要： A method of forming a contact to an underlayer (2) of a device includes the steps of forming a contact hole (5), forming a contact hole barrier layer (7) of a barrier material in the contact hole of the device, etching the contact hole barrier layer on the bottom surface of the contact hole, depositing a liner material (8) in the contact hole, and filling the contact hole with a conductive material (9). A device such as a semiconductor, passive device, capacitor or FeRAM is formed in accordance with the method. The portions of the contact hole barrier layer (7) on the side walls of the contact hole inhibit lateral diffusion of hydrogen and/or oxygen. The contact hole barrier layer can be performed after a wet etch process to fill voids (6) in an existing barrier layer (3) caused by that process, or prior to the wet etch process to prevent damage to the existing barrier layer.
摘要翻译：与器件的底层（2）形成接触的方法包括以下步骤：在器件的接触孔中形成接触孔（5），形成阻挡材料的接触孔阻挡层（7），蚀刻接触孔的底面上的接触孔阻挡层，在接触孔中沉积衬垫材料（8），并用导电材料（9）填充接触孔。根据该方法形成诸如半导体，无源器件，电容器或FeRAM的器件。接触孔的侧壁上的接触孔阻挡层（7）的部分抑制氢和/或氧的横向扩散。接触孔阻挡层可以在湿蚀刻工艺之后进行以填充由该工艺引起的现有阻挡层（3）中的空隙（6），或者在湿蚀刻工艺之前，以防止对现有阻挡层的损坏。

9. 发明申请

WO2004051743A3 RADIATION PROTECTION IN INTEGRATED CIRCUITS 审中-公开
公开(公告)号：WO2004051743A3
公开(公告)日：2004-06-17
申请号：PCT/EP2003/013411
申请日：2003-11-28
申请人： INFINEON TECHNOLOGIES AG , WELLHAUSEN, Uwe , NAGEL, Nicolas , BRUCHHAUS, Rainer , GERNHARDT, Stefan
发明人： WELLHAUSEN, Uwe , NAGEL, Nicolas , BRUCHHAUS, Rainer , GERNHARDT, Stefan
IPC分类号： H01L23/552
摘要： Reduced radiation damage to an IC feature such as a ferroelectric capacitor is disclosed. At least a portion of the feature which is sensitive to radiation is covered by a radiation protection layer. The radiation protection layer protects the feature from being damaged to radiation during, for example, processing of the IC. In one embodiment, the radiation protection layer comprises a noble metal, oxides, alloys, or compounds thereof.

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