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1. 发明申请

WO2006061318A1 INTEGRATED CIRCUIT DIELECTRIC HAVING ORIENTED CYLINDRICAL VOIDS 审中-公开
标题翻译：集成电路具有面向圆柱形电极的集成电路
公开(公告)号：WO2006061318A1
公开(公告)日：2006-06-15
申请号：PCT/EP2005/056117
申请日：2005-11-21
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , IBM UNITED KINGDOM LIMITED , FURUKAWA, Toshiharu , HAKEY, Mark, Charles , HOLMES, Steven, John , HORAK, David, Vaclav , KOBURGER, III, Charles, William , MITCHELL, Peter
发明人： FURUKAWA, Toshiharu , HAKEY, Mark, Charles , HOLMES, Steven, John , HORAK, David, Vaclav , KOBURGER, III, Charles, William , MITCHELL, Peter
IPC分类号： H01L21/768 , H01L23/522
CPC分类号： B82Y10/00 , H01L21/7682 , H01L23/5222 , H01L23/53238 , H01L23/5329 , H01L2924/0002 , Y10S977/742 , Y10S977/842 , H01L2924/00
摘要： A dielectric in an integrated circuit is formed by creating oriented cylindrical voids in a conventional dielectric material. Preferably, voids are formed by first forming multiple relatively long, thin carbon nanotubes perpendicular to a surface of an integrated circuit wafer, by depositing a conventional dielectric on the surface to fill the area between the carbon nanotubes, and by then removing the carbon nanotubes to produce voids in place of the carbon nanotubes. A layer of dielectric and voids thus formed can be patterned or otherwise processed using any of various conventional processes. The use of a conventional dielectric material having numerous air voids substantially reduces the dielectric constant, leaving a dielectric structure which is both structurally strong and can be constructed compatibly with conventional processes and materials.
摘要翻译：集成电路中的电介质通过在常规电介质材料中产生取向的圆柱形空隙来形成。优选地，通过首先通过在表面上沉积常规电介质以填充碳纳米管之间的区域，然后通过将碳纳米管去除以形成多个相对较长的薄碳纳米管，形成集成电路晶片的表面，形成空隙产生代替碳纳米管的空隙。可以使用各种常规方法中的任何一种来形成如此形成的电介质层和空隙层。使用具有多个空气空隙的常规电介质材料基本上降低了介电常数，留下了在结构上很强并且可以与常规工艺和材料相容地构造的电介质结构。

2. 发明申请

WO2006010684A1 INTEGRATED CIRCUIT CHIP UTILIZING ORIENTED CARBON NANOTUBE CONDUCTIVE LAYERS 审中-公开
标题翻译：集成电路芯片利用面向碳纳米管的导电层
公开(公告)号：WO2006010684A1
公开(公告)日：2006-02-02
申请号：PCT/EP2005/053002
申请日：2005-06-27
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , IBM UNITED KINGDOM LIMITED , FURUKAWA, Toshiharu , HAKEY, Mark, Charles , HOLMES, Steven, John , HORAK, David, Vaclav , KOBURGER, III, Charles, William , MITCHELL, Peter
发明人： FURUKAWA, Toshiharu , HAKEY, Mark, Charles , HOLMES, Steven, John , HORAK, David, Vaclav , KOBURGER, III, Charles, William , MITCHELL, Peter
IPC分类号： H01L51/30
CPC分类号： H01L21/7685 , B82Y10/00 , H01L21/32051 , H01L21/76838 , H01L21/76876 , H01L21/76877 , H01L23/53276 , H01L51/0048 , H01L51/0052 , H01L2221/1094 , H01L2924/0002 , Y10S977/742 , Y10S977/762 , Y10S977/778 , Y10S977/842 , H01L2924/00
摘要： A conductive layer in an integrated circuit is formed as a sandwich having multiple sublayers, including at least one sublayer of oriented carbon nanotubes. The conductive layer sandwich preferably contains two sublayers of carbon nanotubes, in which the carbon nanotube orientation in one sublayer is substantially perpendicular to that of the other layer. The conductive layer sandwich preferably contains one or more additional sublayers of a conductive material, such as a metal. In one embodiment, oriented carbon nanotubes are created by forming a series of parallel surface ridges, covering the top and one side of the ridges with a catalyst inhibitor, and growing carbon nanotubes horizontally from the uncovered vertical sides of the ridges. In another embodiment, oriented carbon nanotubes are grown on the surface of a conductive material in the presence of a directional flow of reactant gases and a catalyst.
摘要翻译：集成电路中的导电层形成为具有多个子层的夹层，包括至少一个定向碳纳米管子层。导电层夹层优选包含两个碳纳米管子层，其中一个子层中的碳纳米管取向基本上垂直于另一层的碳纳米管取向。导电层夹层优选地包含一种或多种另外的导电材料的子层，例如金属。在一个实施方案中，通过形成一系列平行的表面脊，通过用催化剂抑制剂覆盖脊的顶部和一侧并从脊的未覆盖的垂直侧水平生长碳纳米管来产生定向碳纳米管。在另一个实施方案中，定向碳纳米管在反应物气体和催化剂的定向流的存在下在导电材料的表面上生长。

3. 发明申请

WO2005083776A1 INTEGRATED CIRCUIT CHIPS UTILIZING CARBON NANOTUBE COMPOSITE INTERCONNECTION VIAS 审中-公开
标题翻译：使用碳纳米管复合互连VIAS的集成电路板
公开(公告)号：WO2005083776A1
公开(公告)日：2005-09-09
申请号：PCT/EP2005/050764
申请日：2005-02-23
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , IBM UNITED KINGDOM LIMITED , FURUKAWA, Toshiharu , HAKEY, Mark, Charles , HORAK, David, Vaclav , KOBURGER III, Charles, William , MASTERS, Mark, Eliot , MITCHELL, Peter , POLONSKY, Stanislav
发明人： FURUKAWA, Toshiharu , HAKEY, Mark, Charles , HORAK, David, Vaclav , KOBURGER III, Charles, William , MASTERS, Mark, Eliot , MITCHELL, Peter , POLONSKY, Stanislav
IPC分类号： H01L21/768
CPC分类号： B82Y10/00 , H01L21/28562 , H01L21/76877 , H01L23/5226 , H01L2221/1094 , H01L2924/0002 , Y10S977/742 , Y10S977/842 , H01L2924/00
摘要： Conductive paths in an integrated circuit are formed using multiple undifferentiated carbon nanotubes embedded in a conductive metal, which is preferably copper. Preferably, conductive paths include vias running between conductive layers. Preferably, composite vias are formed by forming a metal catalyst pad on a conductor at the via site, depositing and etching a dielectric layer to form a cavity, growing substantially parallel carbon nanotubes on the catalyst in the cavity, and filling the remaining voids in the cavity with copper. The next conductive layer is then formed over the via hole.
摘要翻译：集成电路中的导电路径使用嵌入导电金属中的多个未分化碳纳米管形成，优选为铜。优选地，导电路径包括在导电层之间运行的通孔。优选地，通过在通孔位置的导体上形成金属催化剂垫，沉积和蚀刻介电层以形成空腔，在空腔中的催化剂上基本上平行地生长碳纳米管，并填充其中的剩余空隙来形成复合通孔有铜的腔。然后在通孔上形成下一导电层。

4. 发明申请

WO2005078819A1 METHODS OF FABRICATING VERTICAL CARBON NANOTUBE FIELD EFFECT TRANSISTORS FOR ARRANGEMENT IN ARRAYS AND FIELD EFFECT TRANSISTORS AND ARRAYS FORMED THEREBY 审中-公开
标题翻译：制造垂直碳纳米管场效应晶体管的方法，用于阵列中的布置和场效应晶体管及其形成的阵列
公开(公告)号：WO2005078819A1
公开(公告)日：2005-08-25
申请号：PCT/EP2005/050591
申请日：2005-02-10
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , IBM UNITED KINGDOM LIMITED , FURUKAWA, Toshiharu , HAKEY, Mark, Charles , HOLMES, Steven, John , HORAK, David, Vaclav , KOBURGER, Charles, William, III , MITCHELL, Peter , NESBIT, Larry, Alan
发明人： FURUKAWA, Toshiharu , HAKEY, Mark, Charles , HOLMES, Steven, John , HORAK, David, Vaclav , KOBURGER, Charles, William, III , MITCHELL, Peter , NESBIT, Larry, Alan
IPC分类号： H01L51/20
CPC分类号： H01L51/057 , B82Y10/00 , G11C13/025 , H01L29/0665 , H01L29/0673 , H01L29/0676 , H01L29/125 , H01L29/66409 , H01L29/772 , H01L51/0048 , Y10S977/734
摘要： A method for forming carbon nanotube field effect transistors, arrays of carbon nanotube field effect transistors, and device structures and arrays of device structures formed by the methods. The methods include forming a stacked structure including a gate electrode layer and catalyst pads each coupled electrically with a source/drain contact. The gate electrode layer is divided into multiple gate electrodes and at least one semiconducting carbon nanotube is synthesized by a chemical vapor deposition process on each of the catalyst pads. The completed device structure includes a gate electrode with a sidewall covered by a gate dielectric and at least one semiconducting carbon nanotube adjacent to the sidewall of the gate electrode. Source/drain contacts are electrically coupled with opposite ends of the semiconducting carbon nanotube to complete the device structure. Multiple device structures may be configured either as a memory circuit or as a logic circuit.
摘要翻译：一种形成碳纳米管场效应晶体管的方法，碳纳米管场效应晶体管的阵列，以及通过该方法形成的器件结构和器件结构阵列。所述方法包括形成包括栅极电极层和各个与源极/漏极接触电连接的催化剂焊盘的堆叠结构。栅电极层被分成多个栅极电极，并且通过化学气相沉积工艺在每个催化剂焊盘上合成至少一个半导体碳纳米管。完成的器件结构包括具有由栅极电介质覆盖的侧壁的栅电极和与栅电极的侧壁相邻的至少一个半导体碳纳米管。源极/漏极触点与半导体碳纳米管的相对端电耦合以完成器件结构。多个器件结构可以被配置为存储器电路或逻辑电路。

5. 发明申请

WO2005076382A1 VERTICAL FIELD EFFECT TRANSISTORS INCORPORATING SEMICONDUCTING NANOTUBES GROWN IN A SPACER-DEFINED PASSAGE 审中-公开
标题翻译：包含半导体纳米管的垂直场效应晶体管
公开(公告)号：WO2005076382A1
公开(公告)日：2005-08-18
申请号：PCT/EP2005/050128
申请日：2005-01-13
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , IBM UNITED KINGDOM LIMITED , FURUKAWA, Toshiharu , HAKEY, Mark, Charles , HOLMES, Steven, John , HORAK, David, Vaclav , MITCHELL, Peter , NESBIT, Larry, Alan
发明人： FURUKAWA, Toshiharu , HAKEY, Mark, Charles , HOLMES, Steven, John , HORAK, David, Vaclav , MITCHELL, Peter , NESBIT, Larry, Alan
IPC分类号： H01L51/30
CPC分类号： H01L27/283 , B82Y10/00 , H01L51/0048 , H01L51/057 , Y10S977/70 , Y10S977/707 , Y10S977/721 , Y10S977/724
摘要： Vertical field effect transistors having a channel region defined by at least one semiconducting nanotube and methods for fabricating such vertical field effect transistors by chemical vapor deposition using a spacer-defined channel. Each nanotube is grown by chemical vapor deposition catalyzed by a catalyst pad positioned at the base of a high-aspect-ratio passage defined between a spacer and a gate electrode. Each nanotube grows in the passage with a vertical orientation constrained by the confining presence of the spacer. A gap may be provided in the base of the spacer remote from the mouth of the passage. Reactants flowing through the gap to the catalyst pad participate in nanotube growth.
摘要翻译：具有由至少一个半导体纳米管限定的沟道区的垂直场效应晶体管以及通过使用间隔物定义的沟道的化学气相沉积来制造这种垂直场效应晶体管的方法。每个纳米管通过化学气相沉积来生长，该催化剂垫位于位于间隔物和栅电极之间限定的高纵横比通道的基部处的催化剂垫。每个纳米管在通道中生长，其中垂直取向受限于间隔物的限制。可以在远离通道的口的间隔件的基部中设置间隙。通过间隙流过催化剂垫的反应物参与纳米管生长。

6. 发明申请

WO2004105121A1 METHOD FOR MANUFACTURING A MULTI-LEVEL INTERCONNECT STRUCTURE 审中-公开
标题翻译：制造多层互连结构的方法
公开(公告)号：WO2004105121A1
公开(公告)日：2004-12-02
申请号：PCT/GB2004/001933
申请日：2004-05-04
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , IBM UNITED KINGDOM LIMITED , HORAK, David, Vaclav , KOBURGER, Charles, William , MITCHELL, Peter , NESBIT, Larry, Alan
发明人： HORAK, David, Vaclav , KOBURGER, Charles, William , MITCHELL, Peter , NESBIT, Larry, Alan
IPC分类号： H01L21/768
CPC分类号： H01L21/76831 , H01L21/7682 , H01L2924/0002 , H01L2924/00
摘要： A method for forming interlevel dielectric layers in multilevel interconnect structures using air as the constituent low-k dielectric material that is compatible with damascene processes without introducing additional process steps. The conductive features characteristic of the damascene process are formed by standard lithographic and etch processes in the sacrificial mandrel material (22,30) for each level of the interconnect structure. The conductive features (28',32',34') in each level are surrounded by the mandrel material. After all levels of the interconnect structure are formed, a passageway (62) is provided to the mandrel material. An isotropic etchant is introduced through the passageway that selectively etches and removes the mandrel material. The spaces formerly occupied by the mandrel material in the levels of the interconnect structure are filled by air, which operates as a low-k dielectric material.
摘要翻译：一种用于在多层互连结构中形成层间电介质层的方法，其使用空气作为组成的低k介电材料，其与镶嵌工艺兼容，而不引入额外的工艺步骤。镶嵌工艺的特征的导电特征是通过用于互连结构的每个级别的牺牲心轴材料（22,30）中的标准光刻和蚀刻工艺形成的。每个级别的导电特征（28'，32'，34'）被心轴材料包围。在所有级别的互连结构形成之后，向心轴材料提供通道（62）。通过选择性蚀刻和去除心轴材料的通道引入各向同性蚀刻剂。先前由芯棒材料在互连结构的水平上占据的空间由空气填充，空气作为低k电介质材料工作。

7. 发明申请

WO2012138847A2 SYSTEM AND METHOD FOR PROVIDING VEHICLE AND FLEET PROFILES AND PRESENTATIONS OF TRENDS 审中-公开
标题翻译：提供车辆和配置文件的系统和方法和趋势展示
公开(公告)号：WO2012138847A2
公开(公告)日：2012-10-11
申请号：PCT/US2012/032305
申请日：2012-04-05
申请人： MITCHELL, Peter , FLEETMATICS IRL LIMITED
发明人： MITCHELL, Peter
IPC分类号： G08G1/123
CPC分类号： G08G1/127 , G06Q10/0639 , G07C5/008 , G08G1/0104 , G08G1/20
摘要： A computer system and products and methods therefor including at least one computer processor and computer readable storage medium or media including computer code and at least one storage device in which is stored GPS data for a plurality of vehicles the system comprising: a memory including GPS event database including GPS event data transmitted from a plurality of GPS devices, each GPS device associated with a vehicle, and stored over a period of time; and the one or more processors programmed at least to: receive GPS event data transmitted from a plurality of GPS devices, each GPS device associated with a vehicle; for each vehicle, store in GPS event database operatively coupled to at least one of the processors, the GPS event data; analyze the GPS event data to derive a plurality of operational metrics for each of a plurality of vehicles; identify, from the analysis, at least one trend for a GPS event history using the GPS event data; and provide, for a graphic user interface, a representation including a representation of the at least one trend.
摘要翻译：一种计算机系统及其产品和方法，包括至少一个计算机处理器和包括计算机代码的计算机可读存储介质或介质，以及至少一个存储设备，其中存储用于多个车辆的GPS数据，该系统包括：包括GPS事件的存储器数据库，其包括从多个GPS装置发送的GPS事件数据，与车辆相关联的每个GPS装置，并在一段时间内存储; 并且所述一个或多个处理器至少编程为：接收从多个GPS设备发送的GPS事件数据，与车辆相关联的每个GPS设备; 对于每个车辆，存储在可操作地耦合到至少一个处理器的GPS事件数据库中，GPS事件数据; 分析GPS事件数据以导出多个车辆中的每一个的多个操作度量; 从分析中识别使用GPS事件数据的GPS事件历史的至少一个趋势; 并且为图形用户界面提供包括所述至少一个趋势的表示的表示。

8. 发明申请

WO2007129287A1 A VEHICLE TRACKING SYSTEM 审中-公开
标题翻译：车辆跟踪系统
公开(公告)号：WO2007129287A1
公开(公告)日：2007-11-15
申请号：PCT/IE2006/000052
申请日：2006-05-09
申请人： FLEETMATICS PATENTS LIMITED , MITCHELL, Peter , DOLGOPOLOV, Andrei , WALSH, Paul , GOGGIN, John
发明人： MITCHELL, Peter , DOLGOPOLOV, Andrei , WALSH, Paul , GOGGIN, John
IPC分类号： H04Q7/22 , G07C5/00
CPC分类号： H04L67/125 , G08G1/123 , H04L67/18 , H04W4/02
摘要： A vehicle tracking system central host (5, 6) comprises a memory cache processor for managing a plurality of memory caches (35) and a storage device (6) linked with the memory cache processor, for receiving messages from the memory caches and writing them to a database. There are n receiver ports (PORTi) each for receiving message packets of an associated protocol from remote vehicle on-board tracker units. There are also n receiver processors (PROCi), each associated with a port and each receiver processor being for: reading message packets received at the associated port, performing initial processing of the message packets including adding headers to provide processed messages, and writing the processed messages to a log dedicated to the receiver processor. There re also n decoders (DECi), each associated with a receiver processor log (LOGi) and being for (a) instantiating (56) a service object for each log, (b) executing each service object to instantiate (59) a message object in which data from a current message is written as attributes of the message object such that instantiation of the message object normalizes the message and the normalized fields include a vehicle identifier field, and (c) executing each service object to repeat step (b) for each successive message in the associated log, and (d) executing the service object to write each message object to one of said memory caches. The ports, the receiver processors, and the decoders operate in parallel.
摘要翻译：车辆跟踪系统中央主机（5,6）包括用于管理多个存储器高速缓冲存储器（35）的存储器高速缓存处理器和与存储器高速缓冲存储器处理器连接的存储设备（6），用于从存储器高速缓存接收消息并写入它们到一个数据库。有n个接收端口（PORTi），用于从远程车载车载跟踪单元接收相关协议的消息包。还有n个接收器处理器（PROCi），每个接收器处理器（每个与一个端口相关联），每个接收器处理器用于：读取在相关端口处接收的消息分组，执行消息分组的初始处理，包括添加报头以提供经处理的消息，消息发送到专用于接收器处理器的日志。还有n个解码器（DECi），每个解码器（DECi）与接收器处理器日志（LOGi）相关联，并且用于（a）为每个日志实例化（56）服务对象，（b）执行每个服务对象以实例化（59）消息将来自当前消息的数据写入消息对象的属性的对象，使得消息对象的实例化使消息标准化，并且归一化字段包括车辆标识符字段，以及（c）执行每个服务对象以重复步骤（b）对于相关日志中的每个连续消息，以及（d）执行服务对象以将每个消息对象写入到所述存储器高速缓存之一。端口，接收器处理器和解码器并行运行。

9. 发明申请

WO2012138837A1 SYSTEM AND METHOD FOR PROVIDING AN ELECTRONIC REPRESENTATION OF A ROUTE 审中-公开
标题翻译：用于提供路由的电子表示的系统和方法
公开(公告)号：WO2012138837A1
公开(公告)日：2012-10-11
申请号：PCT/US2012/032283
申请日：2012-04-05
申请人： FLEETMATICS IRL LIMITED , MITCHELL, Peter
发明人： MITCHELL, Peter
IPC分类号： G01C21/36
CPC分类号： G01C21/3647 , G08G1/202
摘要： Disclosed is a computer systems, methods and computer program products for providing an electronic representation of a route. A display device displays a plurality of sequential displays of the ground level area representations along the recorded route including: a first display comprising an origin location area representation; a plurality of sequential displays comprising sequential location area representations along the route; and a last display of a destination location area representation. The at least one ground level image can be a photographic image. A record of a route is recorded by a GPS device.
摘要翻译：公开了一种用于提供路线的电子表示的计算机系统，方法和计算机程序产品。显示装置沿着所记录的路线显示地平面区域表示的多个顺序显示，包括：第一显示器，其包括原点位置区域表示; 多个顺序显示器，包括沿路线的顺序位置区域表示; 以及目的地位置区域表示的最后显示。所述至少一个地平面图像可以是摄影图像。路由的记录由GPS设备记录。

10. 发明申请

WO2004078297A1 MULTIPLE GAME GAMING MACHINE 审中-公开
标题翻译：多玩游戏机
公开(公告)号：WO2004078297A1
公开(公告)日：2004-09-16
申请号：PCT/AU2004/000260
申请日：2004-03-01
申请人： ARISTOCRAT TECHNOLOGIES AUSTRALIA PTY LTD , MITCHELL, Peter , CORMACK, William, George , CHIM, Chi, We
发明人： MITCHELL, Peter , CORMACK, William, George , CHIM, Chi, We
IPC分类号： A63F13/10
CPC分类号： G07F17/3213 , G07F17/32 , G07F17/3258 , G07F17/3262 , G07F17/3267 , G07F17/34
摘要： A gaming machine comprises a display and a game controller arranged to control images of symbols displayed on the display. The game controller is arranged to play a game wherein at least one random event is caused to be displayed on the display and, if a predefined winning event occurs, a prize is awarded. A plurality of sub-games constitute the game displayed on the display. As an initial display, fewer than a full set of images of each of the sub-games are displayed to show a partial outcome of the game, the fewer than the full set of images being representative of a determination of an expected value for each of the sub-games.
摘要翻译：游戏机包括显示器和布置成控制显示在显示器上的符号图像的游戏控制器。游戏控制器被布置为玩游戏，其中至少一个随机事件被显示在显示器上，并且如果发生预定义的胜利事件，则奖励奖品。多个子游戏构成在显示器上显示的游戏。作为初始显示，显示每个子游戏的少于一整组图像以显示游戏的部分结果，少于全部图像的代表每个图像的期望值的确定子游戏。

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