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    • 1. 发明申请
    • OBJECT-CODE COMPATIBLE REPRESENTATION OF VERY LONG INSTRUCTION WORD PROGRAMS
    • 对象代码兼容非常长的指令性词汇程序
    • WO1996029645A1
    • 1996-09-26
    • PCT/EP1996001208
    • 1996-03-20
    • INTERNATIONAL BUSINESS MACHINES CORPORATIONIBM DEUTSCHLAND GMBH
    • INTERNATIONAL BUSINESS MACHINES CORPORATIONIBM DEUTSCHLAND GMBHMORENO, Jaime, Humberto
    • G06F09/38
    • G06F9/30061G06F8/445G06F9/3842G06F9/3853G06F9/3885
    • Object-code compatibility is provided among VLIW processors with different organizations. The object-code can also be executed by sequential processors, thus providing compatibility with scalar and superscalar processors. A mechanism is provided which allows representing VLIW programs in an implementation-independent manner. This mechanism relies on instruction cache (I-cache) reload/access logic which incorporates implementation-dependent features into a VLIW program. In this way, programs are represented in main memory in an implementation-independent manner (i.e., without reflecting the organization of the processor where they are executed). Tree-instructions have been proposed as a suitable mechanism to express instruction-level parallelism in computer systems, and achieve object-code compatibility among processor implementations with varying parallel capabilities, but the execution of arbitrary tree-instructions remains an unsolved problem. This invention provides a mechanism and an apparatus for the interpretation of tree-instructions by a computer system based on a VLIW processor. The invention provides formats for representing tree-instructions at different levels within the systems, apparatus for converting among these formats, and apparatus for decoding and executing the multiway branches in tree-instructions.
    • VLIW处理器与不同组织提供对象代码兼容性。 目标代码也可以由顺序处理器执行,从而提供与标量和超标量处理器的兼容性。 提供了一种允许以独立于实现方式表示VLIW程序的机制。 该机制依赖于将实现相关功能集成到VLIW程序中的指令高速缓存(I-cache)重载/访问逻辑。 以这种方式,程序以实现无关的方式在主存储器中表示(即,不反映处理器在哪里被执行的组织)。 已经提出了树指令作为在计算机系统中表达指令级并行性的适当机制,并且在具有不同并行能力的处理器实现之间实现对象代码兼容性,但是任意树指令的执行仍然是未解决的问题。 本发明提供了一种用于通过基于VLIW处理器的计算机系统来解释树指令的机制和装置。 本发明提供了用于表示系统内的不同级别的树指令的格式,用于在这些格式之间转换的装置,以及用于在树指令中解码和执行多路分支的装置。
    • 6. 发明申请
    • METHOD AND SYSTEM FOR CREATING AND MAINTAINING MULTIPLE DOCUMENT VERSIONS IN A DATA PROCESSING SYSTEM LIBRARY
    • 在数据处理系统库中创建和维护多个文档版本的方法和系统
    • WO1993012498A1
    • 1993-06-24
    • PCT/EP1992002682
    • 1992-11-21
    • IBM DEUTSCHLAND GMBHINTERNATIONAL BUSINESS MACHINES CORPORATION
    • IBM DEUTSCHLAND GMBHINTERNATIONAL BUSINESS MACHINES CORPORATIONHOWELL, William, EdwardREDDY, Hari, NukalapatiWANG, Diana, S.
    • G06F15/403
    • G06F17/30011Y10S707/99954
    • A method and system for creating and maintaining multiple document versions in a data processing system implemented library. Selected documents within a data processing system implemented library are uniquely identified as root documents and a version-root identifier for each successor version of a particular root document is established. Thereafter, a selected version-root identifier is automatically associated with each created successor version of a root document. Upon the creation of a successor version of a root document and a second predecessor document, the version-root identifier associated with the root document is automatically associated with the successor version and the second predecessor document. Upon the creation of a successor version base upon multiple non-root predecessor documents a particular non-root predecessor document is automatically selected as a root document and a version-root identifier is established and associated therewith. Thereafter, the newly established version-root identifier is automatically associated with all non-root predecessor documents and the successor version based thereon.
    • 一种用于在数据处理系统实现的库中创建和维护多个文档版本的方法和系统。 数据处理系统实现的库中的所选文档被唯一标识为根文档,并且建立了特定根文档的每个后续版本的版本根标识符。 此后,所选择的版本根标识符将自动与每个创建的根文档的后继版本相关联。 在创建根文档和第二前身文档的后继版本时,与根文档相关联的版本根标识符与后继版本和第二前身文档自动关联。 在基于多个非根前身文档创建后继版本后,将自动选择特定的非根前身文档作为根文档,并且建立版本根标识符并与之相关联。 此后,新建立的版本根标识符基于此自动地与所有非根前身文档和后继版本相关联。
    • 7. 发明申请
    • MULTI-MEDIA SIGNAL PROCESSOR COMPUTER SYSTEM
    • 多媒体信号处理器计算机系统
    • WO1993006553A1
    • 1993-04-01
    • PCT/EP1992001965
    • 1992-08-26
    • IBM DEUTSCHLAND GMBHINTERNATIONAL BUSINESS MACHINES CORPORATION
    • IBM DEUTSCHLAND GMBHINTERNATIONAL BUSINESS MACHINES CORPORATIONCARMON, Donald, EdwardCROUSE, William, GeorgeWARE, Malcolm, Scott
    • G06F13/28
    • G06F17/10G06F9/505G06F13/28G06F2209/509
    • A multi-media user task (host) computer is interfaced to a high speed digital signal processor DSP which provides support functions to the host computer via an interprocessor DMA bus master and controller. Support of multiple dynamic hard real-time signal processing task requirements are met by posting signal processor support task requests from the host processor through the interprocessor DMA controller to the signal processor and its operating system. The signal processor builds data transfer packet request execution lists in a partitioned queue in its own memory and executes internal signal processor tasks invoked by users at the host system by extracting signal sample data from incoming data packets presented by the interprocessor DMA controller in response to its execution of the DMA packet transfer request queues built by the signal processor in the partitioned queue. Processed signal values etc. are extracted from signal processor memory by the DMA interprocessor controller executing the partitioned packet request lists and delivered to the host processor. A very large number of packet transfers in support of numerous user tasks and implementing a very large number of DMA channels is thus made possible while avoiding the need for arbitration between the channels on the part of the signal processor or the host processor.
    • 多媒体用户任务(主机)计算机与高速数字信号处理器DSP接口,高速数字信号处理器DSP通过处理器DMA总线主控制器向主机提供支持功能。 支持多个动态硬实时信号处理任务要求通过将信号处理器支持的任务请求从主处理器通过处理器DMA控制器发送到信号处理器及其操作系统来满足。 信号处理器在其自己的存储器中的分区队列中构建数据传输分组请求执行列表,并且通过从处理器DMA控制器响应于其的传入数据分组提取信号样本数据来执行由主机系统用户调用的内部信号处理器任务 由分区队列中的信号处理器构建的DMA数据包传输请求队列的执行。 处理的信号值等由DMA处理器控制器从信号处理器存储器中执行分配的分组请求列表并被递送到主机处理器。 因此,可以避免对信号处理器或主机处理器的信道之间的仲裁的需要,从而可以实现支持大量用户任务和实现非常大数量的DMA信道的大量数据包传输。
    • 10. 发明申请
    • CODING FOR INFRARED SIGNALS
    • 红外信号编码
    • WO1996012364A1
    • 1996-04-25
    • PCT/EP1995003633
    • 1995-09-15
    • INTERNATIONAL BUSINESS MACHINES CORPORATIONIBM DEUTSCHLAND GMBH
    • INTERNATIONAL BUSINESS MACHINES CORPORATIONIBM DEUTSCHLAND GMBHBALASUBRAMANIAN, Peruvemba, SwaminathLEE, Nathan, JunsupLEKUCH, Scott, Douglas
    • H04L25/49
    • H04L25/49
    • A modulation scheme and system, compatible with both the asynchronous IRDA mode and the synchronous mode of IR communication, involves Non-Return-to-Zero-Inverted (NRZI) and Flash pulse encoding in conjunction with zero-bit stuffing. A digital data stream has a zero-bit inserted therein, before NRZI format encoding, whenever five consecutive one's are detected in the stream to enable the controller to distinguish the data from flags, which are exempt from the zero-bit insertion, and to provide enough transitions in the data so that the demodulator's digital phase lock loop can stay locked independent of the data contents. A Flash pulse (of from 3/16 to 8/16 of bit cell width, depending on the data rate) is generated whenever a transition is detected in the NRZI formatted data. The result, in keeping with IRDA modulation, is that a Flash pulse is generated whenever a zero occurs in the data stream. On the demodulation side, whenever a Flash pulse is received, the level of the receive line is toggled resulting in an output in NRZI format. Using this modulation scheme with a serial controller which supports NRZI and bit-stuffing, a system may be constructed that uses the controller's phase lock loop to send and receive data synchronously, since by ensuring that a zero will be received at least once every seven bits, and using NRZI to feed the phase lock loop, the receiver is able to remain in phase with the data being received and the DC component is effectively removed.
    • 与异步IRDA模式和IR通信的同步模式兼容的调制方案和系统涉及非归零(NRZI)和闪存脉冲编码以及零位填充。 每当在流中检测到五个连续的数据时,数字数据流在NRZI格式编码之前插入零比特,使得控制器能够区分数据与不被零比特插入的标志,并提供 数据中有足够的转换,使得解调器的数字锁相环可以独立于数据内容保持锁定。 每当在NRZI格式化的数据中检测到转换时,产生闪烁脉冲(根据数据速率从3/16到8/16位元组宽度)。 结果,与IRDA调制一致,是在数据流中出现零时产生闪存脉冲。 在解调侧,无论何时接收到闪光脉冲,接收线的电平都会被切换,导致NRZI格式的输出。 使用这种调制方案与支持NRZI和位填充的串行控制器,可以构造一个使用控制器的锁相环同步发送和接收数据的系统,因为通过确保每七位至少接收一次零 ,并且使用NRZI馈送锁相环,接收机能够保持与所接收的数据同相,并且DC分量被有效地去除。