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1. 发明申请

WO2012087583A2 MECHANISM FOR CONFLICT DETECTION USING SIMD 审中-公开
标题翻译：使用SIMD进行冲突检测的机制
公开(公告)号：WO2012087583A2
公开(公告)日：2012-06-28
申请号：PCT/US2011/063836
申请日：2011-12-07
申请人： INTEL CORPORATION , SMELYANSKIY, Mikhail , CHEN, Yen-Kuang , KIM, Daehyun , HUGHES, Christopher J. , LEE, Victor W.
发明人： SMELYANSKIY, Mikhail , CHEN, Yen-Kuang , KIM, Daehyun , HUGHES, Christopher J. , LEE, Victor W.
IPC分类号： G06F13/16 , G06F15/80
CPC分类号： G06F9/3887 , G06F9/30018 , G06F9/30032 , G06F9/30036 , G06F9/345
摘要： A system and method are configured to detect conflicts when converting scalar processes to parallel processes ("SIMDifying"). Conflicts may be detected for an unordered single index, an ordered single index and/or ordered pairs of indices. Conflicts may be further detected for read-after-write dependencies. Conflict detection is configured to identify operations (i.e., iterations) in a sequence of iterations that may not be done in parallel.
摘要翻译：系统和方法被配置为在将标量进程转换为并行进程（“SIMD化”）时检测冲突。可以针对无序单个索引，有序单个索引和/或有序索引对检测到冲突。写入后读取依赖关系可能会进一步检测到冲突。冲突检测被配置为识别可能不能并行完成的迭代序列中的操作（即迭代）。

2. 发明申请

WO2013147869A1 APPARATUS AND METHOD FOR SELECTING ELEMENTS OF A VECTOR COUMPUTATION 审中-公开
标题翻译：选择矢量图选择元素的装置和方法
公开(公告)号：WO2013147869A1
公开(公告)日：2013-10-03
申请号：PCT/US2012/031596
申请日：2012-03-30
申请人： INTEL CORPORATION , LEE, Victor W. , BHARADWAJ, Jayashankar , KIM, Daehyun , VASUDEVAN, Nalini , NGAI, Tin-Fook , HARTONO, Albert , BAGHSORKHI, Sara
发明人： LEE, Victor W. , BHARADWAJ, Jayashankar , KIM, Daehyun , VASUDEVAN, Nalini , NGAI, Tin-Fook , HARTONO, Albert , BAGHSORKHI, Sara
IPC分类号： G06F1/00 , G06F9/06 , G06F9/302
CPC分类号： G06F7/548 , G06F9/3001 , G06F9/30018 , G06F9/30036 , G06F9/30145 , G06F9/3877 , G06F9/3895
摘要： An apparatus and method are described for performing a vector reduction. For example, an apparatus according to one embodiment comprises: a reduction logic tree comprised of a set of N- l reduction logic blocks used to perform reduction in a single operation cycle for N vector elements; a first input vector register storing a first input vector communicatively Coupled to the set of reduction logic blocks; a second input vector register storing a second input vector communicatively coupled to the set of reduction logic blocks; a mask register storing a mask value controlling a set of one or more multiplexers, each of the set of multiplexers selecting a value directly from the first input vector register or an output containing a processed value from one of the reduction logic blocks; and an output vector register coupled to outputs of the one or more multiplexers to receive values output passed through by each of the multiplexers responsive to the control signals.
摘要翻译：描述了用于执行向量减少的装置和方法。例如，根据一个实施例的装置包括：还原逻辑树，包括用于对N个向量元素执行单个操作周期的减少的一组N-1个减少逻辑块; 第一输入向量寄存器，其以通信方式存储耦合到所述一组还原逻辑块的第一输入向量; 存储通信地耦合到所述一组减少逻辑块的第二输入向量的第二输入向量寄存器; 屏蔽寄存器，其存储控制一个或多个多路复用器的集合的掩码值，所述多路复用器集合中的每一个直接从所述第一输入向量寄存器选择值，或者包含来自所述还原逻辑块之一的处理值的输出; 以及耦合到所述一个或多个多路复用器的输出的输出矢量寄存器，以响应于所述控制信号接收由所述多路复用器中的每一个通过的值。

3. 发明申请

WO2013095608A1 APPARATUS AND METHOD FOR VECTORIZATION WITH SPECULATION SUPPORT 审中-公开
标题翻译：用于带有参数支持的矢量化的装置和方法
公开(公告)号：WO2013095608A1
公开(公告)日：2013-06-27
申请号：PCT/US2011/067085
申请日：2011-12-23
申请人： INTEL CORPORATION , BHARADWAJ, Jayashankar , LEE, Victor W. , KIM, Daehyun , VASUDEVAN, Nalini , NGAI, Tin-Fook , HARTONO, Albert , BAGHSORKHI, Sara, S.
发明人： BHARADWAJ, Jayashankar , LEE, Victor W. , KIM, Daehyun , VASUDEVAN, Nalini , NGAI, Tin-Fook , HARTONO, Albert , BAGHSORKHI, Sara, S.
IPC分类号： G06F9/06 , G06F9/30
CPC分类号： G06F11/0751 , G06F9/30018 , G06F9/30036 , G06F9/30043
摘要： An apparatus and method are described for detecting and responding to fault conditions in a processor. For example, one embodiment of a method comprises: reading each active element in succession from a first vector register, each active element specifying an address for a gather or load operation; detecting one or more fault conditions associated with one or more of the active elements; for each active element read in succession prior to a detected fault condition on an element other than the first active element, storing the data loaded from an address associated with the active element in a first output vector register; and for each active element associated with the detected fault condition and following the detected fault condition, setting a bit in an output mask register to indicate the detected fault condition.
摘要翻译：描述了用于检测和响应处理器中的故障状况的装置和方法。例如，一种方法的一个实施例包括：从第一向量寄存器连续读取每个有源元件，每个有源元件指定用于集合或加载操作的地址; 检测与一个或多个所述有源元件相关联的一个或多个故障状况; 对于在除了所述第一有源元件之外的元件的检测到的故障状况之前连续读取的每个有源元件，将从与所述有源元件相关联的地址加载的数据存储在第一输出向量寄存器中; 并且对于与检测到的故障状况相关联的每个有源元件并且在检测到的故障状况之后，将输出屏蔽寄存器中的位设置为指示检测到的故障状况。

4. 发明申请

WO2013095606A1 APPARATUS AND METHOD FOR DETECTING IDENTICAL ELEMENTS WITHIN A VECTOR REGISTER 审中-公开
标题翻译：用于检测矢量寄存器中的标识元素的装置和方法
公开(公告)号：WO2013095606A1
公开(公告)日：2013-06-27
申请号：PCT/US2011/067083
申请日：2011-12-23
申请人： INTEL CORPORATION , LEE, Victor W. , KIM, Daehyun , NGAI, Tin-Fook , BHARADWAJ, Jayashankar , HARTONO, Albert , BAGHSORKHI, Sara , VASUDEVAN, Nalini
发明人： LEE, Victor W. , KIM, Daehyun , NGAI, Tin-Fook , BHARADWAJ, Jayashankar , HARTONO, Albert , BAGHSORKHI, Sara , VASUDEVAN, Nalini
IPC分类号： G06F9/06 , G06F9/30
CPC分类号： G06F9/30101 , G06F9/30018 , G06F9/30021 , G06F9/30036 , G06F9/30145
摘要： An apparatus, system and method are described for identifying identical elements in a vector register. For example, a computer implemented method according to one embodiment comprises the operations of: reading each active element from a first vector register, each active element having a defined bit position within the first vector register; reading each element from a second vector register, each element having a defined bit position within the second vector register corresponding to a bit position of a current active element in the first vector register; reading an input mask register, the input mask register identifying active bit positions in the second vector register for which comparisons are to be made with values in the first vector register, the comparison operations comprising: comparing each active element in the second vector register with elements in the first vector register having bit positions preceding the bit position of the current active element in the second vector register; and setting a bit position in an output mask register equal to a true value if all of the preceding bit positions in the first vector register are equal to the bit in the current active bit position in the second vector register.
摘要翻译：描述了用于识别向量寄存器中的相同元件的装置，系统和方法。例如，根据一个实施例的计算机实现的方法包括以下操作：从第一向量寄存器读取每个活动元件，每个有源元件在第一向量寄存器内具有定义的位位置; 从第二向量寄存器读取每个元素，每个元素在第二向量寄存器内具有对应于第一向量寄存器中当前有效元素的位位置的定义的位位置; 读取输入掩码寄存器，所述输入掩码寄存器识别所述第二向量寄存器中的活动位位置，用于与所述第一向量寄存器中的值进行比较，所述比较操作包括：将所述第二向量寄存器中的每个有效元素与元素在第一矢量寄存器中，位于第二向量寄存器中当前有效元件的位位置之前的位位置; 并且如果第一向量寄存器中的所有先前位位置等于第二向量寄存器中的当前活动位位置中的位，则将输出屏蔽寄存器中的位位置设置为等于真值。

5. 发明申请

WO2012006020A2 RELIABILITY SUPPORT IN MEMORY SYSTEMS WITHOUT ERROR CORRECTING CODE SUPPORT 审中-公开
标题翻译：可靠性支持内存系统，无错误更正代码支持
公开(公告)号：WO2012006020A2
公开(公告)日：2012-01-12
申请号：PCT/US2011/042020
申请日：2011-06-27
申请人： INTEL CORPORATION , STRACOVSKY, Henry , ESPIG, Michael , LEE, Victor W. , KIM, Daehyun
发明人： STRACOVSKY, Henry , ESPIG, Michael , LEE, Victor W. , KIM, Daehyun
IPC分类号： G06F12/16 , G06F12/00 , G06F11/10
CPC分类号： G06F11/1012 , H03M7/30 , H03M7/3082 , H03M7/6064 , H03M13/6312 , H03M13/6505 , H03M13/6566
摘要： Methods and apparatuses for error correction. A N-bit block data to be stored in a memory device is received. The memory device does not perform any error correction code (ECC) algorithm nor provide designated error correction code storage for the N-bit block of data. Data compression is applied to the N-bit data to compress the block of data to generate a M-bit compressed block of data. A K-bit ECC is computed for the M-bit compressed data, wherein M+K is less than or equal to N. The M-bit compressed data and the K-bit ECC are stored together in the memory device.
摘要翻译：用于纠错的方法和装置。接收要存储在存储装置中的N位块数据。存储器件不执行任何纠错码（ECC）算法，也不为N位数据块提供指定的纠错码存储。数据压缩应用于N位数据以压缩数据块以产生M位压缩数据块。针对M位压缩数据计算K位ECC，其中M + K小于或等于N.M位压缩数据和K位ECC一起存储在存储器件中。

6. 发明申请

WO2012135494A2 SYSTEM, APPARATUS, AND METHOD FOR ALIGNING REGISTERS 审中-公开
标题翻译：系统，装置和对准寄存器的方法
公开(公告)号：WO2012135494A2
公开(公告)日：2012-10-04
申请号：PCT/US2012/031202
申请日：2012-03-29
申请人： INTEL CORPORATION , SAN ADRIAN, Jesus Corbal , SANS, Roger Espasa , GIRKAR, Milind Baburao , WU, Lisa K. , BRADFORD, Dennis R. , LEE, Victor W.
发明人： SAN ADRIAN, Jesus Corbal , SANS, Roger Espasa , GIRKAR, Milind Baburao , WU, Lisa K. , BRADFORD, Dennis R. , LEE, Victor W.
IPC分类号： G06F9/06 , G06F9/30
CPC分类号： G06F9/30036 , G06F9/30018 , G06F9/30032 , G06F9/30192
摘要： Embodiments of systems, apparatuses, and methods for performing an align instruction in a computer processor are described. In some embodiments, the execution of an align instruction causes the selective storage of data elements of two concatenated sources to be stored in a destination.
摘要翻译：描述了用于在计算机处理器中执行对准指令的系统，装置和方法的实施例。在一些实施例中，对齐指令的执行导致将两个级联源的数据元素的选择性存储存储在目的地中。

7. 发明申请

WO2014105057A1 INSTRUCTION TO REDUCE ELEMENTS IN A VECTOR REGISTER WITH STRIDED ACCESS PATTERN 审中-公开
标题翻译：指示减少具有强力访问模式的矢量寄存器中的元件
公开(公告)号：WO2014105057A1
公开(公告)日：2014-07-03
申请号：PCT/US2012/072119
申请日：2012-12-28
申请人： INTEL CORPORATION
发明人： HARTONO, Albert , BHARADWAJ, Jayashankar , VASUDEVAN, Nalini , BAGHSORKHI, Sara S. , LEE, Victor W. , KIM, Daehyun
IPC分类号： G06F9/06 , G06F9/46
CPC分类号： G06F9/30036 , G06F9/3001 , G06F9/30018 , G06F9/30065 , G06F9/3455
摘要： A vector reduction instruction with non-unit strided access pattern is received and executed by the execution circuitry of a processor. In response to the instruction, the execution circuitry performs an associative reduction operation on data elements of a first vector register. Based on values of the mask register and a current element position being processed, the execution circuitry sequentially set one or more data elements of the first vector register to a result, which is generated by the associative reduction operation applied to both a previous data element of the first vector register and a data element of a third vector register. The previous data element is located more than one element position away from the current element position.
摘要翻译：具有非单位步进访问模式的向量减少指令由处理器的执行电路接收和执行。响应于该指令，执行电路对第一向量寄存器的数据元素执行关联缩小操作。基于掩模寄存器的值和正在处理的当前元件位置，执行电路依次将第一向量寄存器的一个或多个数据元素设置为通过应用于先前的数据元素的关联缩小操作生成的结果第一向量寄存器和第三向量寄存器的数据元素。先前的数据元素位于远离当前元素位置的多个元素位置。

8. 发明申请

WO2016105840A1 TECHNOLOGIES FOR LOW-LEVEL COMPOSABLE HIGH PERFORMANCE COMPUTING LIBRARIES 审中-公开
标题翻译：低水平复合高性能计算机图形技术
公开(公告)号：WO2016105840A1
公开(公告)日：2016-06-30
申请号：PCT/US2015/062692
申请日：2015-11-25
申请人： INTEL CORPORATION
发明人： RONG, Hongbo , TU, Peng , SHPEISMAN, Tatiana , LIU, Hai , ANDERSON, Todd A. , WU, Youfeng , GLEW, Arthur N. , PETERSEN, Paul M. , LEE, Victor W. , LOWNEY, P.G. , ROBINSON, Arch D. , WANG, Cheng
IPC分类号： G06F9/45 , G06F9/44
CPC分类号： G06F8/43 , G06F8/31 , G06F8/443 , G06F8/4441 , G06F8/453 , G06F8/49 , G06F8/54
摘要： Technologies for generating composable library functions include a first computing device that includes a library compiler configured to compile a composable library and second computing device that includes an application compiler configured to compose library functions of the composable library based on a plurality of abstractions written at different levels of abstractions. For example, the abstractions may include an algorithm abstraction at a high level, a blocked-algorithm abstraction at medium level, and a region-based code abstraction at a low level. Other embodiments are described and claimed herein.
摘要翻译：用于生成可组合库函数的技术包括：第一计算设备，其包括被配置为编译可组合库的库编译器和第二计算设备，所述第二计算设备包括应用编译器，所述应用编译器被配置为基于以不同级别写入的多个抽象来组合所述可组合库的库函数的抽象。例如，抽象可以包括高级别的算法抽象，中等级别的阻塞算法抽象，以及低级别的基于区域的代码抽象。在此描述和要求保护的其它实施例。

9. 发明申请

WO2016130311A1 PERFORMING POWER MANAGEMENT IN A MULTICORE PROCESSOR 审中-公开
标题翻译：在多处理器中执行电源管理
公开(公告)号：WO2016130311A1
公开(公告)日：2016-08-18
申请号：PCT/US2016/014830
申请日：2016-01-26
申请人： INTEL CORPORATION
发明人： LEE, Victor W. , GROCHOWSKI, Edward T. , KIM, Daehyun , BAI, Yuxin , LI, Sheng , MELLEMPUDI, Naveen K. , KALAMKAR, Dhiraj D.
IPC分类号： G06F1/32 , G06F1/26
CPC分类号： G06F1/3287 , G06F1/3225 , G06F1/324 , G06F1/3275 , G06F1/329 , G06F1/3296 , G06F9/50 , Y02D10/126 , Y02D10/14 , Y02D10/171 , Y02D10/172 , Y02D10/24
摘要： In an embodiment, a processor includes: a plurality of first cores to independently execute instructions, each of the plurality of first cores including a plurality of counters to store performance information; at least one second core to perform memory operations; and a power controller to receive performance information from at least some of the plurality of counters, determine a workload type executed on the processor based at least in part on the performance information, and based on the workload type dynamically migrate one or more threads from one or more of the plurality of first cores to the at least one second core for execution during a next operation interval. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，处理器包括：多个第一核，用于独立地执行指令，所述多个第一核中的每一个包括存储执行信息的多个计数器; 用于执行存储器操作的至少一个第二核心; 以及功率控制器，用于从所述多个计数器中的至少一些计数器接收性能信息，至少部分地基于所述性能信息确定在所述处理器上执行的工作负载类型，并且基于所述工作负载类型，动态地从一个或多个计算机迁移一个或多个线程或多个第一核心到至少一个第二核心，以在下一个操作间隔期间执行。描述和要求保护其他实施例。

10. 发明申请

WO2016105841A1 HARDWARE APPARATUSES AND METHODS TO PREFETCH A MULTIDIMENSIONAL BLOCK OF ELEMENTS FROM A MULTIMENSIONAL ARRAY 审中-公开
标题翻译：硬件设备和方法从多维阵列预先提取元素的多维块
公开(公告)号：WO2016105841A1
公开(公告)日：2016-06-30
申请号：PCT/US2015/062704
申请日：2015-11-25
申请人： INTEL CORPORATION
发明人： LEE, Victor W. , SMELYANSKIY, Mikhail , HEINECKE, Alexander F.
IPC分类号： G06F12/08 , G06F9/30
CPC分类号： G06F9/30047 , G06F9/30145 , G06F9/34 , G06F9/3455 , G06F12/0207 , G06F12/0811 , G06F12/0862 , G06F12/0875 , G06F2212/452 , G06F2212/6026
摘要： Methods and apparatuses relating to a prefetch instruction to prefetch a multidimensional block of elements from a multidimensional array into a cache. In one embodiment, a hardware processor includes a decoder to decode a prefetch instruction to prefetch a multidimensional block of elements from a multidimensional array into a cache, wherein at least one operand of the prefetch instruction is to indicate a system memory address of an element of the multidimensional block of elements, a stride of the multidimensional block of elements, and boundaries of the multidimensional block of elements, and an execution unit to execute the prefetch instruction to generate system memory addresses of the other elements of the multidimensional block of elements, and load the multidimensional block of elements into the cache from the system memory addresses.
摘要翻译：与预取指令相关的方法和装置，用于将多维数组的多维块预取到高速缓存。在一个实施例中，硬件处理器包括解码器，用于对预取指令进行解码，以将多维数组的多维块预取到多维阵列到高速缓存中，其中预取指令的至少一个操作数指示系统存储器地址元素的多维块，元素的多维块的步幅，以及元素的多维块的边界，以及执行单元，用于执行预取指令以生成多维元素块的其他元素的系统存储器地址，以及将多维元素块从系统内存地址加载到高速缓存中。

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