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1. 发明申请

WO2015148741A1 CO-DESIGNED DYNAMIC LANGUAGE ACCELERATOR FOR A PROCESSOR 审中-公开
标题翻译：用于处理器的CO设计动态语言加速器
公开(公告)号：WO2015148741A1
公开(公告)日：2015-10-01
申请号：PCT/US2015/022613
申请日：2015-03-26
申请人： INTEL CORPORATION
发明人： WANG, Cheng , WU, Youfeng , RONG, Hongbo , PARK, Hyunchul
IPC分类号： G06F13/16 , G06F9/455
CPC分类号： G06F9/45516 , G06F9/4411 , G06F9/4552 , G06F13/10
摘要： In an embodiment, a processor includes at least one core and a dynamic language accelerator to execute a bytecode responsive to a memory mapped input/output (MMIO) operation on a file descriptor associated with the dynamic language accelerator. The processor may block execution of native code while the dynamic language accelerator executes the bytecode. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，处理器包括至少一个核心和动态语言加速器，以响应于与动态语言加速器相关联的文件描述符的存储器映射的输入/输出（MMIO）操作来执行字节码。当动态语言加速器执行字节码时，处理器可能会阻止本地代码的执行。描述和要求保护其他实施例。

2. 发明申请

WO2015060850A1 CONJUGATE CODE GENERATION FOR EFFICIENT DYNAMIC OPTIMIZATIONS 审中-公开
标题翻译：有效动态优化的合并代码生成
公开(公告)号：WO2015060850A1
公开(公告)日：2015-04-30
申请号：PCT/US2013/066581
申请日：2013-10-24
申请人： INTEL CORPORATION , RONG, Hongbo , PARK, Hyunchul , WANG, Cheng , WU, Youfeng
发明人： RONG, Hongbo , PARK, Hyunchul , WANG, Cheng , WU, Youfeng
IPC分类号： G06F9/44 , G06F9/45
CPC分类号： G06F9/4552 , G06F8/4442 , G06F8/52 , G06F9/45508 , G06F9/45533
摘要： Methods and apparatus relating to conjugate code generation for efficient dynamic optimizations are described. In an embodiment, a binary code and an intermediate representation (IR) code are generated based at least partially on a source program. The binary code and the intermediate code are transmitted to a virtual machine logic. The binary code and the IR code each include a plurality of regions that are in one-to-one correspondence. Other embodiments are also claimed and described.
摘要翻译：描述了与有效动态优化的共轭码生成有关的方法和装置。在一个实施例中，至少部分地基于源程序生成二进制代码和中间表示（IR）代码。二进制代码和中间代码被传送到虚拟机逻辑。二进制代码和IR代码每个包括一对一对应的多个区域。还要求保护和描述其它实施例。

3. 发明申请

WO2017087078A1 TECHNOLOGIES FOR AUTOMATIC REORDERING OF SPARSE MATRICES 审中-公开
标题翻译：稀疏矩阵自动重排技术
公开(公告)号：WO2017087078A1
公开(公告)日：2017-05-26
申请号：PCT/US2016/054500
申请日：2016-09-29
申请人： INTEL CORPORATION
发明人： RONG, Hongbo , PARK, Jongsoo , ANDERSON, Todd A.
IPC分类号： G06F9/44
CPC分类号： G06F8/433 , G06F8/4434 , G06F8/4442 , G06F17/16
摘要： Technologies for automatic reordering of sparse matrices include a computing device to determine a distributivity of an expression defined in a code region of a program code. The expression is determined to be distributive if semantics of the expression are unaffected by a reordering of an input/output of the expression. The computing device performs inter-dependent array analysis on the expression to determine one or more clusters of inter-dependent arrays of the expression, wherein each array of a cluster of the one or more clusters is inter-dependent on each other array of the cluster, and performs bi-directional data flow analysis on the code region by iterative backward and forward propagation of reorderable arrays through expressions in the code region based on the one or more clusters of the inter-dependent arrays. The backward propagation is based on a backward transfer function and the forward propagation is based on a forward transfer function.
摘要翻译：用于稀疏矩阵的自动重新排序的技术包括用于确定在程序代码的代码区域中定义的表达式的分布性的计算设备。如果表达式的语义不受表达式的输入/输出的重新排序影响，则表达式被确定为分布式的。计算设备对该表达执行相互依赖的阵列分析以确定该表达的相互依赖的阵列的一个或多个群集，其中该一个或多个群集的群集的每个阵列相互依赖于该群集的每个其他阵列并且通过基于相互依赖的阵列的一个或多个群集通过代码区域中的表达式对可再定向阵列的迭代后向和前向传播来对代码区域执行双向数据流分析。后向传播基于后向传递函数，前向传播基于前向传递函数。

4. 发明申请

WO2013147896A1 INSTRUCTION AND LOGIC TO EFFICIENTLY MONITOR LOOP TRIP COUNT 审中-公开
标题翻译：指令和逻辑到有效的监视器循环次数
公开(公告)号：WO2013147896A1
公开(公告)日：2013-10-03
申请号：PCT/US2012/031711
申请日：2012-03-30
申请人： INTEL CORPORATION , PARK, Hyunchul , RONG, Hongbo , WANG, Cheng , YU, Youfeng , CHUNG, Jaewoong
发明人： PARK, Hyunchul , RONG, Hongbo , WANG, Cheng , YU, Youfeng , CHUNG, Jaewoong
IPC分类号： G06F9/06 , G06F9/30
CPC分类号： G06F9/325 , G06F8/443 , G06F9/30072 , G06F9/3842 , G06F9/3857 , G06F11/3409 , G06F11/348 , G06F2201/88
摘要： Logic and instruction to efficiently monitor loop trip count. Loop trip count information of a loop may be stored in a dedicated hardware buffer. Average loop trip count of the loop may be calculated based on the stored loop trip count information. Based on the average trip count, loop optimizations may be applied or removed from the loop. The stored loop trip count information may include an identifier identifying the loop, a total loop trip count of the loop, and an exit count of the loop.
摘要翻译：有效监控回路行程数的逻辑和指令。循环的循环行程计数信息可以存储在专用硬件缓冲器中。可以基于存储的循环行程计数信息来计算循环的平均循环行程计数。基于平均行程计数，循环优化可以从循环中应用或移除。存储的循环行程计数信息可以包括标识循环的标识符，循环的总循环行程计数以及循环的退出计数。

5. 发明申请

WO2016105840A1 TECHNOLOGIES FOR LOW-LEVEL COMPOSABLE HIGH PERFORMANCE COMPUTING LIBRARIES 审中-公开
标题翻译：低水平复合高性能计算机图形技术
公开(公告)号：WO2016105840A1
公开(公告)日：2016-06-30
申请号：PCT/US2015/062692
申请日：2015-11-25
申请人： INTEL CORPORATION
发明人： RONG, Hongbo , TU, Peng , SHPEISMAN, Tatiana , LIU, Hai , ANDERSON, Todd A. , WU, Youfeng , GLEW, Arthur N. , PETERSEN, Paul M. , LEE, Victor W. , LOWNEY, P.G. , ROBINSON, Arch D. , WANG, Cheng
IPC分类号： G06F9/45 , G06F9/44
CPC分类号： G06F8/43 , G06F8/31 , G06F8/443 , G06F8/4441 , G06F8/453 , G06F8/49 , G06F8/54
摘要： Technologies for generating composable library functions include a first computing device that includes a library compiler configured to compile a composable library and second computing device that includes an application compiler configured to compose library functions of the composable library based on a plurality of abstractions written at different levels of abstractions. For example, the abstractions may include an algorithm abstraction at a high level, a blocked-algorithm abstraction at medium level, and a region-based code abstraction at a low level. Other embodiments are described and claimed herein.
摘要翻译：用于生成可组合库函数的技术包括：第一计算设备，其包括被配置为编译可组合库的库编译器和第二计算设备，所述第二计算设备包括应用编译器，所述应用编译器被配置为基于以不同级别写入的多个抽象来组合所述可组合库的库函数的抽象。例如，抽象可以包括高级别的算法抽象，中等级别的阻塞算法抽象，以及低级别的基于区域的代码抽象。在此描述和要求保护的其它实施例。

6. 发明申请

WO2014193381A1 DYNAMIC OPTIMIZATION OF PIPELINED SOFTWARE 审中-公开
标题翻译：管道软件动态优化
公开(公告)号：WO2014193381A1
公开(公告)日：2014-12-04
申请号：PCT/US2013/043296
申请日：2013-05-30
申请人： INTEL CORPORATION
发明人： PARK, Hyunchul , RONG, Hongbo , WU, Youfeng
IPC分类号： G06F9/38 , G06F9/46
CPC分类号： G06F8/4452 , G06F8/441 , G06F8/443 , G06F8/4451 , G06F9/3836 , G06F9/384 , G06F9/3863
摘要： In an embodiment, a system includes a processor including at least one core to execute operations of a loop that includes S stages. The system also includes stage insertion means for adding a delay stage to the loop to increase a lifetime of a corresponding register associated with a first variable of the loop and to delay storage of contents of the register. The system also includes a dynamic random access memory (DRAM). Other embodiments are described and claimed.
摘要翻译：在一个实施例中，系统包括处理器，其包括至少一个核，以执行包括S级的循环的操作。该系统还包括阶段插入装置，用于向环路增加延迟级，以增加与循环的第一变量相关联的相应寄存器的寿命并延迟存储寄存器的内容。该系统还包括动态随机存取存储器（DRAM）。描述和要求保护其他实施例。

7. 发明申请

WO2014193375A1 ALLOCATION OF ALIAS REGISTERS IN A PIPELINED SCHEDULE 审中-公开
标题翻译：在管道附表中分配ALIAS注册
公开(公告)号：WO2014193375A1
公开(公告)日：2014-12-04
申请号：PCT/US2013/043224
申请日：2013-05-30
申请人： INTEL CORPORATION
发明人： RONG, Hongbo , WANG, Cheng , PARK, Hyunchul , WU, Youfeng
IPC分类号： G06F9/46 , G06F9/38 , G06F13/16
CPC分类号： G06F9/3838 , G06F8/434 , G06F8/441 , G06F8/443 , G06F9/30127 , G06F9/3017 , G06F9/3834 , G06F9/384
摘要： In an embodiment, a system includes a processor including one or more cores and a plurality of alias registers to store memory range information associated with a plurality of operations of a loop. The memory range information references one or more memory locations within a memory. The system also includes register assignment means for assigning each of the alias registers to a corresponding operation of the loop, where the assignments are made according to a rotation schedule, and one of the alias registers is assigned to a first operation in a first iteration of the loop and to a second operation in a subsequent iteration of the loop. The system also includes the memory coupled to the processor. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，系统包括处理器，其包括一个或多个核和多个别名寄存器，用于存储与循环的多个操作相关联的存储器范围信息。存储器范围信息引用存储器内的一个或多个存储器位置。该系统还包括寄存器分配装置，用于将每个别名寄存器分配给循环的对应操作，其中根据旋转调度进行分配，并且在第一次迭代中将一个别名寄存器分配给第一操作循环和循环的后续迭代中的第二操作。该系统还包括耦合到处理器的存储器。描述和要求保护其他实施例。

8. 发明申请

WO2014160837A1 SOFTWARE PIPELINING AT RUNTIME 审中-公开
标题翻译：软件管道运行
公开(公告)号：WO2014160837A1
公开(公告)日：2014-10-02
申请号：PCT/US2014/031975
申请日：2014-03-27
申请人： INTEL CORPORATION , RONG, Hongbo , PARK, Hyunchul , WU, Youfeng
发明人： RONG, Hongbo , PARK, Hyunchul , WU, Youfeng
IPC分类号： G06F9/38 , G06F9/46
CPC分类号： G06F8/4452 , G06F8/433
摘要： Apparatuses and methods may provide for determining a level of performance for processing one or more loops by a dynamic compiler and executing code optimizations to generate a pipelined schedule for the one or more loops that achieves the determined level of performance within a prescribed time period. In one example, a dependence graph may be established for the one or more loops, and each dependence graph may be partitioned into stages based on the level of performance.
摘要翻译：设备和方法可以提供用于通过动态编译器来确定用于处理一个或多个循环的性能水平，并且执行代码优化以生成用于在规定时间段内实现确定的性能水平的一个或多个循环的流水线调度。在一个示例中，可以为一个或多个循环建立依赖图，并且可以基于性能水平将每个依赖图划分成多个阶段。

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