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1. 发明申请

WO2014142972A1 METHODS AND SYSTEMS TO VECTORIZE SCALAR COMPUTER PROGRAM LOOPS HAVING LOOP-CARRIED DEPENDENCES 审中-公开
标题翻译：用于展示具有循环载体的标量计算机程序脚本的方法和系统
公开(公告)号：WO2014142972A1
公开(公告)日：2014-09-18
申请号：PCT/US2013/032111
申请日：2013-03-15
申请人： INTEL CORPORATION , BHARADWAJ, Jayashankar , VASUDEVAN, Nalini , HARTONO, Albert , BAGHSORKHI, Sara S.
发明人： BHARADWAJ, Jayashankar , VASUDEVAN, Nalini , HARTONO, Albert , BAGHSORKHI, Sara S.
IPC分类号： G06F9/06 , G06F9/30 , G06F9/44
CPC分类号： G06F8/4441 , G06F8/443 , G06F8/452 , G06F9/06 , G06F9/30 , G06F9/44
摘要： Methods and systems to convert scalar computer program loops having loop carried dependences to vector computer program loops are disclosed. One example method and system generates a first predicate set associated with a first conditionally executed statement. The first predicate set contains a first set of predicates that cause a variable to be defined in a scalar computer program loop at or before the variable is defined by the first conditionally executed statement. The method and system also generates a second predicate set associated with the first conditionally executed statement. The second predicate set contains a second set of predicates that cause the variable to be used in the scalar computer program loop at or before the variable is defined by the first conditionally executed statement. The method and system determines whether the second predicate set is a subset of the first predicate set and, based on the determination, propagates a vector value in an element of a vector of the variable to a subsequent element of the vector.
摘要翻译：公开了将具有循环携带依赖性的标量计算机程序循环转换为向量计算机程序循环的方法和系统。一个示例性方法和系统生成与第一条件执行语句相关联的第一谓词集合。第一个谓词集包含第一组谓词，导致在第一个有条件执行的语句定义变量之前或之前，在标量计算机程序循环中定义变量。方法和系统还生成与第一条件执行语句相关联的第二谓词集合。第二个谓词集包含第二组谓词，导致在第一个有条件执行的语句定义变量之前或之前在标量计算机程序循环中使用该变量。方法和系统确定第二谓词集是否是第一谓词集的子集，并且基于该确定，将该变量的向量的元素中的向量值传播到向量的后续元素。

2. 发明申请

WO2013147869A1 APPARATUS AND METHOD FOR SELECTING ELEMENTS OF A VECTOR COUMPUTATION 审中-公开
标题翻译：选择矢量图选择元素的装置和方法
公开(公告)号：WO2013147869A1
公开(公告)日：2013-10-03
申请号：PCT/US2012/031596
申请日：2012-03-30
申请人： INTEL CORPORATION , LEE, Victor W. , BHARADWAJ, Jayashankar , KIM, Daehyun , VASUDEVAN, Nalini , NGAI, Tin-Fook , HARTONO, Albert , BAGHSORKHI, Sara
发明人： LEE, Victor W. , BHARADWAJ, Jayashankar , KIM, Daehyun , VASUDEVAN, Nalini , NGAI, Tin-Fook , HARTONO, Albert , BAGHSORKHI, Sara
IPC分类号： G06F1/00 , G06F9/06 , G06F9/302
CPC分类号： G06F7/548 , G06F9/3001 , G06F9/30018 , G06F9/30036 , G06F9/30145 , G06F9/3877 , G06F9/3895
摘要： An apparatus and method are described for performing a vector reduction. For example, an apparatus according to one embodiment comprises: a reduction logic tree comprised of a set of N- l reduction logic blocks used to perform reduction in a single operation cycle for N vector elements; a first input vector register storing a first input vector communicatively Coupled to the set of reduction logic blocks; a second input vector register storing a second input vector communicatively coupled to the set of reduction logic blocks; a mask register storing a mask value controlling a set of one or more multiplexers, each of the set of multiplexers selecting a value directly from the first input vector register or an output containing a processed value from one of the reduction logic blocks; and an output vector register coupled to outputs of the one or more multiplexers to receive values output passed through by each of the multiplexers responsive to the control signals.
摘要翻译：描述了用于执行向量减少的装置和方法。例如，根据一个实施例的装置包括：还原逻辑树，包括用于对N个向量元素执行单个操作周期的减少的一组N-1个减少逻辑块; 第一输入向量寄存器，其以通信方式存储耦合到所述一组还原逻辑块的第一输入向量; 存储通信地耦合到所述一组减少逻辑块的第二输入向量的第二输入向量寄存器; 屏蔽寄存器，其存储控制一个或多个多路复用器的集合的掩码值，所述多路复用器集合中的每一个直接从所述第一输入向量寄存器选择值，或者包含来自所述还原逻辑块之一的处理值的输出; 以及耦合到所述一个或多个多路复用器的输出的输出矢量寄存器，以响应于所述控制信号接收由所述多路复用器中的每一个通过的值。

3. 发明申请

WO2013095608A1 APPARATUS AND METHOD FOR VECTORIZATION WITH SPECULATION SUPPORT 审中-公开
标题翻译：用于带有参数支持的矢量化的装置和方法
公开(公告)号：WO2013095608A1
公开(公告)日：2013-06-27
申请号：PCT/US2011/067085
申请日：2011-12-23
申请人： INTEL CORPORATION , BHARADWAJ, Jayashankar , LEE, Victor W. , KIM, Daehyun , VASUDEVAN, Nalini , NGAI, Tin-Fook , HARTONO, Albert , BAGHSORKHI, Sara, S.
发明人： BHARADWAJ, Jayashankar , LEE, Victor W. , KIM, Daehyun , VASUDEVAN, Nalini , NGAI, Tin-Fook , HARTONO, Albert , BAGHSORKHI, Sara, S.
IPC分类号： G06F9/06 , G06F9/30
CPC分类号： G06F11/0751 , G06F9/30018 , G06F9/30036 , G06F9/30043
摘要： An apparatus and method are described for detecting and responding to fault conditions in a processor. For example, one embodiment of a method comprises: reading each active element in succession from a first vector register, each active element specifying an address for a gather or load operation; detecting one or more fault conditions associated with one or more of the active elements; for each active element read in succession prior to a detected fault condition on an element other than the first active element, storing the data loaded from an address associated with the active element in a first output vector register; and for each active element associated with the detected fault condition and following the detected fault condition, setting a bit in an output mask register to indicate the detected fault condition.
摘要翻译：描述了用于检测和响应处理器中的故障状况的装置和方法。例如，一种方法的一个实施例包括：从第一向量寄存器连续读取每个有源元件，每个有源元件指定用于集合或加载操作的地址; 检测与一个或多个所述有源元件相关联的一个或多个故障状况; 对于在除了所述第一有源元件之外的元件的检测到的故障状况之前连续读取的每个有源元件，将从与所述有源元件相关联的地址加载的数据存储在第一输出向量寄存器中; 并且对于与检测到的故障状况相关联的每个有源元件并且在检测到的故障状况之后，将输出屏蔽寄存器中的位设置为指示检测到的故障状况。

4. 发明申请

WO2013095642A1 SYSTEMS, APPARATUSES, AND METHODS FOR SETTING AN OUTPUT MASK IN A DESTINATION WRITEMASK REGISTER FROM A SOURCE WRITE MASK REGISTER USING AN INPUT WRITEMASK AND IMMEDIATE 审中-公开
标题翻译：用于使用输入写入和立即从源写入掩码寄存器设置目的地写入寄存器中的输出掩码的系统，设备和方法
公开(公告)号：WO2013095642A1
公开(公告)日：2013-06-27
申请号：PCT/US2011/067219
申请日：2011-12-23
申请人： INTEL CORPORATION , LEE, Victor, W. , KIM, Daehyun , NGAI, Tin-fook , BHARADWAJ, Jayashankar , HARTONO, Albert , BAGHSORKHI, Sara , VASUDEVAN, Nalini
发明人： LEE, Victor, W. , KIM, Daehyun , NGAI, Tin-fook , BHARADWAJ, Jayashankar , HARTONO, Albert , BAGHSORKHI, Sara , VASUDEVAN, Nalini
IPC分类号： G06F9/06 , G06F9/30
CPC分类号： G06F9/30036 , G06F9/30018 , G06F9/30021 , G06F9/30025 , G06F9/30072 , G06F15/8007 , G06F15/8053 , G06F15/8084 , G06F15/8092
摘要： Embodiments of systems, apparatuses, and methods for performing in a computer processor generation of a predicate mask based on vector comparison in response to a single instruction are described.
摘要翻译：描述了用于在计算机处理器中执行基于向量比较响应于单个指令生成谓词掩码的系统，装置和方法的实施例。

5. 发明申请

WO2013095617A1 APPARATUS AND METHOD FOR PROPAGATING CONDITIONALLY EVALUATED VALUES IN SIMD/VECTOR EXECUTION 审中-公开
标题翻译：在SIMD / VECTOR执行中传播有条件评估值的装置和方法
公开(公告)号：WO2013095617A1
公开(公告)日：2013-06-27
申请号：PCT/US2011/067094
申请日：2011-12-23
申请人： INTEL CORPORATION , BHARADWAJ, Jayashankar , VASUDEVAN, Nalini , LEE, Victor, W. , KIM, Daehyun , HARTONO, Albert , BAGHSORKHI, Sara, S.
发明人： BHARADWAJ, Jayashankar , VASUDEVAN, Nalini , LEE, Victor, W. , KIM, Daehyun , HARTONO, Albert , BAGHSORKHI, Sara, S.
IPC分类号： G06F9/06 , G06F9/30
CPC分类号： G06F9/30018 , G06F9/30032 , G06F9/30036 , G06F9/30098 , G06F9/30192 , G06F9/3877
摘要： An apparatus and method for propagating conditionally evaluated values. For example, a method according to one embodiment comprises: reading each value contained in an input mask register, each value being a true value or a false value and having a bit position associated therewith; for each true value read from the input mask register, generating a first result containing the bit position of the true value; for each false value read from the input mask register following the first true value, adding the vector length of the input mask register to a bit position of the last true value read from the input mask register to generate a second result; and storing each of the first results and second results in bit positions of an output register corresponding to the bit positions read from the input mask register.
摘要翻译：用于传播有条件评估值的装置和方法。例如，根据一个实施例的方法包括：读取输入屏蔽寄存器中包含的每个值，每个值是真值或假值，并具有与其相关联的位位置; 对于从输入掩码寄存器读取的每个真值，生成包含真值的位位置的第一结果; 对于从输入屏蔽寄存器读取的每个错误值跟随第一个真实值，将输入屏蔽寄存器的向量长度加到从输入屏蔽寄存器读取的最后一个真值的位位置，以产生第二个结果; 并将每个第一结果和第二结果存储在与从输入屏蔽寄存器读取的位位置对应的输出寄存器的位位置中。

6. 发明申请

WO2013095616A1 APPARATUS AND METHOD FOR SELECTING ELEMENTS OF A VECTOR COMPUTATION 审中-公开
标题翻译：选择矢量计算要素的装置和方法
公开(公告)号：WO2013095616A1
公开(公告)日：2013-06-27
申请号：PCT/US2011/067093
申请日：2011-12-23
申请人： INTEL CORPORATION , BHARADWAJ, Jayashankar , VASUDEVAN, Nalini , LEE, Victor , KIM, Daehyun , BAGHSORKHI, Sara , HARTONO, Albert
发明人： BHARADWAJ, Jayashankar , VASUDEVAN, Nalini , LEE, Victor , KIM, Daehyun , BAGHSORKHI, Sara , HARTONO, Albert
IPC分类号： G06F9/06 , G06F9/30 , G06F9/305
CPC分类号： G06F9/30098 , G06F9/30018 , G06F9/30036
摘要： An apparatus and method are described for selecting elements to be used in a vector computation. For example, a method according to one embodiment includes the following operations: specifying whether to identify the first, last or next after last active element of an input mask register using an immediate value; identifying the first, last or next after last active element in the input mask register according to the immediate value; reading a value from an input vector register corresponding to the identified first, last or next after last active element in the input mask register; and writing the value to an output vector register.
摘要翻译：描述了用于选择要在向量计算中使用的元素的装置和方法。例如，根据一个实施例的方法包括以下操作：使用立即值来指定是否识别输入屏蔽寄存器的第一，最后或下一个有效元素; 根据立即值识别输入屏蔽寄存器中的最后一个或最后一个有效元素; 从输入矢量寄存器读取对应于输入屏蔽寄存器中识别的第一，最后或下一个最后有效元件的值; 并将该值写入输出向量寄存器。

7. 发明申请

WO2013095606A1 APPARATUS AND METHOD FOR DETECTING IDENTICAL ELEMENTS WITHIN A VECTOR REGISTER 审中-公开
标题翻译：用于检测矢量寄存器中的标识元素的装置和方法
公开(公告)号：WO2013095606A1
公开(公告)日：2013-06-27
申请号：PCT/US2011/067083
申请日：2011-12-23
申请人： INTEL CORPORATION , LEE, Victor W. , KIM, Daehyun , NGAI, Tin-Fook , BHARADWAJ, Jayashankar , HARTONO, Albert , BAGHSORKHI, Sara , VASUDEVAN, Nalini
发明人： LEE, Victor W. , KIM, Daehyun , NGAI, Tin-Fook , BHARADWAJ, Jayashankar , HARTONO, Albert , BAGHSORKHI, Sara , VASUDEVAN, Nalini
IPC分类号： G06F9/06 , G06F9/30
CPC分类号： G06F9/30101 , G06F9/30018 , G06F9/30021 , G06F9/30036 , G06F9/30145
摘要： An apparatus, system and method are described for identifying identical elements in a vector register. For example, a computer implemented method according to one embodiment comprises the operations of: reading each active element from a first vector register, each active element having a defined bit position within the first vector register; reading each element from a second vector register, each element having a defined bit position within the second vector register corresponding to a bit position of a current active element in the first vector register; reading an input mask register, the input mask register identifying active bit positions in the second vector register for which comparisons are to be made with values in the first vector register, the comparison operations comprising: comparing each active element in the second vector register with elements in the first vector register having bit positions preceding the bit position of the current active element in the second vector register; and setting a bit position in an output mask register equal to a true value if all of the preceding bit positions in the first vector register are equal to the bit in the current active bit position in the second vector register.
摘要翻译：描述了用于识别向量寄存器中的相同元件的装置，系统和方法。例如，根据一个实施例的计算机实现的方法包括以下操作：从第一向量寄存器读取每个活动元件，每个有源元件在第一向量寄存器内具有定义的位位置; 从第二向量寄存器读取每个元素，每个元素在第二向量寄存器内具有对应于第一向量寄存器中当前有效元素的位位置的定义的位位置; 读取输入掩码寄存器，所述输入掩码寄存器识别所述第二向量寄存器中的活动位位置，用于与所述第一向量寄存器中的值进行比较，所述比较操作包括：将所述第二向量寄存器中的每个有效元素与元素在第一矢量寄存器中，位于第二向量寄存器中当前有效元件的位位置之前的位位置; 并且如果第一向量寄存器中的所有先前位位置等于第二向量寄存器中的当前活动位位置中的位，则将输出屏蔽寄存器中的位位置设置为等于真值。

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