专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

WO2013100894A1 METHOD OF FORMING LOW RESISTIVITY TANX/TA DIFFUSION BARRIERS FOR BACKEND INTERCONNECTS 审中-公开
标题翻译：形成低电阻TANX / TA扩展障碍的方法用于后置互连
公开(公告)号：WO2013100894A1
公开(公告)日：2013-07-04
申请号：PCT/US2011/067342
申请日：2011-12-27
申请人： INTEL CORPORATION , JEZEWSKI, Christopher , BOYANOV, Boyan , CLARKE, James J. , FABER, Jacob J.
发明人： JEZEWSKI, Christopher , BOYANOV, Boyan , CLARKE, James J. , FABER, Jacob J.
IPC分类号： H01L21/28 , H01L21/318
CPC分类号： H01L21/76846 , C23C14/0036 , C23C14/165 , C23C14/35 , H01L21/2855 , H01L21/76843 , H01L21/76873 , H01L21/76879 , H01L23/53238 , H01L23/53252 , H01L23/53261 , H01L23/53266 , H01L23/53295 , H01L2221/1089 , H01L2924/0002 , H01L2924/00
摘要： The present disclosure relates diffusion barrier layers for backend interconnects and their methods of manufacturing.A TaN x /Ta diffusion barrier layer used for backend interconnect is formed at a temperature between about 150-450°C, wherein the Ta film exhibits a body-centered-cubic (BCC) structure and a lower electrical resistivity. Other embodiments are described and claimed.
摘要翻译：本公开涉及用于后端互连的扩散阻挡层及其制造方法。在用于后端互连的TaNx / Ta扩散阻挡层在约150-450℃之间的温度下形成，其中Ta膜表现出以体为中心的 - 立方（BCC）结构和较低的电阻率。描述和要求保护其他实施例。

2. 发明申请

WO2005067055A1 TRANSISTOR GATE ELECTRODE HAVING CONDUCTOR MATERIAL LAYER 审中-公开
标题翻译：具有导体材料层的晶体管栅极电极
公开(公告)号：WO2005067055A1
公开(公告)日：2005-07-21
申请号：PCT/US2004/043663
申请日：2004-12-22
申请人： INTEL CORPORATION , MURPHY, Anand , BOYANOV, Boyan , DATTA, Suman , DOYLE, Brian, S. , JIN, Been-Yih , YU, Shaofeng , CHAU, Robert
发明人： MURPHY, Anand , BOYANOV, Boyan , DATTA, Suman , DOYLE, Brian, S. , JIN, Been-Yih , YU, Shaofeng , CHAU, Robert
IPC分类号： H01L29/10
CPC分类号： H01L29/1054 , H01L21/823807 , H01L21/823814 , H01L21/823842 , H01L21/823857 , H01L29/66636 , H01L29/7842 , H01L29/7848
摘要： Various embodiments of the invention relates to a PMOS device having a transistor channel of silicon germanium material on a substrate, a gate dielectric having a dielectric constant greater than that of silicon dioxide on the channel, a gate electrode conductor material having a work function in a range between a valence energy band edge and a conductor energy band edge for silicon on the gate dielectric, and a gate electrode semiconductor material on the gate electrode conductor material.
摘要翻译：本发明的各种实施例涉及一种在衬底上具有硅锗材料的晶体管沟道的PMOS器件，介电常数大于沟道上的二氧化硅的介电常数的栅极电介质，具有工作功能的栅电极导体材料在栅极电介质上的硅的价态能带边缘和导体能带边缘之间的范围，以及栅电极导体材料上的栅电极半导体材料。

3. 发明申请

WO2008036385A1 DIELECTRIC SPACERS FOR METAL INTERCONNECTS AND METHOD TO FORM THE SAME 审中-公开
标题翻译：用于金属互连的电介质间隔件及其形成方法
公开(公告)号：WO2008036385A1
公开(公告)日：2008-03-27
申请号：PCT/US2007/020443
申请日：2007-09-21
申请人： INTEL CORPORATION , BIELEFELD, Jeffery, D. , BOYANOV, Boyan
发明人： BIELEFELD, Jeffery, D. , BOYANOV, Boyan
IPC分类号： H01L21/3205 , H01L21/28
CPC分类号： H01L21/7682 , H01L21/76804 , H01L21/76831 , H01L21/76885 , H01L23/5222 , H01L23/5283 , H01L23/53238 , H01L23/53276 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： Dielectric spacers for a plurality of metal interconnects and a method to form such dielectric spacers are described. In one embodiment, the dielectric spacers are adjacent to neighboring metal interconnects having flared profiles and are discontiguous from one another. In another embodiment, the dielectric spacers provide a region upon which un-landed vias may effectively land.
摘要翻译：描述了用于多个金属互连的介电间隔件以及形成这种介电间隔物的方法。在一个实施例中，介电间隔物与具有扩口轮廓的相邻金属互连件相邻并且彼此不连续。在另一个实施例中，电介质间隔物提供了一个区域，未着陆过孔可以有效地着陆。

4. 发明申请

WO2013101204A1 SELF-ENCLOSED ASYMMETRIC INTERCONNECT STRUCTURES 审中-公开
标题翻译：自封不对称互连结构
公开(公告)号：WO2013101204A1
公开(公告)日：2013-07-04
申请号：PCT/US2011/068159
申请日：2011-12-30
申请人： INTEL CORPORATION , BOYANOV, Boyan
发明人： BOYANOV, Boyan
IPC分类号： H01L21/28
CPC分类号： H01L23/522 , H01L21/768 , H01L21/76804 , H01L21/76829 , H01L21/76834 , H01L21/76849 , H01L21/76883 , H01L21/76897 , H01L23/5226 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： Techniques are disclosed that enable improved shorting margin between unlanded conductive interconnect features and neighboring conductive features. The techniques provided are particularly useful, for instance, when lithography registration errors cause neighboring conductive features to be physically closer than expected, but can also be used when such proximity is intentional. In some embodiments, the techniques can be implemented using a layer of electromigration management material (EMM) and one or more insulator layers, wherein the various layers are provisioned to enable a differential etch rate. In particular, the overall etch rate of materials above the target landing pad is faster than the overall etch rate of materials above the off-target landing pad, which results in a self-enclosed conductive interconnect feature having an asymmetric taper or profile. The differential etch rate may result, for example, from configuration of the EMM layer, or from accompanying insulator layers having different etch rates.
摘要翻译：公开了能够改善未上行的导电互连特征与相邻导电特征之间的短路裕度的技术。所提供的技术特别有用，例如，当光刻注册误差导致相邻的导电特征物理上比预期的更近，但是当这种接近是有意的时也可以使用。在一些实施例中，可以使用电迁移管理材料层（EMM）和一个或多个绝缘体层来实现这些技术，其中提供各种层以实现差分蚀刻速率。特别地，目标着陆焊盘上方的材料的总体蚀刻速率比在靶外着陆焊盘上方的材料的总体蚀刻速度更快，这导致具有不对称锥度或轮廓的自封闭导电互连特征。差分蚀刻速率可以由例如EMM层的构造或者具有不同蚀刻速率的伴随的绝缘体层产生。

5. 发明申请

WO2005062366A1 METHOD FOR IMPROVING TRANSISTOR PERFORMANCE THROUGH REDUCING THE SALICIDE INTERFACE RESISTANCE 审中-公开
标题翻译：通过减少绝缘体接触电阻来提高晶体管性能的方法
公开(公告)号：WO2005062366A1
公开(公告)日：2005-07-07
申请号：PCT/US2004/038986
申请日：2004-11-19
申请人： INTEL CORPORATION , MURTHY, Anand , BOYANOV, Boyan , GLASS, Glenn , HOFFMANN, Thomas
发明人： MURTHY, Anand , BOYANOV, Boyan , GLASS, Glenn , HOFFMANN, Thomas
IPC分类号： H01L21/336
CPC分类号： H01L29/7848 , H01L21/28518 , H01L21/823807 , H01L21/823814 , H01L29/0653 , H01L29/0847 , H01L29/165 , H01L29/167 , H01L29/36 , H01L29/41725 , H01L29/6628 , H01L29/665 , H01L29/6653 , H01L29/6656 , H01L29/6659 , H01L29/66628 , H01L29/66636 , H01L29/78 , H01L29/7833 , H01L29/7842 , Y10S438/933
摘要： An embodiment of the invention reduces the external resistance of a transistor by utilizing a silicon germanium alloy for the source and drain regions and a nickel silicon germanium self-aligned silicide (i.e., salicide) layer to form the contact surface of the source and drain regions. The interface of the silicon germanium and the nickel silicon germanium silicide has a lower specific contact resistivity based on a decreased metalsemiconductor work function between the silicon germanium and the silicide and the increased carrier mobility in silicon germanium versus silicon. The silicon germanium may be doped to further tune its electrical properties. A reduction of the external resistance of a transistor equates to increased transistor performance both in switching speed and power consumption.
摘要翻译：本发明的一个实施例通过利用用于源极和漏极区域的硅锗合金和镍硅锗自对准硅化物（即，自对准硅化物）层来形成源极和漏极区域的接触表面来降低晶体管的外部电阻。基于硅锗和硅化物之间的金属半导体功函数降低，硅锗与硅硅锗的界面具有较低的比接触电阻率，并且硅锗与硅中的载流子迁移率增加。可以掺杂硅锗以进一步调整其电性能。降低晶体管的外部电阻等同于在开关速度和功耗方面提高晶体管的性能。

6. 发明申请

WO2013066356A1 METHODS AND APPARATUSES TO FORM SELF-ALIGNED CAPS 审中-公开
标题翻译：形成自对准CAPS的方法和装置
公开(公告)号：WO2013066356A1
公开(公告)日：2013-05-10
申请号：PCT/US2011/059453
申请日：2011-11-04
申请人： INTEL CORPORATION , BOYANOV, Boyan , SINGH, Kanwal Jit
发明人： BOYANOV, Boyan , SINGH, Kanwal Jit
IPC分类号： H01L21/28
CPC分类号： H01L23/53238 , H01L21/76802 , H01L21/7684 , H01L21/76849 , H01L21/7685 , H01L21/76879 , H01L21/76883 , H01L23/485 , H01L23/5226 , H01L23/528 , H01L23/53209 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： At least one conductive line in a dielectric layer over a substrate is recessed to form a channel. The channel is self-aligned to the conductive line. The channel can be formed by etching the conductive line to a predetermined depth using a chemistry comprising an inhibitor to provide uniformity of etching independent of a crystallographic orientation. A capping layer to prevent electromigration is deposited on the recessed conductive line in the channel. The channel is configured to contain the capping layer within the width of the conductive line.
摘要翻译：在衬底上的电介质层中的至少一个导电线凹入以形成沟道。通道与导线自对准。可以通过使用包含抑制剂的化学品将导电线蚀刻到预定深度来形成沟道，以提供独立于晶体取向的蚀刻均匀性。用于防止电迁移的覆盖层沉积在通道中的凹进的导电线上。通道被配置为在导电线的宽度内容纳覆盖层。

7. 发明申请

WO2009085506A1 AIR-GAP ILD WITH UNLANDED VIAS 审中-公开
标题翻译：带有野生VIAS的空气隙空气
公开(公告)号：WO2009085506A1
公开(公告)日：2009-07-09
申请号：PCT/US2008/084680
申请日：2008-11-25
申请人： INTEL CORPORATION , BALAKRISHNAN, Sridhar , BOYANOV, Boyan
发明人： BALAKRISHNAN, Sridhar , BOYANOV, Boyan
IPC分类号： H01L21/3205 , H01L21/4763 , H01L21/31
CPC分类号： H01L21/7682 , H01L21/76807 , H01L21/76834 , H01L21/76885 , H01L23/5222 , H01L23/53295 , H01L2924/0002 , H01L2924/14 , H01L2924/00
摘要： A spacer is adjacent to a conductive line. Vias that do not completely land on the conductive line land on the spacer and do not punch through into a volume below the spacer.
摘要翻译：间隔件与导线相邻。没有完全降落在间隔物上的导电线上的通孔，并且不穿入隔垫之下的体积。

8. 发明申请

WO2007130368A2 DIELECTRIC SPACERS FOR METAL INTERCONNECTS AND METHOD TO FORM THE SAME 审中-公开
标题翻译：用于金属互连的介电间隔件及其形成方法
公开(公告)号：WO2007130368A2
公开(公告)日：2007-11-15
申请号：PCT/US2007/010484
申请日：2007-05-01
申请人： INTEL CORPORATION , BOYANOV, Boyan , HUSSEIN, Makarem, A.
发明人： BOYANOV, Boyan , HUSSEIN, Makarem, A.
CPC分类号： H01L21/76834 , H01L21/7682 , H01L21/76877 , H01L23/5222 , H01L23/53223 , H01L23/53238 , H01L23/53252 , H01L23/53276 , H01L23/53295 , H01L2221/1094 , H01L2924/0002 , H01L2924/00
摘要： A plurality of metal interconnects incorporating dielectric spacers and a method to form such dielectric spacers are described. In one embodiment, the dielectric spacers adjacent to neighboring metal interconnects are discontiguous from one another. In another embodiment, the dielectric spacers may provide a region upon which un-landed vias may effectively land.
摘要翻译：描述了包含电介质间隔体的多个金属互连以及形成这种电介质间隔体的方法。在一个实施例中，与相邻金属互连相邻的电介质间隔物彼此不连续。在另一个实施例中，电介质间隔体可以提供未落地通孔可以有效着落的区域。

9. 发明申请

WO2009158236A2 FORMING ULTRA LOW DIELECTRIC CONSTANT POROUS DIELECTRIC FILMS AND STRUCTURES FORMED THEREBY 审中-公开
标题翻译：形成超低介电常数多孔电介质膜及其形成的结构
公开(公告)号：WO2009158236A2
公开(公告)日：2009-12-30
申请号：PCT/US2009/047467
申请日：2009-06-16
申请人： INTEL CORPORATION , RAMACHANDRARAO, Vijayakumar, S. , KLOSTER, Grant , BOYANOV, Boyan
发明人： RAMACHANDRARAO, Vijayakumar, S. , KLOSTER, Grant , BOYANOV, Boyan
IPC分类号： H01L21/31 , H01L21/205
CPC分类号： H01L21/3105 , Y10T428/249953 , Y10T428/249978
摘要： Methods of forming a microelectronic structure are described. Embodiments of those methods include removing a portion of at least one of Si-C bonds and CHx bonds in a dielectric material comprising a porogen material by reaction with a wet chemical, wherein the portion of Si-C and CHx bonds are converted to Si-H bonds. The Si-H bonds may be further hydrolyzed to form SiOH linkages. The SiOH linkages may then be removed by a radiation based cure, wherein a portion of the porogen material is also removed.
摘要翻译：描述形成微电子结构的方法。这些方法的实施方案包括通过与湿化学品反应除去包含致孔剂材料的电介质材料中的至少一个Si-C键和CHx键的一部分，其中Si-C和CHx键的部分转化为Si- H债券。可以进一步水解Si-H键以形成SiOH键。然后可以通过基于辐射的固化来除去SiOH键，其中一部分致孔剂材料也被除去。

10. 发明申请

WO2006058009A2 USING ZEOLITES TO IMPROVE THE MECHANICAL STRENGHT OF LOW-K INTERLAYER DIELECTRICS 审中-公开
标题翻译：使用ZEOLITES改善低K电介质的机械强度
公开(公告)号：WO2006058009A2
公开(公告)日：2006-06-01
申请号：PCT/US2005/042333
申请日：2005-11-17
申请人： INTEL CORPORATION , BOYANOV, Boyan , KLOSTER, Grant , GOODNER, Michael
发明人： BOYANOV, Boyan , KLOSTER, Grant , GOODNER, Michael
CPC分类号： H01L21/76835 , H01L21/02145 , H01L21/02203 , H01L21/02282 , H01L21/02318 , H01L21/02362 , H01L21/31695 , H01L21/76807 , H01L21/7682 , H01L21/76826 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A method for impregnating the pores of a zeolite low-k dielectric layer with a polymer, and forming an interconnect structure therein, thus mechanically strengthening the dielectric layer and preventing metal deposits within the pores.
摘要翻译：用聚合物浸渍沸石低k电介质层的孔，并在其中形成互连结构的方法，从而机械地增强电介质层并防止孔内的金属沉积。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式