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1. 发明申请

WO2013130088A1 DUAL MODE VOLTAGE REGULATOR WITH RECONFIGURATION CAPABILITY 审中-公开
标题翻译：具有重新配置能力的双模电压稳压器
公开(公告)号：WO2013130088A1
公开(公告)日：2013-09-06
申请号：PCT/US2012/027343
申请日：2012-03-01
申请人： INTEL CORPORATION , COWLEY, Nicholas, P. , TALBOT, Andrew, D. , ALI, Isaac , PINSON, Keith , PERRY, Colin, L. , AITKEN, Matthew, T. , KAN, Chi Man , MUDD, Mark, S. , SPINKS, Stephen, J. , MARTIN, Alan, J. , BARBER, William, L.
发明人： COWLEY, Nicholas, P. , TALBOT, Andrew, D. , ALI, Isaac , PINSON, Keith , PERRY, Colin, L. , AITKEN, Matthew, T. , KAN, Chi Man , MUDD, Mark, S. , SPINKS, Stephen, J. , MARTIN, Alan, J. , BARBER, William, L.
IPC分类号： G05F1/10 , G05F1/565
CPC分类号： H02M3/158 , H02M2001/0032 , H02M2001/0045 , Y02B70/16
摘要： A dual mode voltage regulator according to one embodiment includes a passive regulator circuit, a switching regulator circuit, and a controller circuit configured to determine parameters of an external select input. The controller is configured to selectively couple, on a cold boot up, either the passive regulator circuit or the switching regulator circuit between an input voltage port and an output load based on the determination of parameters.
摘要翻译：根据一个实施例的双模式电压调节器包括无源调节器电路，开关调节器电路和被配置为确定外部选择输入的参数的控制器电路。控制器被配置为基于参数的确定，在冷启动时选择性地将无源调节器电路或开关调节器电路耦合在输入电压端口和输出负载之间。

2. 发明申请

WO2013095514A1 A DUAL MODE VOLTAGE REGULATOR WITH DYNAMIC RECONFIGURATION CAPABILITY 审中-公开
标题翻译：具有动态重构能力的双模电压调节器
公开(公告)号：WO2013095514A1
公开(公告)日：2013-06-27
申请号：PCT/US2011/066866
申请日：2011-12-22
申请人： INTEL CORPORATION , COWLEY, Nicholas P. , TALBOT, Andrew D. , ALI, Isaac , PINSON, Keith , PERRY, Colin L. , AITKEN, Matthew T. , KAN, Chi Man , MUDD, Mark S. , SPINKS, Stephen J. , MARTIN, Alan J. , BARBER, William L.
发明人： COWLEY, Nicholas P. , TALBOT, Andrew D. , ALI, Isaac , PINSON, Keith , PERRY, Colin L. , AITKEN, Matthew T. , KAN, Chi Man , MUDD, Mark S. , SPINKS, Stephen J. , MARTIN, Alan J. , BARBER, William L.
IPC分类号： G05F1/10 , G05F1/575
CPC分类号： H02M3/156 , G05F1/46 , H02M3/158 , H02M2001/0045
摘要： A dual mode voltage regulator according to one embodiment includes a passive regulator circuit; a switching regulator circuit; and a controller circuit configured to monitor operational parameters of the dual mode voltage regulator and selectively couple either the passive regulator circuit or the switching regulator circuit between an input voltage port and an output load. The selective coupling is based on the monitoring of parameters including current through the output load, voltage at the input voltage port and voltage at the output load as well as the availability of a system clock signal.
摘要翻译：根据一个实施例的双模式电压调节器包括无源调节器电路; 开关稳压电路; 以及控制器电路，被配置为监视双模式电压调节器的操作参数，并且在输入电压端口和输出负载之间选择性地耦合无源调节器电路或开关调节器电路。选择耦合是基于对参数的监视，包括输出负载的电流，输入电压端口的电压和输出负载的电压以及系统时钟信号的可用性。

3. 发明申请

WO2012134832A2 COUPLED INDUCTOR TO FACILITATE INTEGRATED POWER DELIVERY 审中-公开
标题翻译：耦合电感器，以便于整合电力输送
公开(公告)号：WO2012134832A2
公开(公告)日：2012-10-04
申请号：PCT/US2012/029348
申请日：2012-03-16
申请人： INTEL CORPORATION , COWLEY, Nicholas P. , ALI, Isaac , SPINKS, Stephen J.
发明人： COWLEY, Nicholas P. , ALI, Isaac , SPINKS, Stephen J.
IPC分类号： H01F17/04 , H01F27/28
CPC分类号： H02M3/1584 , H01F17/02 , Y10T29/49071
摘要： An embodiment of the present invention provides an apparatus, comprising a surface mounted device (SMD) inductor, the SMD inductor including at least two counter wound aircoils formed on a same SMD former; wherein the at least two counter wound aircoils are connected to three terminals on the SMD former, wherein a single terminal is connected to a common node of both windings with two independent terminals accessing the other winding node.
摘要翻译：本发明的一个实施例提供了一种包括表面安装器件（SMD）电感器的器件，该SMD电感器包括形成在同一SMD成形器上的至少两个反绕绕的电极; 其中所述至少两个计数器缠绕的空心体连接到所述SMD形成器上的三个端子，其中单个端子连接到两个绕组的公共节点，其中两个独立的端子接近另一绕组节点。

4. 发明申请

WO2012134832A3 COUPLED INDUCTOR TO FACILITATE INTEGRATED POWER DELIVERY 审中-公开
公开(公告)号：WO2012134832A3
公开(公告)日：2012-10-04
申请号：PCT/US2012/029348
申请日：2012-03-16
申请人： INTEL CORPORATION , COWLEY, Nicholas P. , ALI, Isaac , SPINKS, Stephen J.
发明人： COWLEY, Nicholas P. , ALI, Isaac , SPINKS, Stephen J.
IPC分类号： H01F17/04 , H01F27/28
摘要： An embodiment of the present invention provides an apparatus, comprising a surface mounted device (SMD) inductor, the SMD inductor including at least two counter wound aircoils formed on a same SMD former; wherein the at least two counter wound aircoils are connected to three terminals on the SMD former, wherein a single terminal is connected to a common node of both windings with two independent terminals accessing the other winding node.

5. 发明申请

WO2013158101A1 A SIGNAL AMPLIFIER WITH ACTIVE POWER MANAGEMENT 审中-公开
标题翻译：具有有源电源管理的信号放大器
公开(公告)号：WO2013158101A1
公开(公告)日：2013-10-24
申请号：PCT/US2012/034211
申请日：2012-04-19
申请人： INTEL CORPORATION , COWLEY, Nicholas P. , ALI, Isaac , BARBER, William L.
发明人： COWLEY, Nicholas P. , ALI, Isaac , BARBER, William L.
IPC分类号： H03F1/02 , H04L25/03
CPC分类号： H03F1/0227 , H03F1/3241 , H03F3/195 , H03F3/245 , H03F2200/09 , H03F2200/102 , H03F2200/333 , H03F2200/411 , H03F2200/504 , H03F2200/541 , H03G3/30 , H04L25/0264 , H04L25/0272 , H04L27/361
摘要： A system for amplifying a signal with active power management according to one embodiment includes a first digital to analog converter (DAC) circuit configured to provide a modulated carrier signal; a amplifier circuit coupled to the first DAC, where the amplifier circuit is configured to amplify the modulated carrier signal; an output stage circuit coupled to the amplifier circuit, where the output stage circuit is configured to provide the amplified signal to a network; a second DAC circuit configured to provide a full wave rectified envelope of the modulated carrier signal; and a switching regulator circuit including a voltage reference input coupled to the second DAC circuit, where the switching regulator circuit is configured to provide a supply voltage to the output stage circuit and the supply voltage is modulated in response to the envelope received at the voltage reference input.
摘要翻译：根据一个实施例的用于放大具有有功功率管理的信号的系统包括被配置为提供调制载波信号的第一数模转换器（DAC）电路; 耦合到所述第一DAC的放大器电路，其中所述放大器电路被配置为放大所述经调制的载波信号; 耦合到放大器电路的输出级电路，其中输出级电路被配置为向网络提供放大的信号; 第二DAC电路，被配置为提供调制载波信号的全波整流包络; 以及开关调节器电路，其包括耦合到所述第二DAC电路的电压参考输入，其中所述开关调节器电路被配置为向所述输出级电路提供电源电压，并且响应于在所述电压基准处接收到的信封来调制所述电源电压输入。

6. 发明申请

WO2013165400A1 A SYSTEM FOR ANALOG TO DIGITAL CONVERSION WITH IMPROVED SPURIOUS FREE DYNAMIC RANGE 审中-公开
标题翻译：用于模拟数字转换的系统，具有改进的免费动态范围
公开(公告)号：WO2013165400A1
公开(公告)日：2013-11-07
申请号：PCT/US2012/036009
申请日：2012-05-01
申请人： INTEL CORPORATION , COWLEY, Nicholas P. , ALI, Isaac , BARBER, William L.
发明人： COWLEY, Nicholas P. , ALI, Isaac , BARBER, William L.
IPC分类号： H03M1/12
CPC分类号： H03M1/124 , H03B28/00 , H03H7/01 , H03M1/0626 , H03M1/1215
摘要： Generally, this disclosure describes an apparatus, systems and methods for analog to digital conversion with improved spurious free dynamic range. The system includes a segmented ADC circuit with a plurality of interleaved ADC segments, the segmented ADC circuit configured to generate a digital signal including a channel with an associated channel frequency; a frequency down-converter circuit coupled to the segmented ADC circuit, the frequency down-converter circuit configured to frequency shift the digital signal by a frequency offset; a spur frequency prediction circuit coupled to the frequency down-converter circuit, the spur frequency prediction circuit configured to predict frequencies of spurs generated by the ADC segments, the prediction based on the number of ADC segments and based on the sampling rate of the digital signal; the spur frequency prediction circuit further configured to generate the frequency offset based on the predicted spur frequencies and based on a frequency band of the channel; and a filter circuit coupled to the frequency down-converter circuit, the filter circuit configured to remove one or more of the spurs from the frequency shifted digital signal to generate a filtered signal.
摘要翻译：通常，本公开描述了具有改进的无杂散动态范围的用于模数转换的装置，系统和方法。该系统包括具有多个交错ADC段的分段ADC电路，分段ADC电路被配置为生成包括具有相关信道频率的信道的数字信号; 所述降频转换器电路被耦合到所述分段ADC电路，所述降频转换器电路被配置为使所述数字信号频率偏移频率偏移; 耦合到所述降频转换器电路的杂散频率预测电路，所述杂散频率预测电路被配置为预测由所述ADC段产生的杂散的频率，所述预测基于所述ADC段的数量，并且基于所述数字信号的采样率 ; 所述杂音频率预测电路还被配置为基于所述预测的杂散频率并且基于所述信道的频带来生成所述频率偏移; 以及耦合到所述降频转换器电路的滤波器电路，所述滤波器电路被配置为从所述频移数字信号中去除所述杂波中的一个或多个以产生经滤波的信号。

7. 发明申请

WO2014110315A1 A SUCCESSIVE APPROXIMATION ANALOG-TO-DIGITAL CONVERSION ARCHITECTURAL ARRANGMENT FOR RECEIVERS 审中-公开
标题翻译：接收端的连续逼近模拟到数字转换架构设计
公开(公告)号：WO2014110315A1
公开(公告)日：2014-07-17
申请号：PCT/US2014/010963
申请日：2014-01-10
申请人： INTEL CORPORATION , COWLEY, Nicholas P. , ALI, Isaac , SUETINOV, Viatcheslav I. , PINSON, Keith
发明人： COWLEY, Nicholas P. , ALI, Isaac , SUETINOV, Viatcheslav I. , PINSON, Keith
IPC分类号： H03M1/12
CPC分类号： H03M1/0626 , H03M1/466
摘要： An apparatus and method of successive approximation analog-to-digital conversion for receivers comprising that during a sample mode, connecting an array of capacitors to a plurality of sampling switches coupled to a plurality of amplified input signals, and during a conversion mode, connecting in common the array of capacitors to a comparator and isolating the array of capacitors from the plurality of sampling switches. Additionally, filtering is done by the summation of samples at phase offsets.
摘要翻译：一种用于接收机的逐次逼近模数转换的装置和方法，包括在采样模式期间，将电容器阵列连接到耦合到多个放大输入信号的多个采样开关，并且在转换模式期间，连接到将电容器阵列与比较器共用，并将电容器阵列与多个采样开关隔离。另外，通过相位偏移处的样本的求和来进行滤波。

8. 发明申请

WO2014110314A1 A SUCCESSIVE APPROXIMATION ANALOG-TO-DIGITAL CONVERSION WITH GAIN CONTROL FOR TUNERS 审中-公开
标题翻译：具有调节器增益控制的连续逼近的模拟数字转换
公开(公告)号：WO2014110314A1
公开(公告)日：2014-07-17
申请号：PCT/US2014/010962
申请日：2014-01-10
申请人： INTEL CORPORATION , COWLEY, Nicholas P. , ALI, Isaac , SUETINOV, Viatcheslav I. , PINSON, Keith
发明人： COWLEY, Nicholas P. , ALI, Isaac , SUETINOV, Viatcheslav I. , PINSON, Keith
IPC分类号： G06F17/50
CPC分类号： H03M1/183
摘要： A method and system for implementing a gain control with fine resolution and minimal additional circuitry. The fine digital gain control may be deployed in conjunction with a coarse switched gain at the front end of a sampling receiver. The fine digital gain control mechanism is configured to receive an input signal and moderate gains applied to the received input signal. The output of a low noise amplifier (LNA) is connected to a switched attenuator which provides fine gain stepped gain control. The output of this stage is connected to the switch stage whose output is connected to a charge redistribution successive approximation register digital-to- analog converter (SAR ADC) configured to convert an analog waveform into a digital representation.
摘要翻译：一种用于实现具有精细分辨率和最小额外电路的增益控制的方法和系统。精细的数字增益控制可以结合在采样接收器的前端处的粗略的开关增益来部署。精细数字增益控制机构被配置为接收输入信号并且适中的增益被施加到所接收的输入信号。低噪声放大器（LNA）的输出连接到提供精细增益阶梯增益控制的开关衰减器。该级的输出连接到开关级，其输出端连接到配置为将模拟波形转换为数字表示的电荷再分配逐次逼近寄存器数模转换器（SAR ADC）。

9. 发明申请

WO2011084264A1 EFFICIENT TUNING AND DEMODULATION TECHNIQUES 审中-公开
标题翻译：有效的调谐和解调技术
公开(公告)号：WO2011084264A1
公开(公告)日：2011-07-14
申请号：PCT/US2010/058223
申请日：2010-11-29
申请人： INTEL CORPORATION , COWLEY, Nicholas P. , ARAMBEPOLA, Bernard , MARTIN, Alan J. , ALI, Isaac
发明人： COWLEY, Nicholas P. , ARAMBEPOLA, Bernard , MARTIN, Alan J. , ALI, Isaac
IPC分类号： H04N5/44
CPC分类号： H04N21/42615 , H04H2201/60 , H04N5/50 , H04N5/765 , H04N21/4263 , H04N21/4347 , H04N21/4382 , H04N21/4383 , H04N21/4436
摘要： Techniques for the reception and processing of wireless signals are disclosed. For instance, an apparatus may include multiple receiving paths, a content stream generation module, and a distribution module. The multiple receiving paths include a first receiving path that generates a first decoded signal from an input RF signal in accordance with a first tuning setting. The content stream generation module has first and second inputs. Based on decoded signals received at the first and second inputs, the content stream generation module may generate first and second content streams, respectively. In situations where both the first and second content streams correspond to the first tuning setting, the distribution module provides the first decoded signal to both the first and second inputs of the content stream generation module. Also, a control module may remove operational power from any of the plurality of receiving paths that are currently being unused.
摘要翻译：公开了接收和处理无线信号的技术。例如，设备可以包括多个接收路径，内容流生成模块和分发模块。多个接收路径包括根据第一调谐设置从输入RF信号产生第一解码信号的第一接收路径。内容流生成模块具有第一和第二输入。基于在第一和第二输入处接收到的解码信号，内容流生成模块可以分别生成第一和第二内容流。在第一和第二内容流都对应于第一调谐设置的情况下，分配模块将第一解码信号提供给内容流生成模块的第一和第二输入。此外，控制模块可以从当前未被使用的多个接收路径中的任何一个接收路径移除操作功率。

10. 发明申请

WO2013158104A1 SYSTEM, APPARATUS AND METHOD TO IMPROVE ANALOG-TO-DIGITAL CONVERTER OUTPUT 审中-公开
标题翻译：系统，装置和方法来改进模拟数字转换器输出
公开(公告)号：WO2013158104A1
公开(公告)日：2013-10-24
申请号：PCT/US2012/034237
申请日：2012-04-19
申请人： INTEL CORPORATION , COWLEY, Nicholas P. , ALI, Isaac
发明人： COWLEY, Nicholas P. , ALI, Isaac
IPC分类号： H03M1/12
CPC分类号： H03M1/08 , H03M1/00 , H03M1/0695 , H03M1/1028 , H03M1/12 , H03M1/1215
摘要： According to various embodiments, a system, an apparatus and a method are presented that relate to determining and correcting signal imbalances between output samples of an analog-to-digital (A-D) converter array (that may be implemented as part of a wideband ADC). A statistic module and correction module are associated with the A-D converter array. The statistic module is configured to receive digital samples from the plurality of A-D converters, and generate a statistical sample value for each A-D converter using a set of digital samples received therefrom. The correction module is configured to, for at least one of the plurality of A-D converters, determine an offset value by comparing the statistical sample value for the at least one of the plurality of A-D converters with a reference value, and apply the offset value to a digital sample from that at least one A-D converter to generate a corrected digital sample.
摘要翻译：根据各种实施例，提出了一种涉及确定和校正模数（AD）转换器阵列（可被实现为宽带ADC的一部分）的输出采样之间的信号不平衡的系统，装置和方法，。统计模块和校正模块与A-D转换器阵列相关联。统计模块被配置为从多个A-D转换器接收数字样本，并且使用从其接收的一组数字样本为每个A-D转换器生成统计采样值。校正模块被配置为，对于多个AD转换器中的至少一个，通过将多个AD转换器中的至少一个AD转换器的统计采样值与参考值进行比较来确定偏移值，并将偏移值应用于来自该至少一个AD转换器的数字样本以产生经校正的数字样本。

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