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    • 3. 发明申请
    • A SYSTEM FOR ANALOG TO DIGITAL CONVERSION WITH IMPROVED SPURIOUS FREE DYNAMIC RANGE
    • 用于模拟数字转换的系统,具有改进的免费动态范围
    • WO2013165400A1
    • 2013-11-07
    • PCT/US2012/036009
    • 2012-05-01
    • INTEL CORPORATIONCOWLEY, Nicholas P.ALI, IsaacBARBER, William L.
    • COWLEY, Nicholas P.ALI, IsaacBARBER, William L.
    • H03M1/12
    • H03M1/124H03B28/00H03H7/01H03M1/0626H03M1/1215
    • Generally, this disclosure describes an apparatus, systems and methods for analog to digital conversion with improved spurious free dynamic range. The system includes a segmented ADC circuit with a plurality of interleaved ADC segments, the segmented ADC circuit configured to generate a digital signal including a channel with an associated channel frequency; a frequency down-converter circuit coupled to the segmented ADC circuit, the frequency down-converter circuit configured to frequency shift the digital signal by a frequency offset; a spur frequency prediction circuit coupled to the frequency down-converter circuit, the spur frequency prediction circuit configured to predict frequencies of spurs generated by the ADC segments, the prediction based on the number of ADC segments and based on the sampling rate of the digital signal; the spur frequency prediction circuit further configured to generate the frequency offset based on the predicted spur frequencies and based on a frequency band of the channel; and a filter circuit coupled to the frequency down-converter circuit, the filter circuit configured to remove one or more of the spurs from the frequency shifted digital signal to generate a filtered signal.
    • 通常,本公开描述了具有改进的无杂散动态范围的用于模数转换的装置,系统和方法。 该系统包括具有多个交错ADC段的分段ADC电路,分段ADC电路被配置为生成包括具有相关信道频率的信道的数字信号; 所述降频转换器电路被耦合到所述分段ADC电路,所述降频转换器电路被配置为使所述数字信号频率偏移频率偏移; 耦合到所述降频转换器电路的杂散频率预测电路,所述杂散频率预测电路被配置为预测由所述ADC段产生的杂散的频率,所述预测基于所述ADC段的数量,并且基于所述数字信号的采样率 ; 所述杂音频率预测电路还被配置为基于所述预测的杂散频率并且基于所述信道的频带来生成所述频率偏移; 以及耦合到所述降频转换器电路的滤波器电路,所述滤波器电路被配置为从所述频移数字信号中去除所述杂波中的一个或多个以产生经滤波的信号。