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1. 发明申请

WO2013100958A1 CYCLING ENDURANCE EXTENDING FOR MEMORY CELLS OF A NON-VOLATILE MEMORY ARRAY 审中-公开
标题翻译：对非易失性存储器阵列的存储单元的循环耐久性扩展
公开(公告)号：WO2013100958A1
公开(公告)日：2013-07-04
申请号：PCT/US2011/067558
申请日：2011-12-28
申请人： INTEL CORPORATION , GUO, Xin , PANGAL, Kiran , WAKCHAURE, Yogesh B. , RUBY, Paul D. , KUMAR, Ravi J.
发明人： GUO, Xin , PANGAL, Kiran , WAKCHAURE, Yogesh B. , RUBY, Paul D. , KUMAR, Ravi J.
IPC分类号： G11C16/34 , G11C16/10
CPC分类号： G06F11/1068 , G11C11/5642 , G11C16/06 , G11C16/26 , G11C16/3409
摘要： Examples are disclosed for cycling endurance extending for memory cells of a non-volatile memory array. The examples include implementing one or more endurance extending schemes based on program/erase cycle counts or a failure trigger. The one or more endurance extending schemes may include a gradual read window expansion, a gradual read window shift, an erase blank check algorithm, a dynamic soft-program or a dynamic pre-program.
摘要翻译：公开了用于对非易失性存储器阵列的存储器单元进行扩展的循环耐久性的示例。这些示例包括基于程序/擦除周期计数或故障触发来实现一个或多个耐力扩展方案。一个或多个耐力扩展方案可以包括逐渐读取窗口扩展，逐渐读取窗口移位，擦除空白校验算法，动态软程序或动态预编程。

2. 发明申请

WO2016209542A1 METHOD AND APPARATUS FOR REDUCING READ LATENCY FOR A BLOCK ERASABLE NON-VOLATILE MEMORY 审中-公开
标题翻译：用于减少可擦除非易失性存储器的读取延迟的方法和装置
公开(公告)号：WO2016209542A1
公开(公告)日：2016-12-29
申请号：PCT/US2016/034474
申请日：2016-05-26
申请人： INTEL CORPORATION
发明人： PELSTER, David J. , WAKCHAURE, Yogesh B. , GUO, Xin , RUBY, Paul D. , DAYACAP, Justin R. , DOLLER, Joseph F. , FRICKEY, Robert E.
IPC分类号： G11C16/16 , G11C16/04 , G06F3/06
CPC分类号： G11C16/16 , G11C16/0483 , G11C16/10 , G11C16/26 , G11C16/32 , G11C16/3445 , G11C2216/20
摘要： Provided are an apparatus, memory controller and method for performing a block erase operation with respect to a non-volatile memory. A command is generated to perform a portion of the block erase operation. At least one read or write operation is performed after executing the command. An additional instance of the command is executed in response to determining that the block erase operation did not complete after performing the at least one read or write operation.
摘要翻译：提供了一种用于对非易失性存储器执行块擦除操作的装置，存储器控制器和方法。产生用于执行块擦除操作的一部分的命令。在执行命令后至少执行一次读或写操作。响应于在执行至少一个读或写操作之后确定块擦除操作未完成，执行该命令的附加实例。

3. 发明申请

WO2015009827A1 ERASE MANAGEMENT IN MEMORY SYSTEMS 审中-公开
标题翻译：存储系统中的擦除管理
公开(公告)号：WO2015009827A1
公开(公告)日：2015-01-22
申请号：PCT/US2014/046849
申请日：2014-07-16
申请人： INTEL CORPORATION , WAKCHAURE, Yogesh B. , PELSTER, David J. , GUO, Xin
发明人： WAKCHAURE, Yogesh B. , PELSTER, David J. , GUO, Xin
IPC分类号： G11C16/14 , G11C16/06
CPC分类号： G06F12/0246 , G06F2212/1036 , G06F2212/7204 , G06F2212/7205 , G06F2212/7207 , G06F2212/7208 , G06F2212/7209 , G06F2212/7211 , G11C11/5635 , G11C16/10 , G11C16/102 , G11C16/16 , G11C16/32 , G11C16/349 , G11C16/3495
摘要： Computer processor hardware receives notification that data stored in a region of storage cells in a non-volatile memory system stores invalid data. In response to the notification, the computer processor hardware marks the region as storing invalid data. The computer processor hardware controls the magnitude of erase dwell time (i.e., the amount of time that one or more cells are set to an erased state) associated with overwriting of the invalid data in the storage cells with replacement data. For example, to re-program respective storage cells, the data manager must erase the storage cells and then program the storage cells with replacement data. The data management logic can control the erase dwell time to be less than a threshold time value to enhance a life of the non-volatile memory system.
摘要翻译：计算机处理器硬件接收存储在非易失性存储器系统中的存储单元区域中的数据存储无效数据的通知。响应于该通知，计算机处理器硬件将该区域标记为存储无效数据。计算机处理器硬件控制与用替换数据重写存储单元中的无效数据相关联的擦除驻留时间的大小（即，一个或多个单元被设置为擦除状态的时间量）。例如，为了重新编程各个存储单元，数据管理器必须擦除存储单元，然后用替换数据对存储单元进行编程。数据管理逻辑可以将擦除停留时间控制为小于阈值时间值以增强非易失性存储器系统的寿命。

4. 发明申请

WO2013191898A1 EXTENDED SELECT GATE LIFETIME 审中-公开
标题翻译：扩展选择门锁生命
公开(公告)号：WO2013191898A1
公开(公告)日：2013-12-27
申请号：PCT/US2013/044155
申请日：2013-06-04
申请人： INTEL CORPORATION , WAKCHAURE, Yogesh B. , PANGAL, Kiran , GUO, Xin , MENG, Qingru , BELGAL, Hanmant
发明人： WAKCHAURE, Yogesh B. , PANGAL, Kiran , GUO, Xin , MENG, Qingru , BELGAL, Hanmant
IPC分类号： G11C16/06 , G11C16/14 , G11C16/12
CPC分类号： G11C16/14 , G11C16/0483 , G11C16/06 , G11C16/10 , G11C16/102 , G11C16/16 , G11C16/26 , G11C16/3418 , G11C16/3445 , G11C29/028 , H01L27/115
摘要： A memory device may include two or more memory cells in an integrated circuit, at least one flash cell acting as a select gate coupled to the two or more memory cells, and an interface to accept a select gate erase command and a select gate program command during normal operation of the integrated circuit. The integrated circuit may be capable to perform operations to erase the at least one select gate in response to the select gate erase command, and program the at least one select gate in response to the select gate program command.
摘要翻译：存储器件可以包括集成电路中的两个或更多个存储器单元，用作耦合到两个或更多个存储器单元的选择栅极的至少一个闪存单元以及接受选择栅极擦除命令和选择栅极程序指令的接口在集成电路正常运行期间。集成电路可以执行响应于选择栅极擦除命令擦除至少一个选择栅极的操作，并且响应于选择栅极程序命令编程至少一个选择栅极。

5. 发明申请

WO2017172009A1 METHODS AND APPARATUS TO PERFORM ERASE-SUSPEND OPERATIONS IN MEMORY DEVICES 审中-公开
标题翻译：用于在存储器件中执行擦除 - 暂停操作的方法和设备
公开(公告)号：WO2017172009A1
公开(公告)日：2017-10-05
申请号：PCT/US2017/015381
申请日：2017-01-27
申请人： INTEL CORPORATION
发明人： MADRASWALA, Aliasgar S. , WAKCHAURE, Yogesh B. , JARAMILLO, Camila , BEMALKHEDKAR, Trupti
IPC分类号： G06F3/06
摘要： A disclosed example to use an erase-suspend feature with a memory device includes sending, by a memory host controller, an erase-suspend enable setting and an erase segment duration value to the memory device. The erase-suspend enable setting is to cause the memory device to perform an erase operation as a plurality of erase segments and to suspend the erase operation between the erase segments. The erase segment duration value is to specify a length of time for the erase segments. The memory host controller initiates an erase operation to be performed at the memory device. When the erase operation is suspended, the memory host controller initiates a second memory operation to be performed at the memory device. After the memory host controller determines that the second memory operation is complete, the memory host controller initiates resumption of the erase operation.
摘要翻译：与存储器设备一起使用擦除暂停特征的公开示例包括由存储器主机控制器向存储器设备发送擦除暂停使能设置和擦除段持续时间值。擦除暂停使能设置是使存储器件执行作为多个擦除段的擦除操作并暂停擦除段之间的擦除操作。擦除段持续时间值用于指定擦除段的时间长度。存储器主机控制器启动要在存储器设备上执行的擦除操作。当擦除操作被挂起时，存储器主机控制器启动要在存储器装置处执行的第二存储器操作。内存主控制器确定第二个内存操作完成后，内存主控制器启动恢复擦除操作。

6. 发明申请

WO2017065910A1 METHODS AND APPARATUS TO PRESERVE DATA OF A SOLID STATE DRIVE DURING A POWER LOSS EVENT 审中-公开
标题翻译：用于在电力损失事件期间保存固态驱动器的数据的方法和设备
公开(公告)号：WO2017065910A1
公开(公告)日：2017-04-20
申请号：PCT/US2016/051474
申请日：2016-09-13
申请人： INTEL CORPORATION
发明人： WAKCHAURE, Yogesh B. , MADRASWALA, Aliasgar , KALAVADE, Pranav , GUO, Xin , PELSTER, David , LOEWEN, Myron , ZHU, Feng , WATT, Brennan A.
IPC分类号： G11C11/56 , G06F3/06
CPC分类号： G06F3/0625 , G06F3/0619 , G06F3/065 , G06F3/0688 , G06F12/0811 , G06F2212/283 , G11C7/10 , G11C11/4096 , G11C11/5628 , G11C16/10 , G11C16/225 , G11C2211/5641
摘要： Methods, apparatus, systems and articles of manufacture to preserve data of a solid state drive during a power loss event are disclosed. An example method includes sending, upon detection of the power loss event, from a processor of the solid state drive, a command to abort an ongoing write operation of an aborted memory cell. In response to an indication that the ongoing write operation is aborted, the data to be written to the aborted memory cell is recovered. A first portion of the data to be written to the aborted memory cell is written to a first memory cell. A second portion of the data to be written to the aborted memory cell is written to a second memory cell.
摘要翻译：公开了在电力损失事件期间保存固态驱动器的数据的方法，装置，系统和制造物品。示例性方法包括在检测到功率损失事件时从固态驱动器的处理器发送中止正在中止的存储器单元的正在进行的写入操作的命令。响应于正在进行的写入操作被中止的指示，要被写入中止的存储器单元的数据被恢复。要被写入中止的存储器单元的数据的第一部分被写入第一存储器单元。要被写入中止存储器单元的数据的第二部分被写入第二存储器单元。

7. 发明申请

WO2016048562A1 METHOD AND SYSTEM FOR USING NAND PAGE BUFFERS TO IMPROVE THE TRANSFER BUFFER UTILIZATION OF A SOLID STATE DRIVE 审中-公开
标题翻译：使用NAND缓冲器改善固态驱动器传输缓冲器利用的方法和系统
公开(公告)号：WO2016048562A1
公开(公告)日：2016-03-31
申请号：PCT/US2015/047029
申请日：2015-08-26
申请人： INTEL CORPORATION
发明人： WAKCHAURE, Yogesh B. , PELSTER, David J. , HOFFMAN, Eric L. , GUO, Xin , MADRASWALA, Aliasgar S.
IPC分类号： G06F13/16 , G06F12/02 , G06F12/08
CPC分类号： G06F11/1068 , G06F3/0619 , G06F3/0656 , G06F3/0679 , G06F3/0688 , G06F11/1048 , G06F11/106 , G06F11/1072 , G06F12/0246 , G06F12/0868 , G06F2003/0691 , G06F2212/1016 , G06F2212/202 , G06F2212/2022 , G06F2212/214 , G06F2212/222 , G06F2212/403 , G06F2212/7201 , G06F2212/7203 , G11C11/5628 , G11C11/5642 , G11C16/0483 , G11C29/42 , G11C29/52 , G11C2029/0411 , G11C2211/5641 , G11C2211/5642 , G11C2211/5643 , G11C2211/5648
摘要： A page data (e.g., upper page data) received from a host is stored in a transfer buffer of a controller of a solid state drive. Another page data (e.g., lower page data) is read from a non-volatile memory (e.g., a NAND memory) to store in the transfer buffer as an error corrected page data. The error corrected page data and the page data are written to the non-volatile memory. In additional embodiments, a controller loads a page data (e.g., upper page data) received from the host in one or more NAND page buffers. The controller reads another page data (e.g., lower page data) from a NAND memory to store in a transfer buffer as an error corrected page data. The error corrected page data stored in the transfer buffer is loaded to the one or more NAND page buffers.
摘要翻译：从主机接收的页数据（例如，上页数据）被存储在固态驱动器的控制器的传送缓冲器中。从非易失性存储器（例如，NAND存储器）中读取另一页数据（例如，较低页数据），以作为纠错页数据存储在传送缓冲器中。错误校正的页面数据和页面数据被写入非易失性存储器。在另外的实施例中，控制器在一个或多个NAND页缓冲器中加载从主机接收的页数据（例如，上页数据）。控制器从NAND存储器读取另一个页数据（例如，下页数据），以存储在转移缓冲器中作为纠错页数据。存储在传送缓冲器中的纠错页数据被加载到一个或多个NAND页缓冲器。

8. 发明申请

WO2017052924A1 METHODS AND APPARATUS TO CONFIGURE PERFORMANCE OF A SOLID STATE DRIVE BASED ON HOST WRITE BANDWIDTH 审中-公开
标题翻译：基于HOST写带宽配置固态驱动器的性能的方法和装置
公开(公告)号：WO2017052924A1
公开(公告)日：2017-03-30
申请号：PCT/US2016/048426
申请日：2016-08-24
申请人： INTEL CORPORATION
发明人： WAKCHAURE, Yogesh B. , GUO, Xin , PELSTER, David J. , HOFFMAN, Eric L.
IPC分类号： G06F3/06
CPC分类号： G06F3/061 , G06F3/064 , G06F3/0655 , G06F3/0679 , G06F3/0688 , G06F12/0246 , G06F2212/1016 , G06F2212/7202 , G11C11/5628 , G11C16/0483 , G11C16/10 , G11C16/20 , G11C2211/5641
摘要： An example apparatus includes a non-volatile memory including a first memory having a first write rate and a second memory having a second write rate, the first write rate greater than the second write rate An example controller is to determine, based on a ratio, a first portion of the data to be written to the first memory, and a second portion of the data to be written to the second memory type, the second portion of the data not included in the first portion of the data.
摘要翻译：示例性装置包括非易失性存储器，其包括具有第一写入速率的第一存储器和具有第二写入速率的第二存储器，第一写入速率大于第二写入速率。示例性控制器基于比率来确定，要写入到第一存储器的数据的第一部分和要写入第二存储器类型的数据的第二部分，数据的第二部分不包括在数据的第一部分中。

9. 发明申请

WO2016160162A1 METHOD AND APPARATUS FOR IMPROVING IMMUNITY TO DEFECTS IN A NON-VOLATILE MEMORY 审中-公开
标题翻译：改善非易失性存储器中的缺陷的方法和装置
公开(公告)号：WO2016160162A1
公开(公告)日：2016-10-06
申请号：PCT/US2016/018515
申请日：2016-02-18
申请人： INTEL CORPORATION
发明人： GUO, Xin , ZHU, Feng , WAKCHAURE, Yogesh B. , PELSTER, David J.
IPC分类号： G06F11/10 , G06F12/02
CPC分类号： G06F3/0619 , G06F3/0655 , G06F3/0688 , G06F11/108 , G11C11/005 , G11C16/26 , G11C29/52 , G11C2029/0411
摘要： Methods and apparatus related to a rotated planar XOR scheme for Varied-Sector-Size (VSS) enablement in flat indirection systems are described. In one embodiment, non-volatile memory stores user data in a first set of plurality of planes across a plurality of dies and parity data corresponding to the user data in a second set of plurality of planes. The user data in the first set of the plurality of planes across the plurality of dies and the second set of the plurality of planes is rotated to match a mapping of the parity data. Other embodiments are also disclosed and claimed.
摘要翻译：描述了与扁平间接系统中的不同扇形尺寸（VSS）启用的旋转平面XOR方案相关的方法和装置。在一个实施例中，非易失性存储器将用户数据存储在多个管芯的多个平面的第一组中，并且在第二组多个平面中对应于用户数据的奇偶校验数据。跨越多个管芯的多个平面的第一组中的用户数据和多个平面中的第二组被旋转以匹配奇偶校验数据的映射。还公开并要求保护其他实施例。

10. 发明申请

WO2015048125A1 FLASH MEMORY SYSTEM ENDURANCE IMPROVEMENT USING TEMPERATURE BASED NAND SETTINGS 审中-公开
标题翻译：使用基于温度的NAND设置的闪存存储系统耐久性改进
公开(公告)号：WO2015048125A1
公开(公告)日：2015-04-02
申请号：PCT/US2014/057204
申请日：2014-09-24
申请人： INTEL CORPORATION
发明人： WAKCHAURE, Yogesh B. , PANGAL, Kiran , GUO, Xin
IPC分类号： G11C16/04 , G11C16/06
CPC分类号： G11C16/349 , G11C7/04 , G11C11/5628 , G11C16/26 , G11C16/3454
摘要： Methods and apparatus to improve flash memory system endurance using temperature based flash memory settings are described. In one embodiment, memory controller logic applies one of a first trim profile or a second trim profile to a flash memory storage device based at least partially on a comparison of a threshold temperature value and a sensed temperature of the flash memory storage device. Other embodiments are also disclosed and claimed.
摘要翻译：描述了使用基于温度的闪存设置改善闪存系统耐久性的方法和装置。在一个实施例中，存储器控制器逻辑至少部分地基于阈值温度值和闪速存储器存储设备的感测温度的比较，将闪存存储器件的第一修剪配置文件或第二修剪配置文件中的一个应用于闪速存储器存储设备。还公开并要求保护其他实施例。

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