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1. 发明申请

WO2018063209A1 RESISTIVE RANDOM ACCESS MEMORY CELL 审中-公开
标题翻译：电阻式随机存取存储器单元
公开(公告)号：WO2018063209A1
公开(公告)日：2018-04-05
申请号：PCT/US2016/054305
申请日：2016-09-29
申请人： INTEL CORPORATION
发明人： MAJHI, Prashant , PILLARISETTY, Ravi , KARPOV, Elijah, V. , MUKHERJEE, Niloy , CLARKE, Jame, S.
IPC分类号： H01L45/00 , G11C13/00
CPC分类号： G11C13/003 , G11C13/0002 , G11C13/0069 , G11C2013/0073 , G11C2213/72 , G11C2213/79 , H01L27/2436
摘要： Substrates, assemblies, and techniques for enabling a resistive random access memory cell are disclosed herein. For example, in some embodiments, a device may include a source, where the source includes a source junction, a gate, and a drain, where the drain includes a drain junction and the drain junction is configured to operate as a one transistor, one resistor (1T1R) in a first configuration and as a one diode, one resistor (1D1R) in a second configuration. In an example, during the first configuration the first configuration the drain junction is in reverse bias and has a first junction resistance and during the second configuration, the drain junction is under positive bias and the drain junction has a second junction resistance, wherein the first junction resistance is higher than the second junction resistance.
摘要翻译：本文公开了用于启用电阻随机存取存储器单元的衬底，组件和技术。例如，在一些实施例中，器件可以包括源极，其中源极包括源极结，栅极和漏极，其中漏极包括漏极结并且漏极结配置为作为一个晶体管操作，一个晶体管第一配置中的电阻器（1T1R）以及作为一个二极管，第二配置中的一个电阻器（1D1R）。在一个示例中，在第一配置期间，第一配置中，漏极结处于反向偏置并且具有第一结电阻，并且在第二配置期间，漏极结处于正偏压下并且漏极结具有第二结电阻，其中第一结电阻高于第二结电阻。

2. 发明申请

WO2013154564A1 SELECTOR FOR LOW VOLTAGE EMBEDDED MEMORY 审中-公开
标题翻译：低电压嵌入式存储器的选择器
公开(公告)号：WO2013154564A1
公开(公告)日：2013-10-17
申请号：PCT/US2012/033295
申请日：2012-04-12
申请人： INTEL CORPORATION , KUO, Charles , KARPOV, Elijah, V. , DOYLE, Brian, S. , KENCKE, David, L. , CHAU, Robert, S.
发明人： KUO, Charles , KARPOV, Elijah, V. , DOYLE, Brian, S. , KENCKE, David, L. , CHAU, Robert, S.
IPC分类号： G11C5/02 , G11C5/06 , G11C7/10 , G11C11/15
CPC分类号： H01L43/10 , G11C5/025 , G11C5/063 , G11C8/10 , G11C11/16 , G11C11/1659 , G11C13/003 , G11C2213/15 , G11C2213/71 , H01L43/12
摘要： Techniques, materials, and circuitry are disclosed which enable low-voltage, embedded memory applications. In one example embodiment, an embedded memory is configured with a bitcell having a memory element and a selector element serially connected between an intersection of a wordline and bitline. The selector element can be implemented, for instance, with any number of crystalline materials that exhibit an S-shaped current-voltage (IV) curve, or that otherwise enables a snapback in the selector voltage after the threshold criteria is exceeded. The snapback of the selector is effectively exploited to accommodate the ON-state voltage of the selector under a given maximum supply voltage, wherein without the snapback, the ON-state voltage would exceed that maximum supply voltage. In some example embodiments, the maximum supply voltage is less than 1 volt (e.g., 0.9 volts or less).
摘要翻译：公开了能够实现低电压嵌入式存储器应用的技术，材料和电路。在一个示例实施例中，嵌入式存储器配置有具有存储元件的位单元和串行连接在字线和位线的交叉点之间的选择器元件。选择器元件可以例如用任何数量的表现出S形电流 - 电压（IV）曲线的结晶材料来实现，或者否则在超过阈值标准之后能使得在选择器电压中的回跳。选择器的快速恢复被有效地用于在给定的最大电源电压下适应选择器的导通状态电压，其中在没有快速恢复的情况下，导通状态电压将超过该最大供电电压。在一些示例性实施例中，最大供电电压小于1伏特（例如，0.9伏或更小）。

3. 发明申请

WO2017111831A1 STACKABLE SWITCHING DEVICE 审中-公开
标题翻译：可堆叠切换装置
公开(公告)号：WO2017111831A1
公开(公告)日：2017-06-29
申请号：PCT/US2015/000389
申请日：2015-12-26
申请人： INTEL CORPORATION , KARPOV, Elijah, V. , MAJHI, Prashant , SHAH, Uday , PILLARISETTY, Ravi
发明人： KARPOV, Elijah, V. , MAJHI, Prashant , SHAH, Uday , PILLARISETTY, Ravi
IPC分类号： H01L29/78 , H01L21/336 , H01L27/02
CPC分类号： H01L27/02 , H01L27/2463 , H01L27/2481 , H01L29/76 , H01L29/78 , H01L45/08 , H01L45/1206 , H01L45/1226 , H01L45/145 , H01L45/1675
摘要： Substrates, assemblies, and techniques for enabling a stackable switching device are disclosed herein. For example, in some embodiments, a device may include a source, a drain, and a reaction layer located between the source and the drain. The source, the drain, and the reaction layer can be on top of a support substrate such as a semiconductor substrate and a contact area can modulate the resistance of the reaction layer. In an example, the contact area is a Schottky contact area and the reaction layer is a resistive switching layer.
摘要翻译：本文公开了用于启用可堆叠开关装置的基板，组件和技术。例如，在一些实施例中，器件可以包括源极，漏极和位于源极和漏极之间的反应层。源极，漏极和反应层可以位于诸如半导体衬底之类的支撑衬底的顶部，并且接触区域可以调节反应层的电阻。在一个例子中，接触面积是肖特基接触面积，反应层是电阻切换层。

4. 发明申请

WO2017111851A1 MEMORY CELLS WITH ENHANCED TUNNELING MAGNETORESISTANCE RATIO, MEMORY DEVICES AND SYSTEMS INCLUDING THE SAME 审中-公开
标题翻译：具有增强隧道磁阻率的存储单元，包括相同存储器设备和系统
公开(公告)号：WO2017111851A1
公开(公告)日：2017-06-29
申请号：PCT/US2015/000421
申请日：2015-12-24
申请人： INTEL CORPORATION , DOYLE, Brian, S. , KARPOV, Elijah, V. , OGUZ, Kaan , O'BRIEN, Kevin, P. , KUO, Charles, C. , DOCZY, Mark, L. , SHAH, Uday , WANG, Yih
发明人： DOYLE, Brian, S. , KARPOV, Elijah, V. , OGUZ, Kaan , O'BRIEN, Kevin, P. , KUO, Charles, C. , DOCZY, Mark, L. , SHAH, Uday , WANG, Yih
IPC分类号： H01L43/08 , H01L43/02 , H01L43/12
CPC分类号： H01L43/08 , G11C11/161 , G11C11/1659 , G11C11/1673 , G11C11/1675
摘要： Memory cells with improved tunneling magnetoresistance ratio (TMR) are disclosed. In some embodiments such devices may include a magnetoresistive tunnel junction (MTJ) element coupled in series with a tunneling magnetoresistance enhancement element (TMRE). The MTJ element and TMRE may each be configured to transition between high and low resistance states, e.g., in response to a voltage. In some embodiments, the MTJ and TMRE are configure such that when a read voltage is applied to the cell while the MTJ is in its low resistance state the TMRE is driven to is low resistance state, and when such voltage is applied while the MTJ is in its high resistance state, the TMRE remains in its high resistance state. Devices and systems including such memory cells are also disclosed.
摘要翻译：公开了具有改进的隧道磁阻比（TMR）的存储器单元。在一些实施例中，这种器件可以包括与隧穿磁阻增强元件（TMRE）串联耦合的磁阻隧道结（MTJ）元件。例如，响应于电压，MTJ元件和TMRE均可以被配置为在高电阻状态和低电阻状态之间转换。在一些实施例中，MTJ和TMRE被配置为使得当在MTJ处于其低电阻状态时将读取电压施加到单元时，TMRE被驱动为低电阻状态，并且当MTJ是在其高电阻状态下，TMRE保持高电阻状态。包括这种存储器单元的器件和系统也被公开了。

5. 发明申请

WO2017111829A1 THIN FILM SWITCHING DEVICE 审中-公开
标题翻译：薄膜开关装置
公开(公告)号：WO2017111829A1
公开(公告)日：2017-06-29
申请号：PCT/US2015/000387
申请日：2015-12-26
申请人： INTEL CORPORATION , KARPOV, Elijah, V. , MAJHI, Prashant , DOYLE, Brian, S. , PILLARISETTY, Ravi
发明人： KARPOV, Elijah, V. , MAJHI, Prashant , DOYLE, Brian, S. , PILLARISETTY, Ravi
IPC分类号： H01L29/78 , H01L21/336 , H01L27/02
CPC分类号： H01L27/02 , B82Y10/00 , H01L28/00 , H01L29/0673 , H01L29/0676 , H01L29/1033 , H01L29/401 , H01L29/42364 , H01L29/42392 , H01L29/66439 , H01L29/775 , H01L29/78 , H01L29/84 , H01L49/003
摘要： Substrates, assemblies, and techniques for enabling a thin film switching device are disclosed herein. For example, in some embodiments, an apparatus can include a source, a drain, a transition material located between the source and the drain, and a dielectric layer. The dielectric layer can create stress on the transition material in response to an applied voltage, and the transition material can undergo a change in conductivity in response to the stress.
摘要翻译：本文公开了用于启用薄膜开关器件的衬底，组件和技术。例如，在一些实施例中，装置可以包括源极，漏极，位于源极和漏极之间的过渡材料以及介电层。响应于施加的电压，介电层可以在过渡材料上产生应力，并且过渡材料可以响应于应力而经历电导率的变化。

6. 发明申请

WO2019139622A1 FERROELECTRIC FIELD-EFFECT TRANSISTORS FOR 3D MEMORY ARRAYS AND METHODS OF MANUFACTURING THE SAME 审中-公开
公开(公告)号：WO2019139622A1
公开(公告)日：2019-07-18
申请号：PCT/US2018/013604
申请日：2018-01-12
申请人： INTEL CORPORATION
发明人： MAJHI, Prashant , KARPOV, Elijah, V. , DOYLE, Brian, S. , SHARMA, Abhishek, A. , PILLARISETTY, Ravi
IPC分类号： H01L27/11514 , H01L27/11507 , H01L27/11509 , H01L27/11512 , H01L21/28
摘要： Methods, apparatus, systems and articles of manufacture are disclosed for a gate all around ferroelectric material field-effect transistor. Examples include a ferroelectric memory device that includes a semiconductor substrate, a semiconductor rod extending in an elongate direction substantially parallel to the semiconductor substrate, a ferroelectric gate insulator coating the semiconductor rod and a gate conductor adjacent the semiconductor rod, the ferroelectric gate insulator positioned between the gate conductor and the semiconductor rod.

7. 发明申请

WO2017111844A1 MEMORY DEVICES INCLUDING INTEGRATED TUNNEL DIODE IN CONTACT AND TECHNIQUES FOR FORMING SAME 审中-公开
标题翻译：包括集成的隧道二极管在内的存储器件以及形成相同的技术
公开(公告)号：WO2017111844A1
公开(公告)日：2017-06-29
申请号：PCT/US2015/000403
申请日：2015-12-24
申请人： INTEL CORPORATION
发明人： PILLARISETTY, Ravi , MAJHI, Prashant , MUKHERJEE, Niloy , KARPOV, Elijah, V. , SHAH, Uday
IPC分类号： H01L27/115 , H01L21/8247
CPC分类号： H01L27/11582 , H01L28/00
摘要： Techniques are disclosed for integrating a tunnel diode in a 1T-1 R resistive random-access memory (RRAM) cell. The tunnel diode can be connected in series with the RRAM cell, so as to provide current control. The diode's p-n junction can be formed, for example, using the source/drain material and an additional diode material layer there over, which may be, for example, an epitaxial p-type or n-type material doped opposite the underlying source/drain material. A source contact and the source portion may be electronically contacted through the diode portion. The P+/N+ tunnel diode provided by the source portion and diode portion may provide a negative differential resistance (NDR) that serves to clamp current and protect against overshoot during the RRAM device's FORMING and SET operations, reducing RRAM filament damage. In some cases, the tunnel diode may be configured to provide high conductance in an opposite polarity during the RRAM device's RESET operation.
摘要翻译：公开了用于在1T-1R电阻式随机存取存储器（RRAM）单元中集成隧道二极管的技术。隧道二极管可以与RRAM单元串联连接，以提供电流控制。二极管的pn结可以例如使用源极/漏极材料和其上的附加二极管材料层形成，其可以是例如与下面的源极/漏极相对地被掺杂的外延p型或n型材料材料。源极触点和源极部分可以通过二极管部分电子接触。由源极部分和二极管部分提供的P + / N +隧道二极管可提供负差分电阻（NDR），用于钳位电流并防止RRAM器件的FORMING和SET操作期间的过冲，从而减少RRAM灯丝损坏。在一些情况下，隧道二极管可以被配置为在RRAM器件的RESET操作期间以相反的极性提供高电导。

8. 发明申请

WO2017111776A1 NON-VOLATILE MEMORY DEVICES INCLUDING INTEGRATED BALLAST RESISTOR 审中-公开
标题翻译：非易失性存储器设备，包括集成镇流器
公开(公告)号：WO2017111776A1
公开(公告)日：2017-06-29
申请号：PCT/US2015/000233
申请日：2015-12-23
申请人： INTEL CORPORATION
发明人： MAJHI, Prashant , KARPOV, Elijah, V. , PILLARISETTY, Ravi , SHAH, Uday , MUKHERJEE, Niloy
IPC分类号： H01L45/02 , H01L45/00
CPC分类号： H01L45/146 , H01L27/2481 , H01L45/08
摘要： A non-volatile memory device is disclosed, in which a ballast resistor layer is disposed between the selector element and memory element of a given memory cell of the device. The material composition of the ballast resistor can be customized, as desired, and in some cases may be, for example, a sub-stoichiometric oxide of hafnium oxide (HfO x ), tantalum oxide (TaO x ), or titanium dioxide (TiO x ), or an alloy of any thereof. In accordance with some embodiments, the integrated ballast resistor may serve the function of damping current surge related to the snapback characteristics of the selector element, preserving control of memory element switching. In accordance with some embodiments, an integrated ballast resistor layer provided as described herein may be implemented, for example, in any of a wide range of resistive random-access memory (RRAM) architectures and spin-transfer torque magnetic random-access memory (STTMRAM) architectures, including cross-point implementations of these types of architectures.
摘要翻译：公开了一种非易失性存储器件，其中镇流电阻器层设置在设备的给定存储器单元的选择器元件和存储器元件之间。根据需要，镇流电阻器的材料组成可以定制，并且在一些情况下可以是例如氧化铪（HfO x：），氧化钽（TaO x或者二氧化钛（TiO x），或者它们中的任何一种的合金。根据一些实施例，集成镇流电阻器可以起到抑制与选择器元件的骤回特性相关的电流浪涌的功能，保持对存储器元件切换的控制。根据一些实施例，可以例如在宽范围的电阻随机存取存储器（RRAM）体系结构和自旋转移力矩磁随机存取存储器（STTMRAM）中的任何一个中实现如本文所述提供的集成镇流器电阻器层）体系结构，包括这些类型体系结构的交叉点实现。

9. 发明申请

WO2015147801A8 TECHNIQUES FOR FORMING NON-PLANAR RESISTIVE MEMORY CELLS 审中-公开
公开(公告)号：WO2015147801A8
公开(公告)日：2015-10-01
申请号：PCT/US2014/031735
申请日：2014-03-25
申请人： INTEL CORPORATION , MAJHI, Prashant , KARPOV, Elijah, V. , SHAH, Uday , MUKHERJEE, Niloy , KUO, Charles, C. , PILLARISETTY, Ravi , DOYLE, Brian, S. , CHAU, Robert, S.
发明人： MAJHI, Prashant , KARPOV, Elijah, V. , SHAH, Uday , MUKHERJEE, Niloy , KUO, Charles, C. , PILLARISETTY, Ravi , DOYLE, Brian, S. , CHAU, Robert, S.
IPC分类号： H01L27/115 , H01L21/8247
摘要： Techniques are disclosed for forming non-planar resistive memory cells, such as non-planar resistive random-access memory (ReRAM or RRAM) cells. The techniques can be used to reduce forming voltage requirements and/or resistances involved (such as the resistance during the low-resistance state) relative to planar resistive memory cells for a given memory cell space. The non-planar resistive memory cell includes a first electrode, a second electrode, and a switching layer disposed between the first and second electrodes. The second electrode may be substantially between opposing portions of the switching layer, and the first electrode may be substantially adjacent to at least two sides of the switching layer, after the non-planar resistive memory cell is formed. In some cases, an oxygen exchange layer (OEL) may be disposed between the switching layer and one of the first and second electrodes to, for example, increase flexibility in incorporating materials in the cell.

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