专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

WO2014110050A1 MEMORY DEVICE HAVING AN ADAPTABLE NUMBER OF OPEN ROWS 审中-公开
标题翻译：具有适应性开放数量的存储设备
公开(公告)号：WO2014110050A1
公开(公告)日：2014-07-17
申请号：PCT/US2014/010544
申请日：2014-01-07
申请人： QUALCOMM INCORPORATED
发明人： SHEN, Jian , WANG, Liyong , CHUA-EOAN, Lew
IPC分类号： G11C7/10 , G11C11/408 , G11C11/4093
CPC分类号： G11C8/18 , G06F3/0604 , G06F3/0638 , G06F3/0653 , G06F3/0673 , G06F12/0215 , G06F12/0802 , G06F12/0862 , G06F12/10 , G06F13/1689 , G06F2212/1016 , G06F2212/60 , G11C7/1039 , G11C8/06 , G11C8/10 , G11C11/4082 , G11C11/4093
摘要： A memory device comprises a memory array, at least one row address buffer, a set of row data buffers, a row decoder, an array of sense amplifiers, and a demultiplexer. The memory array comprises data elements organized into rows and columns. Each of the rows is addressable by a row address. Each of the data elements in each of the rows is addressable by a column address. The at least one row address buffer holds a selected row address of a set of successive selected row addresses. The set of row data buffers holds respective contents of selected rows that correspond to the set of successive selected row addresses. The row decoder decodes the selected row address to access a selected row. The array of sense amplifier reads the selected row and transmits content of the selected row to one of the row data buffers through the demultiplexer, and writes the content of the selected row back to the selected row.
摘要翻译：存储器件包括存储器阵列，至少一个行地址缓冲器，一组行数据缓冲器，行解码器，读出放大器阵列和解复用器。存储器阵列包括组织成行和列的数据元素。每行都可以通过行地址寻址。每行中的每个数据元素都可以通过列地址进行寻址。至少一个行地址缓冲器保存一组连续选择的行地址的所选行地址。行数据缓冲器集合保持与所选择的一组连续的行地址对应的所选行的各个内容。行解码器解码所选择的行地址以访问所选行。读出放大器的阵列通过解复用器读取所选择的行并将所选行的内容发送到行数据缓冲器中的一个，并将所选行的内容写回所选行。

2. 发明申请

WO2014070129A2 MANAGING AN ANALYTIC FUNCTION TO BE PERFORMED ON DATA STORED IN AN INPUT BLOCK 审中-公开
标题翻译：在输入块中存储数据时管理分析功能
公开(公告)号：WO2014070129A2
公开(公告)日：2014-05-08
申请号：PCT/US2012040767
申请日：2012-06-04
申请人： HEWLETT PACKARD DEVELOPMENT CO , CHAO NEIL EARNEST , FAN HONGMIN
发明人： CHAO NEIL EARNEST , FAN HONGMIN
IPC分类号： G06F13/14 , G06F12/00
CPC分类号： G06F3/0647 , G06F3/0623 , G06F3/067 , G06F3/0676 , G06F5/00 , G06F12/0215 , G06F12/0253 , G06F12/0623 , G06F12/0676
摘要： In an example, an analytic function to be performed on data stored in an input block is managed through an interface to a framework through which a user is to define the analytic function. The framework is to buffer batches of the data into a memory through implementation of a Reader, a Writer, a PreReader, and a PreWriter on the data stored in the input block when the user-defined analytic function is performed, and wherein the Reader, the Writer, the PreReader, and the PreWriter are individually movable with respect to each other in the input block. In addition, the user-defined analytic function is received through the interface.
摘要翻译：在一个示例中，要对存储在输入块中的数据执行的分析功能通过用户要定义分析功能的框架的接口来管理。该框架通过在执行用户定义的分析功能时对存储在输入块中的数据执行读取器，写入器，预读器和预写器来将批量数据缓存到存储器中，并且其中读取器，写入器，预读器和预写器在输入块中可相对于彼此单独移动。另外，用户定义的分析功能通过接口接收。

3. 发明申请

WO2012069874A1 INTEGRATED CIRCUIT DEVICE, SIGNAL PROCESSING SYSTEM AND METHOD FOR PREFETCHING LINES OF DATA THEREFOR 审中-公开
标题翻译：集成电路设备，信号处理系统及其数据线的预编译方法
公开(公告)号：WO2012069874A1
公开(公告)日：2012-05-31
申请号：PCT/IB2010/055334
申请日：2010-11-22
申请人： FREESCALE SEMICONDUCTOR, INC. , ROBERSTON, Alistair , MAIOLANI, Mark
发明人： ROBERSTON, Alistair , MAIOLANI, Mark
IPC分类号： G06F9/312 , G06F3/06
CPC分类号： G06F12/0215 , G06F9/3802 , G06F9/3816 , G06F12/0246 , G06F12/0862 , G06F2212/17 , G06F2212/2022 , G06F2212/6022
摘要： An integrated circuit device (105) comprising at least one prefetching module (140) for prefetching lines of data (250) from at least one memory element (150). The prefetching module (140) is configured to determine a position of a requested block of data (305) within a respective line of data (300) of the at least one memory element (150), determine a number (n) of subsequent lines of data (250) to prefetch, based at least partly on the determined position of the requested block of data (305) within the respective line of data (300) of the at least one memory element (150), and cause the prefetching of n successive lines of data (250) from the at least one memory element (150).
摘要翻译：一种集成电路装置（105），包括用于从至少一个存储元件（150）预取数据线（250）的至少一个预取模块（140）。预取模块（140）被配置为确定所请求的数据块（305）在所述至少一个存储元件（150）的相应数据线（300）内的位置，确定后续行数（n）至少部分地基于在所述至少一个存储元件（150）的相应数据线（300）内的所请求的数据块（305）的确定的位置来预取数据（250），并且使得来自至少一个存储元件（150）的n个连续数据行（250）。

4. 发明申请

WO2010108096A3 MEMORY ACCESS CONTROLLER, SYSTEMS, AND METHODS FOR OPTIMIZING MEMORY ACCESS TIMES 审中-公开
标题翻译：存储器访问控制器，系统和优化存储器访问时间的方法
公开(公告)号：WO2010108096A3
公开(公告)日：2011-01-13
申请号：PCT/US2010027981
申请日：2010-03-19
申请人： QUALCOMM INC , MADDALI SRINIVAS , SRIRAMAGIRI DEEPTI VIJAYALAKSHMI
发明人： MADDALI SRINIVAS , SRIRAMAGIRI DEEPTI VIJAYALAKSHMI
IPC分类号： G06F13/16 , G06F12/06 , G06F12/08
CPC分类号： G11C11/4085 , G06F12/0215 , G06F12/0607 , G06F12/0623 , G06F13/1694
摘要： A configurable memory access controller and related systems and methods. In embodiments described herein, the configurable memory controller is adapted to provide a separate memory access configuration for each of a plurality of memory banks in a given memory system. The memory access configuration provided for each memory bank can either be to leave open or close at least one memory page in each memory bank. In this manner, a memory access configuration can be provided for each memory bank on an individualized basis to optimize memory access times based on the type of data activity in each memory bank. In embodiments described herein, the memory controller can also be configured to allow for dynamic configuration of one or more memory banks. Dynamic configuration involves changing or overriding the memory access configuration for a particular memory bank to optimize memory access times.
摘要翻译：可配置的存储器访问控制器及相关系统和方法。在本文描述的实施例中，可配置存储器控制器适于为给定存储器系统中的多个存储器组中的每一个提供单独的存储器访问配置。为每个存储体提供的存储器访问配置可以是在每个存储体中保持打开或关闭至少一个存储器页。以这种方式，可以基于个别的基础为每个存储体提供存储器访问配置，以基于每个存储体中的数据活动的类型优化存储器访问时间。在这里描述的实施例中，存储器控制器还可以被配置为允许一个或多个存储体的动态配置。动态配置涉及更改或覆盖特定存储库的存储器访问配置，以优化存储器访问时间。

5. 发明申请

WO2010108096A2 MEMORY ACCESS CONTROLLER, SYSTEMS, AND METHODS FOR OPTIMIZING MEMORY ACCESS TIMES 审中-公开
标题翻译：存储器访问控制器，系统和优化存储器访问时间的方法
公开(公告)号：WO2010108096A2
公开(公告)日：2010-09-23
申请号：PCT/US2010/027981
申请日：2010-03-19
申请人： QUALCOMM INCORPORATED , MADDALI, Srinivas , SRIRAMAGIRI, Deepti, Vijayalakshmi
发明人： MADDALI, Srinivas , SRIRAMAGIRI, Deepti, Vijayalakshmi
IPC分类号： G06F13/16 , G06F12/06 , G06F12/08
CPC分类号： G11C11/4085 , G06F12/0215 , G06F12/0607 , G06F12/0623 , G06F13/1694
摘要： A configurable memory access controller and related systems and methods. In embodiments described herein, the configurable memory controller is adapted to provide a separate memory access configuration for each of a plurality of memory banks in a given memory system. The memory access configuration provided for each memory bank can either be to leave open or close at least one memory page in each memory bank. In this manner, a memory access configuration can be provided for each memory bank on an individualized basis to optimize memory access times based on the type of data activity in each memory bank. In embodiments described herein, the memory controller can also be configured to allow for dynamic configuration of one or more memory banks. Dynamic configuration involves changing or overriding the memory access configuration for a particular memory bank to optimize memory access times.
摘要翻译：可配置的存储器访问控制器及相关系统和方法。在本文描述的实施例中，可配置存储器控制器适于为给定存储器系统中的多个存储器组中的每一个提供单独的存储器访问配置。为每个存储体提供的存储器访问配置可以是在每个存储体中保持打开或关闭至少一个存储器页。以这种方式，可以基于个别的基础为每个存储体提供存储器访问配置，以基于每个存储体中的数据活动的类型优化存储器访问时间。在这里描述的实施例中，存储器控制器还可以被配置为允许一个或多个存储体的动态配置。动态配置涉及更改或覆盖特定存储库的存储器访问配置，以优化存储器访问时间。

6. 发明申请

WO2004102403A3 A SYSTEM INCLUDING A HOST CONNECTED TO A PLURALITY OF MEMORY MODULES VIA A SERIAL MEMORY INTERCONNECT 审中-公开
标题翻译：包括通过串行存储器互连连接到多个存储器模块的主机的系统
公开(公告)号：WO2004102403A3
公开(公告)日：2005-08-25
申请号：PCT/US2004014441
申请日：2004-05-10
申请人： ADVANCED MICRO DEVICES INC , POLZIN R STEPHEN , WEBER FREDERICK D , TALBOT GERALD R , HEWITT LARRY D , REEVES RICHARD W , PATEL SHWETAL A , LA FETRA ROSS V , GULICK DALE E , HUMMEL MARK D , MIRANDA PAUL C
发明人： POLZIN R STEPHEN , WEBER FREDERICK D , TALBOT GERALD R , HEWITT LARRY D , REEVES RICHARD W , PATEL SHWETAL A , LA FETRA ROSS V , GULICK DALE E , HUMMEL MARK D , MIRANDA PAUL C
IPC分类号： G06F12/00 , G06F13/16 , G06F13/28 , G11C5/00 , G06F13/42
CPC分类号： G06F13/4243 , G06F12/0215 , G06F12/0862 , G06F13/1626 , G06F2212/6022
摘要： A system (50) including a host (100) coupled to a serially connected chain of memory modules (150A-B). In one embodiment, each of the memory modules includes a memory control hub (160) for controlling access to a plurality of memory chips (261) on the memory module. The memory modules are coupled serially in a chain to the host via a plurality of memory links (110). Each memory link may include an uplink (211) for conveying transactions toward the host and a downlink (212) for conveying transactions originating at the host to a next memory module in the chain. The uplink and the downlink may convey transactions using packets that include control and configuration packets and memory access packets. The memory control hub may convey a transaction received on a first downlink of a first memory link on a second downlink of a second memory link independent of decoding the transaction.
摘要翻译：一种系统（50），包括耦合到串行连接的存储器模块链（150A-B）的主机（100）。在一个实施例中，每个存储器模块包括用于控制对存储器模块上的多个存储器芯片（261）的访问的存储器控制集线器（160）。存储器模块通过多个存储器链路（110）以链式串行耦合到主机。每个存储器链路可以包括用于向主机传送事务的上行链路（211）和用于将在主机处发起的事务传送到链路中的下一个存储器模块的下行链路（212）。上行链路和下行链路可以使用包括控制和配置分组和存储器访问分组的分组来传送事务。存储器控制集线器可以在第二存储器链路的第二下行链路上传送在第一存储器链路的第一下行链路上接收的事务，而与解码事务无关。

7. 发明申请

WO2003083661A1 MEMORY-ACCESS MANAGEMENT METHOD AND SYSTEM FOR SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY OR THE LIKE 审中-公开
标题翻译：用于同步动态随机存取存储器的存储器访问管理方法和系统
公开(公告)号：WO2003083661A1
公开(公告)日：2003-10-09
申请号：PCT/CN2003/000223
申请日：2003-03-27
申请人： VIA TECHNOLOGIES, INC.
发明人： LAI, Jiin , KAO, Chihkuo
IPC分类号： G06F12/00
CPC分类号： G06F12/0895 , G06F12/0215 , G06F12/123
摘要： A memory-access management method and system is provided for use with an DRAM (Dynamic Random-Access Memory) or the like, for the purpose of increasing the performance of memory access to the SDRAM by means of tracking the memory-access history of previous access operations. The memory-page management system has a managing device for managing the N memory pages. According to the embodiment, the managing device further comprises a page register unit. The page register unit is used for storing K storage units, each of which stores an address data of the memory page. The utilization-rate register unit is coupled to the page register circuit, and used for monitoring utilizations of the storage units. In practical design, the number K of the storage units can be designed to be less than the number N of the memory pages.
摘要翻译：提供了与DRAM（动态随机存取存储器）等一起使用的存储器访问管理方法和系统，用于通过跟踪先前的存储器访问历史来增加对SDRAM的存储器访问的性能访问操作。内存页管理系统具有用于管理N个内存页的管理装置。根据实施例，管理装置还包括页寄存器单元。页面寄存器单元用于存储K个存储单元，每个存储单元存储存储器页面的地址数据。利用率寄存器单元耦合到页寄存器电路，并用于监视存储单元的利用率。在实际设计中，存储单元的数量K可以设计成小于存储器页数N。

8. 发明申请

WO2003058456A1 METHOD FOR DYNAMICALLY ADJUSTING A MEMORY PAGE CLOSING POLICY 审中-公开
标题翻译：用于动态调整存储器关闭策略的方法
公开(公告)号：WO2003058456A1
公开(公告)日：2003-07-17
申请号：PCT/US2002/041550
申请日：2002-12-27
申请人： INTEL CORPORATION
发明人： KHAN, Opher, D. , WILCOX, Jeffrey, R.
IPC分类号： G06F12/02
CPC分类号： G06F12/0215
摘要： A method for dynamically adjusting a memory page-closing policy for computer systems employing various types of DRAM memory partitioned into one or more memory banks, and circuitry for implementing the method. In general, the method comprises monitoring memory accesses to memory banks and dynamically adjusting the memory page closing policy for those memory bank based on locality characteristics of its memory accesses so that memory latencies are reduced. In one embodiment, in response to memory requests from a computer system processor, memory accesses to the DRAM memory are made on a page-wise basis. As each memory page is accessed, a page-miss, page-hit or page-hit state is produced. Depending on the page access states, which generally will reflect the locality characteristics of (an) application(s) accessing the memory, a page-close set point is adjusted. When a timing count corresponding to the page exceeds the page-close set point, the memory page is closed.
摘要翻译：一种用于动态调整采用划分成一个或多个存储体的各种类型的DRAM存储器的计算机系统的存储器页面关闭策略的方法，以及用于实现该方法的电路。通常，该方法包括监视对存储体的存储器访问，并且基于其存储器访问的位置特性动态地调整针对那些存储体的存储器页面关闭策略，从而减少存储器延迟。在一个实施例中，响应于来自计算机系统处理器的存储器请求，在逐页的基础上进行对DRAM存储器的存储器访问。当访问每个内存页面时，会产生页面错失，页面命中或页面命中状态。根据通常将反映访问存储器的（a）应用程序的位置特性的页面访问状态，调整页面设置点。当与页面相对应的定时计数超过页面关闭设置点时，内存页面被关闭。

9. 发明申请

WO2002079994A2 MEMORY CONTROL SYSTEM WITH INCREMENTER FOR GENERATING SPECTULATIVE ADDRESSES 审中-公开
标题翻译：具有增强器的存储器控制系统用于生成地址
公开(公告)号：WO2002079994A2
公开(公告)日：2002-10-10
申请号：PCT/IB2002/000800
申请日：2002-03-15
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V.
发明人： BAO, Liewei
IPC分类号： G06F12/02
CPC分类号： G06F12/0215
摘要： A memory controller includes an incrementer for predicting a next address to be asserted by a processor. The incrementer, structurally a counter, is configurable to wrap at a wrap boundary and to indicate when a predicted address crosses a page boundary if the memory is in page mode. This incrementer provides accurate predictions even where successor addresses are on different pages or, in the case of address loops, even in some cases in which the successor address is not consecutive. Thus, the number of accurate address predictions is increased, enhancing overall performance. The invention has particular applicability to signal processing applications with instructions loops that cross one or more page boundaries.
摘要翻译：存储器控制器包括用于预测由处理器断言的下一个地址的增量器。增量器，结构上是一个计数器，可配置为在包装边界包装，并指示当存储器处于页面模式时，预测地址何时跨越页面边界。即使在后续地址在不同的页面上，或者在地址循环的情况下，即使在某些情况下，后继地址不是连续的，该增量器也提供准确的预测。因此，准确地址预测的数量增加，从而提高整体性能。本发明特别适用于具有跨越一个或多个页面边界的指令循环的信号处理应用。

10. 发明申请

WO0188717A3 SYSTEM AND METHOD FOR USING A PAGE TRACKING BUFFER TO REDUCE MAIN MEMORY LATENCY IN A COMPUTER SYSTEM 审中-公开
标题翻译：使用页面跟踪缓冲器来减少计算机系统中的主存储器延迟的系统和方法
公开(公告)号：WO0188717A3
公开(公告)日：2002-03-21
申请号：PCT/US0113272
申请日：2001-04-24
申请人： SUN MICROSYSTEMS INC
发明人： CHERABUDDI RAJASEKHAR , NORMOYLE KEVIN , MCGEE BRIAN
IPC分类号： G06F12/02
CPC分类号： G06F12/0215
摘要： A memory controller for a memory subsystem of a computer system connects to a processor bus. The memory controller is for use with memory devices such as RDRAM or DDR SDRAM that allow for multiple open pages. Memory references are remapped by an address mapper (400) and processed by a page tracking buffer (402) to keep track of open pages in the memory devices. The controller also has a state machine (420), and an interface to memory devices (422). The page tracking buffer (402) has a row address content addressable memory (410) for determining when a reference is in an open page, and a bank content addressable memory (408) for determining when a reference is to the same bank as an open page. The controller closes open pages of a bank prior to opening new pages in that bank. The page tracking buffer (402) has fewer lines than the product of the maximum number of memory devices times the maximum number of simultaneously open pages of each device, but provides for tracking any page of any of the memory devices.
摘要翻译：用于计算机系统的存储器子系统的存储器控制器连接到处理器总线。内存控制器可用于允许多个打开页面的存储设备，如RDRAM或DDR SDRAM。存储器引用由地址映射器（400）重新映射，并由页面跟踪缓冲器（402）处理，以跟踪存储器件中的打开的页面。控制器还具有状态机（420）和与存储器件（422）的接口。页面跟踪缓冲器（402）具有用于确定何时引用位于打开页面中的行地址内容可寻址存储器（410），以及用于确定何时将引用作为打开的同一个存储体的引用的存储体内容可寻址存储器（408）页。在该银行开设新页面之前，控制器关闭银行的开放页面。页面跟踪缓冲器（402）具有比存储器设备的最大数量乘以每个设备的同时打开页面的最大数量的乘积更少的行，但是提供跟踪任何存储器设备的任何页面。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式