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1. 发明申请

WO2004040668A3 FIELD EFFECT TRANSISTOR ASSEMBLY AND AN INTEGRATED CIRCUIT ARRAY 审中-公开
标题翻译：场效应晶体管布局和电路阵列
公开(公告)号：WO2004040668A3
公开(公告)日：2004-07-08
申请号：PCT/DE0303612
申请日：2003-10-30
申请人： INFINEON TECHNOLOGIES AG , GRAHAM ANDREW , HOFMANN FRANZ , HOENLEIN WOLFGANG , KRETZ JOHANNES , KREUPL FRANZ , LANDGRAF ERHARD , LUYKEN RICHARD JOHANNES , ROESNER WOLFGANG , SCHULZ THOMAS , SPECHT MICHAEL
发明人： GRAHAM ANDREW , HOFMANN FRANZ , HOENLEIN WOLFGANG , KRETZ JOHANNES , KREUPL FRANZ , LANDGRAF ERHARD , LUYKEN RICHARD JOHANNES , ROESNER WOLFGANG , SCHULZ THOMAS , SPECHT MICHAEL
IPC分类号： G11C13/02 , H01L29/78 , H01L51/00 , H01L51/30 , H01L51/20
CPC分类号： G11C13/025 , B82Y10/00 , G11C2213/17 , H01L27/283 , H01L51/0048 , H01L51/0052 , H01L51/0512
摘要： The invention relates to a field effect transistor assembly and an integrated circuit array. The field effect transistor assembly contains a substrate, a first wiring plane with a first source/drain region on the substrate and a second wiring plane with a second source/drain region above the first wiring plane. The field effect transistor assembly also comprises at least one vertical nanoelement as a channel region, which is situated between and coupled to both wiring planes. The nanoelement is at least partially surrounded by electrically conductive material, forming a gate region, whereby electrically insulating material is provided between the nanoelement and the electrically conductive material to act as a gate insulating layer.
摘要翻译：本发明涉及一种场效应晶体管装置和一种电路阵列。场效应晶体管装置包括衬底，在衬底上具有第一源极/漏极区域的第一布线平面以及在第一布线平面上具有第二源极/漏极区域的第二布线平面。此外，场效应晶体管装置包含至少一个垂直纳米元件作为沟道区域，其布置在布线平面之间并耦合到两者。纳米元件至少部分地由导电材料包围的栅极区域，所述电绝缘材料作为纳米元件和所述导电材料之间的栅绝缘层提供。

2. 发明申请

WO2004040644A3 MEMORY CELL, MEMORY CELL ARRANGEMENT, STRUCTURING ARRANGEMENT AND METHOD FOR PRODUCTION OF A MEMORY CELL 审中-公开
标题翻译：存储单元中，存储器单元装置，纹理安排及其制造方法的存储单元
公开(公告)号：WO2004040644A3
公开(公告)日：2004-08-12
申请号：PCT/DE0303589
申请日：2003-10-29
申请人： INFINEON TECHNOLOGIES AG , GRAHAM ANDREW , HOFMANN FRANZ , HOENLEIN WOLFGANG , KRETZ JOHANNES , KREUPL FRANZ , LANDGRAF ERHARD , LUYKEN RICHARD JOHANNES , ROESNER WOLFGANG , SCHULZ THOMAS , SPECHT MICHAEL
发明人： GRAHAM ANDREW , HOFMANN FRANZ , HOENLEIN WOLFGANG , KRETZ JOHANNES , KREUPL FRANZ , LANDGRAF ERHARD , LUYKEN RICHARD JOHANNES , ROESNER WOLFGANG , SCHULZ THOMAS , SPECHT MICHAEL
IPC分类号： G11C13/02 , H01L21/8242 , H01L27/108 , H01L51/00 , H01L51/05 , H01L51/30 , H01L21/8239 , H01L51/20
CPC分类号： G11C13/025 , B82Y10/00 , G11C13/0033 , G11C2213/16 , H01L27/10841 , H01L27/10864 , H01L27/10876 , H01L27/283 , H01L51/0048 , H01L51/0052 , H01L51/0512 , H01L51/057
摘要： The invention relates to a memory cell, memory cell arrangement, structuring arrangement and method for production of a memory cell. The memory cell has a vertical gate transistor and a memory capacitor, whereby the vertical gate transistor comprises a semiconducting nanostructure, grown on at least part of the memory capacitor.
摘要翻译：本发明涉及一种存储器单元，存储器单元阵列，纹理化装置和一种用于制造存储器单元的方法。该存储单元有一个垂直的开关晶体管和存储电容器，所述具有半导体纳米结构垂直开关晶体管上生长至少存储电容器的一部分。

3. 发明申请

WO02092505A3 NANOTUBE ARRAY AND METHOD FOR PRODUCING A NANOTUBE ARRAY 审中-公开
标题翻译：碳纳米管安排和方法制造纳米管安排
公开(公告)号：WO02092505A3
公开(公告)日：2003-02-27
申请号：PCT/EP0205433
申请日：2002-05-16
申请人： INFINEON TECHNOLOGIES AG , GRAHAM ANDREW , HOFMANN FRANZ , KRETZ JOHANNES , KREUPL FRANZ , LUYKEN RICHARD JOHANNES , ROESNER WOLFGANG
发明人： GRAHAM ANDREW , HOFMANN FRANZ , KRETZ JOHANNES , KREUPL FRANZ , LUYKEN RICHARD JOHANNES , ROESNER WOLFGANG
IPC分类号： B82B3/00 , C01B31/02 , G01N27/12 , G11C13/02 , H01L29/06 , H01L51/00 , H01L51/30 , H01L21/3205
CPC分类号： H01L51/0048 , B82Y10/00 , C01B32/05 , G01N27/127 , G11C13/025 , H01L51/0595
摘要： The invention relates to a nanotube array, comprising a substrate, a catalyst layer having one or more partial areas on the surface of the substrate and at least one nanotube parallel to the surface of the substrate on the surface of the catalyst layer. The nanotube array also has an electrically insulating layer between the substrate and the nanotubes and a topography such that the end segments of the at least one nanotube rest on the electrically insulating layer while its central segment rests freely. The invention also relates to a method for the production of said nanotube array.
摘要翻译：本发明涉及一种纳米管装置，其包括催化剂层布置的纳米管的表面上的衬底，包括一个或多个子区域的催化剂层，在衬底的表面上和至少一个平行于衬底的表面上。纳米管组件还包括基板，并且具有使得所述至少一个纳米管搁在其端部上的电绝缘层上，并在其中间部分露出的形貌纳米管之间的电绝缘层。本发明还涉及一种用于制造纳米管阵列。

4. 发明申请

WO2004023519A2 HIGH-DENSITY NROM-FINFET 审中-公开
标题翻译： HIGH POET NROM的FinFET
公开(公告)号：WO2004023519A2
公开(公告)日：2004-03-18
申请号：PCT/EP0309297
申请日：2003-08-21
申请人： INFINEON TECHNOLOGIES AG , HOFMANN FRANZ , LANDGRAF ERHARD , LUYKEN RICHARD JOHANNES , ROESNER WOLFGANG , SPECHT MICHAEL
发明人： HOFMANN FRANZ , LANDGRAF ERHARD , LUYKEN RICHARD JOHANNES , ROESNER WOLFGANG , SPECHT MICHAEL
IPC分类号： G11C16/04 , H01L21/28 , H01L21/336 , H01L21/8246 , H01L21/8247 , H01L21/84 , H01L27/115 , H01L27/12 , H01L29/786 , H01L29/788 , H01L29/792 , H01R11/22 , H01R13/62 , H01L
CPC分类号： H01L21/28273 , G11C16/0466 , H01L21/28282 , H01L21/845 , H01L27/115 , H01L27/11521 , H01L27/11568 , H01L27/1203 , H01L29/66795 , H01L29/66825 , H01L29/66833 , H01L29/785 , H01L29/7881 , H01L29/792 , Y10S257/903 , Y10S257/904 , Y10S257/905
摘要： The invention relates to a semiconductor memory comprising a plurality of memory cells, each memory cell comprising the following: a first conductively doped contact area (S/D), a second conductively doped contact area (S/D) and a channel region arranged therebetween, which are embodied in a plate-type rib (FIN) made of a semiconductor material and which are arranged successively in the above-mentioned order in the longitudinal direction of the rib (FIN), said rib (FIN) having a substantially rectangular shape, according to a cross-sectional view extending in a perpendicular manner with respect to the longitudinal direction of the rib (FIN), comprising an upper rib side (10) and opposite lateral rib surfaces (12, 14); a memory layer (18) which is embodied in order to program the memory cell and which is arranged on the upper rib side (10) and distanced by means a first insulating layer (20), said memory layer (18) protruding over at least one (12) of the lateral rib surfaces (12) in a normal direction of one lateral rib surface (12), such that said one lateral rib surface (12) and the upper rib surface (10) form an injection edge (16) for injecting charge carriers from the channel region into the memory layer (18); and at least one gate electrode (WL1) which is distanced by means of a second insulating layer (22) from said one lateral rib surface (12) and distanced by means of a third insulating layer (29) from the memory layer (18), said gate electrode (WL1) being electrically insulated in relation to the channel region and being embodied in order to control the electrical conductivity thereof.
摘要翻译：本发明涉及一种具有多个存储器单元，每个存储器单元包括一个半导体存储器：第一导电掺杂接触区（S / D），第二导电掺杂接触区（S / D）和一个介于沟道区，其中（在网状肋FIN ）形成的半导体材料，以及（在肋FIN的纵向方向上按此次序）被布置成一个在另一个后面，其中所述鳍（FIN）至少在垂直（在沟道区延伸到所述肋FIN的长度方向）截面，具有一肋顶部的大致rechtsecksförmige形状（10）和相对的肋的侧表面（12，14）; 所设计的用于通过第一绝缘体层编程所述存储器单元存储层（18）（20）间隔开的肋顶部（10）布置，其中，在一个正常的方向经由肋的侧表面中的至少一个（12）（12）的存储层（18）肋侧表面（12）突出，以使所述一个肋侧表面（12）和肋顶部（10）形成用于从沟道区的载流子到所述存储层注入（18）的喷射边缘（16）; 和至少一个栅极电极（WL1），其通过第二绝缘体层隔开一个（22）的肋侧表面（12）和通过所述存储层（18）的第三绝缘层（29），其中所述沟道区相对的栅电极（WL1），其电是绝缘的，并适于控制其导电性。

5. 发明申请

WO2004023557A3 SEMICONDUCTOR MEMORY WITH VERTICAL MEMORY TRANSISTORS IN A CELL FIELD ARRANGEMENT WITH 1-2F<2 >CELLS 审中-公开
标题翻译：具有1-2F 2细胞的具有垂直存储晶体管的半导体存储器
公开(公告)号：WO2004023557A3
公开(公告)日：2004-09-10
申请号：PCT/EP0309296
申请日：2003-08-21
申请人： INFINEON TECHNOLOGIES AG , HOFMANN FRANZ , LANDGRAF ERHARD , LUYKEN RICHARD JOHANNES , SCHULZ THOMAS , SPECHT MICHAEL
发明人： HOFMANN FRANZ , LANDGRAF ERHARD , LUYKEN RICHARD JOHANNES , SCHULZ THOMAS , SPECHT MICHAEL
IPC分类号： H01L21/20 , H01L21/28 , H01L21/336 , H01L21/8246 , H01L27/10 , H01L27/115 , H01L29/73 , H01L29/76 , H01L29/792
CPC分类号： H01L29/7926 , H01L21/28282 , H01L27/115 , H01L27/11568 , H01L29/66833 , H01L29/792 , H01L29/7923
摘要： The invention relates to a semiconductor memory with a number of memory cells, whereby each of the memory cells comprises four vertical memory transistors with trapping layers. The shallower contact regions are embodied in a semiconductor region running at an angle to the lines and gaps of the cell field, whereby the gate electrode preferably runs on the stage lateral surfaces of the shallower semiconductor region. A memory density of 1-2F per bit may thus be achieved.
摘要翻译：本发明涉及具有多个存储单元的半导体存储器，每个存储单元包括具有俘获层的四个垂直存储晶体管。较高的接触区形成在倾斜于单元阵列的行和列延伸的较高半导体区中，其中栅电极优选在较高半导体区的阶梯侧表面上被引导。以这种方式可以实现每比特1-2F 2的存储密度。

6. 发明申请

WO03088310A2 SUBSTRATE AND METHOD FOR PRODUCING A SUBSTRATE 审中-公开
标题翻译：衬底和方法制备基片
公开(公告)号：WO03088310A2
公开(公告)日：2003-10-23
申请号：PCT/DE0301281
申请日：2003-04-16
申请人： INFINEON TECHNOLOGIES AG , HOFMANN FRANZ , LUYKEN RICHARD JOHANNES , ROESNER WOLFGANG , SPECHT MICHAEL , STAEDELE MARTIN
发明人： HOFMANN FRANZ , LUYKEN RICHARD JOHANNES , ROESNER WOLFGANG , SPECHT MICHAEL , STAEDELE MARTIN
IPC分类号： H01L29/06 , H01L21/02 , H01L21/20 , H01L21/265 , H01L21/336 , H01L21/762 , H01L21/8234 , H01L27/08 , H01L27/088 , H01L27/12 , H01L29/786 , H01L
CPC分类号： H01L21/76262 , H01L21/76251
摘要： The invention relates to a substrate (600) which is provided with a support layer (501). An insulator layer (502) is applied to the support layer (501), comprising at least two areas having respectively different thicknesses. A semi-conductor layer (303) having an FD-area (304) and a PD-area (305) is applied to the surface of the insulating layer (502), comprising a planar surface. The planar surface is the surface which is opposite the insulating layer (502).
摘要翻译：本发明提供一种基板（600），其包括载体层（501）。其中的绝缘层（502）被施加，包括各自具有不同厚度的至少两个区域的载体层（501）上。在绝缘体层的表面（502）是与FD区域（304）和PD区域（305）的半导体层（303）被施加，其具有平坦表面，所述平坦表面与所述表面的绝缘体层（502）对面。

7. 发明申请

WO03005369A3 MOLECULAR ELECTRONICS ARRANGEMENT AND METHOD FOR PRODUCING A MOLECULAR ELECTRONICS ARRANGEMENT 审中-公开
标题翻译：分子电子装置和生产分子电子装置的方法
公开(公告)号：WO03005369A3
公开(公告)日：2003-04-17
申请号：PCT/DE0202379
申请日：2002-07-01
申请人： INFINEON TECHNOLOGIES AG , HARTWICH JESSICA , KRETZ JOHANNES , LUYKEN RICHARD JOHANNES , ROESNER WOLFGANG
发明人： HARTWICH JESSICA , KRETZ JOHANNES , LUYKEN RICHARD JOHANNES , ROESNER WOLFGANG
IPC分类号： B82B1/00 , G11C11/21 , G11C13/02 , H01L51/00 , H01L51/30 , H01L51/40 , H01L51/20
CPC分类号： G11C13/0019 , B82Y10/00 , G11C13/0014 , H01L51/0048 , H01L51/005 , H01L51/0052 , H01L51/0093 , H01L51/0595
摘要： The invention relates to a molecular electronics arrangement comprising a substrate, at least one first strip conductor having a surface and being arranged in or on the substrate, a spacer which is arranged on the surface of the at least one first strip conductor and which partially covers the surface of the at least one first strip conductor, and at least one second strip conductor which is arranged on the spacer and comprises a surface which faces the surface of the at least one first strip conductor in a plane manner. The spacer partially covers the surface of the at least one second strip conductor, and defines a pre-determined distance between the at least one first strip conductor and the at least one second strip conductor. The inventive molecular electronics arrangement also comprises molecular electronics molecules which are arranged between a free region of the surface of the at least one first strip conductor and a free region of the surface of the at least one second strip conductor, the length of said molecules being essentially equal to the distance between the at least one first strip conductor and the at least one second strip conductor. The invention also relates to a method for producing a molecular electronics arrangement.
摘要翻译：本发明涉及一种分子电子装置的至少一个第一互连配置间隔物的表面上具有基片，至少一个第一互连，其具有表面和被布置在衬底中或上，一个其中至少一个的表面上第一导体部分覆盖，设置在间隔件第二互连，其具有表面，该表面至少相对的第一配线面的表面，其中所述间隔，所述至少一个第二互连的表面部分地覆盖至少一个，并且其中，由所述间隔件的装置的预定所述至少一个第一互连和所述至少限定一个第二导体轨道之间的距离，以及之间的至少一个第一互连件的表面的暴露部分和所述至少一个第二表面的未覆盖区域导体排列的分子电子分子，其长度基本上等于至少一个第一导体迹线和至少一个第二导体迹线之间的距离。此外，提供了用于制造分子电子器件的方法。

8. 发明申请

WO0213284A2 MEMORY ELEMENT AND METHOD FOR PRODUCTION OF A MEMORY ELEMENT 审中-公开
标题翻译：存储器元件和用于制造存储器元件的方法
公开(公告)号：WO0213284A2
公开(公告)日：2002-02-14
申请号：PCT/DE0103037
申请日：2001-08-09
申请人： INFINEON TECHNOLOGIES AG , HOFMANN FRANZ , LUYKEN RICHARD JOHANNES , ROESNER WOLFGANG
发明人： HOFMANN FRANZ , LUYKEN RICHARD JOHANNES , ROESNER WOLFGANG
IPC分类号： H01L23/52 , G11C13/02 , H01L21/3205 , H01L21/768 , H01L27/10 , H01L27/28 , H01L35/24 , H01L45/00 , H01L51/05 , H01L51/20 , H01L27/00
CPC分类号： H01L27/28 , B82Y10/00 , G11C13/0014 , G11C13/0016 , G11C2213/77 , H01L51/0575
摘要： A memory element with organic material comprises two metallised layers, arranged one on top of the other, with first lines and second lines which are arranged to intersect with each other. A channel is formed at the intersections between the first line and the second line, which overlaps the first line partially and completely overlaps the second line. The channels are filled with a filling material, the electrical conductivity of which may be altered by an applied electrical voltage.
摘要翻译：有机材料存储元件具有两个金属化层，一个在另一个的上方设置有彼此交叉布置的第一线和第二线。在每种情况下，在第一条线和第二条线之间的交叉处形成沟槽，其与第一条线部分地完全重叠并且与第二条线完全重叠。沟槽填充有电导率随所施加的电压而变化的填充物。

9. 发明申请

WO2006005321A3 METHOD FOR PRODUCING AN INTEGRATED CIRCUIT AND SUBSTRATE COMPRISING A BURIED LAYER 审中-公开
标题翻译：具有弯曲层的集成电路和衬底的制造方法
公开(公告)号：WO2006005321A3
公开(公告)日：2006-02-23
申请号：PCT/DE2005001209
申请日：2005-07-08
申请人： INFINEON TECHNOLOGIES AG , ILICALI GUERKAN , LUYKEN RICHARD JOHANNES , ROESNER WOLFGANG
发明人： ILICALI GUERKAN , LUYKEN RICHARD JOHANNES , ROESNER WOLFGANG
IPC分类号： H01L21/762 , H01L21/84 , H01L27/12
CPC分类号： H01L27/1203 , H01L21/76275 , H01L21/76283 , H01L21/84 , H01L29/78648
摘要： The invention relates to a substrate comprising a buried layer. According to the invention, a silicon carrier wafer has a buried first silicon-germanium-carbon layer, on which a silicon layer is configured.
摘要翻译：具有掩埋层的衬底在硅载体晶片上具有其上形成有硅层的掩埋的第一硅 - 锗 - 碳层。

10. 发明申请

WO02090573A3 BIOCHIP ARRANGEMENT 审中-公开
标题翻译：生物薄片安排
公开(公告)号：WO02090573A3
公开(公告)日：2003-04-10
申请号：PCT/DE0201700
申请日：2002-05-10
申请人： INFINEON TECHNOLOGIES AG , FREY ALEXANDER , HOFMANN FRANZ , LUYKEN RICHARD JOHANNES
发明人： FREY ALEXANDER , HOFMANN FRANZ , LUYKEN RICHARD JOHANNES
IPC分类号： C12Q1/00 , G01N33/543 , C12Q1/68
CPC分类号： C12Q1/00 , G01N33/54373 , G01N33/5438
摘要： The biochip comprises a substrate, at least one sensor, arranged on or in the substrate and an electrically conducting permeation layer, arranged at a given, non-zero separation from the surface of the substrate, to which an electrical voltage may be applied. The biochip arrangement may be used, for example, as a DNA sensor, whereby a receptor molecule, immobilised on the sensor electrode, hybridises a DNA molecule and thus an electrical sensor signal which may be drawn from between sensor electrodes, is influenced in a characteristic manner.
摘要翻译：生物芯片组件包括一基板，至少一个设置在上或在衬底传感器和导电渗透层，其从所述衬底的表面布置在预定的非零的距离，并且其中，电电压可以被施加到。生物芯片布置是有用的，例如，通过固定的捕获分子的DNA传感器杂交的DNA分子上的传感器电极，因此所涉及的传感器电极之间，可移动的电传感器信号特征的影响。

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