专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

WO2007027813A3 MICRO-CAVITY MEMS DEVICE AND METHOD OF FABRICATING SAME 审中-公开
标题翻译：微孔MEMS器件及其制造方法
公开(公告)号：WO2007027813A3
公开(公告)日：2007-12-06
申请号：PCT/US2006033924
申请日：2006-08-30
申请人： IBM , HSU LOUIS C , CLEVENGER LAWRENCE A , DALTON TIMOTHY J , RADENS CARL J , WONG KEITH KWONG HON , YANG CHIH-CHAO
发明人： HSU LOUIS C , CLEVENGER LAWRENCE A , DALTON TIMOTHY J , RADENS CARL J , WONG KEITH KWONG HON , YANG CHIH-CHAO
IPC分类号： H01P1/10
CPC分类号： H01H50/005 , H01H2050/007 , Y10T29/4902 , Y10T29/49105 , Y10T29/49147
摘要： A MEM switch is described having a free moving element (140) within in micro-cavity (40), and guided by at least one inductive element. The switch consists of an upper inductive coil (170); an optional lower inductive coil (190), each having a metallic core (180,200) preferably made of permalloy; a micro-cavity (40); and a free-moving switching element (140) also made of magnetic material. Switching is achieved by passing a current through the upper coil, inducing a magnetic field in the coil element. The magnetic field attracts the free-moving magnetic element upwards, shorting two open wires (M_I M_r) and thus, closing the switch. When the current flow stops or is reversed, the free-moving magnetic element drops back by gravity to the bottom of the micro-cavity and the wires open. When gravity cannot be used, a lower coil becomes necessary to pull the free-moving switching element back and holding it at its original position.
摘要翻译：描述了一种MEM开关，其具有在微腔（40）内的自由移动元件（140），并由至少一个电感元件引导。开关由上部感应线圈（170）组成; 可选的下感应线圈（190），每个具有优选由坡莫合金制成的金属芯（180,200）微腔（40）; 以及也由磁性材料制成的自由移动的开关元件（140）。通过使电流通过上部线圈来实现切换，从而在线圈元件中产生磁场。磁场向上吸引自由移动的磁性元件，使两根开放的导线（M_I M_r）短路，从而闭合开关。当电流停止或反转时，自由移动的磁性元件通过重力返回到微腔的底部并且电线打开。当不能使用重力时，需要下部线圈将自由移动的开关元件拉回并将其保持在其原始位置。

2. 发明申请

WO2007016047A3 METHOD AND STRUCTURE FOR FORMING SLOT VIA BITLINE FOR MRAM DEVICES 审中-公开
标题翻译：用于通过MRAM器件的位线形成槽的方法和结构
公开(公告)号：WO2007016047A3
公开(公告)日：2008-01-03
申请号：PCT/US2006028718
申请日：2006-07-24
申请人： IBM , GAIDIS MICHAEL C , RADENS CARL , CLEVENGER LAWRENCE A , DALTON TIMOTHY J , HSU LOUIS L C , WONG KEITH KWONG HON , YANG CHIH-CHAO
发明人： GAIDIS MICHAEL C , RADENS CARL , CLEVENGER LAWRENCE A , DALTON TIMOTHY J , HSU LOUIS L C , WONG KEITH KWONG HON , YANG CHIH-CHAO
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： B82Y10/00 , H01L27/222 , H01L43/12
摘要： A magnetic random access memory (MRAM) device includes a magnetic tunnel junction (MTJ) stack formed over a lower wiring level, a hardmask formed on the MTJ stack, and an upper wiring level formed over the hardmask. The upper wiring level includes a slot via bitline formed therein, the slot via bitline in contact with the hardmask and in contact with an etch stop layer partially surrounding sidewalls of the hardmask.
摘要翻译：磁性随机存取存储器（MRAM）器件包括形成在下布线层上的磁隧道结（MTJ）堆叠，形成在MTJ堆叠上的硬掩模和形成在硬掩模上的上布线层。上布线层包括经由位于其中的位线的槽，槽经由与硬掩模接触的位线并与部分地围绕硬掩模的侧壁的蚀刻停止层接触。

3. 发明申请

WO2006113186A3 INTERCONNECT STRUCTURE AND METHOD OF FABRICATION OF SAME 审中-公开
标题翻译：互连结构及其制造方法
公开(公告)号：WO2006113186A3
公开(公告)日：2008-07-24
申请号：PCT/US2006013179
申请日：2006-04-07
申请人： IBM , YANG CHIH-CHAO , CLEVENGER LAWRENCE A , COWLEY ANDREW P , DALTON TIMOTHY J , YOON MEEYOUNG H
发明人： YANG CHIH-CHAO , CLEVENGER LAWRENCE A , COWLEY ANDREW P , DALTON TIMOTHY J , YOON MEEYOUNG H
IPC分类号： H01L21/4763
CPC分类号： H01L21/76849 , H01L21/76807 , H01L21/76814 , H01L21/76831 , H01L21/76843 , H01L2924/0002 , H01L2924/00
摘要： A damascene wire and method of forming the wire. The method including: forming a mask layer on a top surface of a dielectric layer; forming an opening in the mask layer; forming a trench in the dielectric layer where the dielectric layer is not protected by the mask layer; recessing the sidewalls of the trench under the mask layer; forming a conformal conductive liner on all exposed surface of the trench and the mask layer; filling the trench with a core electrical conductor; removing portions of the conductive liner extending above the top surface of the dielectric layer and removing the mask layer; and forming a conductive cap on a top surface of the core conductor. The structure includes a core conductor clad in a conductive liner and a conductive capping layer in contact with the top surface of the core conductor that is not covered by the conductive liner.
摘要翻译：一种镶嵌线及其形成方法。该方法包括：在电介质层的顶表面上形成掩模层; 在掩模层中形成开口; 在电介质层中形成沟槽，其中电介质层不被掩模层保护; 使掩模层下方的沟槽的侧壁凹陷; 在沟槽和掩模层的所有暴露表面上形成共形导电衬垫; 用芯电导体填充沟槽; 去除在电介质层的顶表面上方延伸的导电衬垫的部分，并去除掩模层; 以及在所述芯导体的顶表面上形成导电帽。该结构包括包覆在导电衬垫中的芯导体和与未被导电衬垫覆盖的芯导体的顶表面接触的导电覆盖层。

4. 发明申请

WO2006113158A3 MIM CAPACITOR AND METHOD OF FABRICATING SAME 审中-公开
标题翻译： MIM电容器及其制造方法
公开(公告)号：WO2006113158A3
公开(公告)日：2007-03-01
申请号：PCT/US2006012904
申请日：2006-04-07
申请人： IBM , YANG CHIH-CHANO , CLEVENGER LAWRENCE A , DALTON TIMOTHY J , HSU LOUIS C
发明人： YANG CHIH-CHANO , CLEVENGER LAWRENCE A , DALTON TIMOTHY J , HSU LOUIS C
IPC分类号： H01L21/8242 , H01L21/20
CPC分类号： H01L23/5223 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A damascene MIM capacitor and a method of fabricating the MIM capacitor. The MIM capacitor includes a dielectric layer (140) having top and bottom surfaces; a trench in the dielectric layer, the trench extending from the top surface to the bottom surface of the dielectric layer (140); a first plate of a MIM capacitor comprising a conformal conductive liner (175) formed on all sidewalls and extending along a bottom of the trench, the bottom of the trench coplanar with the bottom surface of the dielectric layer; an insulating layer (190) formed over a top surface of the conformal conductive liner; and a second plate (195) of the MIM capacitor comprising a core conductor in direct physical contact with the insulating layer, the core conductor filling spaces in the trench not filled by the conformal conductive liner and the insulating layer. The method includes forming portions of the MIM capacitor simultaneously with damascene interconnection wires.
摘要翻译：一种镶嵌MIM电容器和一种制造MIM电容器的方法。 MIM电容器包括具有顶表面和底表面的电介质层（140）所述电介质层中的沟槽，所述沟槽从所述介电层（140）的顶表面延伸到所述底表面; MIM电容器的第一板包括形成在所有侧壁上并沿着沟槽的底部延伸的共形导电衬垫（175），沟槽的底部与电介质层的底表面共面; 绝缘层（190），形成在所述共形导电衬垫的顶表面上; 和MIM电容器的第二板（195），其包括与所述绝缘层直接物理接触的芯导体，所述沟槽中的所述芯导体填充空间未被所述共形导电衬垫和所述绝缘层填充。该方法包括与镶嵌互连线同时形成MIM电容器的一部分。

5. 发明申请

WO2011032741A3 METHOD FOR MANUFACTURING A THIN-FILM PHOTOVOLTAIC CELL MODULE ENCOMPASSING AN ARRAY OF CELLS AND PHOTOVOLTAIC CELL MODULE 审中-公开
标题翻译：制造薄膜光伏电池模块的方法，包括电池阵列和光电池模块
公开(公告)号：WO2011032741A3
公开(公告)日：2012-04-05
申请号：PCT/EP2010059849
申请日：2010-07-09
申请人： IBM , KRAUSE RAINER KLAUS , LI ZHENGWEN O , QUON ROGER A , CLEVENGER LAWRENCE A , PETRARCA KEVIN S , RADENS CARL , SAPP BRIAN C
发明人： KRAUSE RAINER KLAUS , LI ZHENGWEN O , QUON ROGER A , CLEVENGER LAWRENCE A , PETRARCA KEVIN S , RADENS CARL , SAPP BRIAN C
IPC分类号： H01L31/05 , H05K1/02 , H05K3/22
CPC分类号： H01L31/042 , H01L31/0465 , H01L31/0504 , H02S50/10 , Y02E10/50
摘要： The invention relates to a method for manufacturing a thin-film photovoltaic cell module (10) encompassing an array of cells (100), comprising the steps of (i) providing the array of cells (100); (ii) determining, per cell (100), an electrical performance for one or more cells (100) of the array; (iii) identifying each cell (100) by its position in the array; (iv) determining one or more electrical paths (50, 52, 54) encompassing one or more of the cells (100) according to at least one optimization criterion; and (v) combining two or more cells (100) for realizing one or more electrical paths (50, 52, 54) by maintaining or establishing electrical connections (30) between individual cells (100) of the array according to the at least one optimization criterion.
摘要翻译：本发明涉及一种用于制造包围电池阵列（100）的薄膜光伏电池模块（10）的方法，包括以下步骤：（i）提供电池阵列（100）; （ii）每个单元（100）确定阵列的一个或多个单元（100）的电性能; （iii）通过其在阵列中的位置来识别每个单元（100）; （iv）根据至少一个优化标准确定包含一个或多个所述单元（100）的一个或多个电路径（50,52,54）; 以及（v）通过根据所述至少一个维持或建立阵列的各个单元（100）之间的电连接（30），组合用于实现一个或多个电路径（50,52,54）的两个或更多个单元（100）优化标准。

6. 发明申请

WO2007127503A8 STRUCTURE AND METHOD FOR MOSFET GATE ELECTRODE LANDING PAD 审中-公开
标题翻译： MOSFET栅极电极贴片的结构和方法
公开(公告)号：WO2007127503A8
公开(公告)日：2008-09-04
申请号：PCT/US2007060564
申请日：2007-01-16
申请人： IBM
发明人： CLEVENGER LAWRENCE A , DALTON TIMOTHY J , HSU LOUIS C , RADENS CARL , WONG KWONG-HON , YANG CHIH-CHAO
IPC分类号： H01L27/12 , H01L27/01 , H01L31/0392
CPC分类号： H01L27/1203 , H01L21/28114 , H01L21/823456 , H01L21/84 , H01L29/42376 , H01L2924/0002 , H01L2924/00
摘要： A transistor device and method of forming the same comprises a substrate; a first gate electrode over the substrate; a second gate electrode over the substrate; and a landing pad comprising a pair of flanged ends overlapping the second gate electrode, wherein the structure of the second gate electrode is discontinuous with the structure of the landing pad.
摘要翻译：晶体管器件及其形成方法包括：衬底; 衬底上的第一栅电极; 在衬底上的第二栅电极; 以及包括与第二栅电极重叠的一对凸缘端的着陆焊盘，其中第二栅电极的结构与着陆焊盘的结构不连续。

7. 发明申请

WO2007127503A2 STRUCTURE AND METHOD FOR MOSFET GATE ELECTRODE LANDING PAD 审中-公开
标题翻译： MOSFET栅极电极贴片的结构与方法
公开(公告)号：WO2007127503A2
公开(公告)日：2007-11-08
申请号：PCT/US2007060564
申请日：2007-01-16
申请人： IBM
发明人： CLEVENGER LAWRENCE A , DALTON TIMOTHY J , HSU LOUIS C , RADENS CARL , YANG CHIH-CHAO
IPC分类号： H01L27/12 , H01L27/01 , H01L31/0392
CPC分类号： H01L27/1203 , H01L21/28114 , H01L21/823456 , H01L21/84 , H01L29/42376 , H01L2924/0002 , H01L2924/00
摘要： A transistor device and method of forming the same comprises a substrate; a first gate electrode over the substrate; a second gate electrode over the substrate; and a landing pad comprising a pair of flanged ends overlapping the second gate electrode, wherein the structure of the second gate electrode is discontinuous with the structure of the landing pad.
摘要翻译：晶体管器件及其形成方法包括：衬底; 衬底上的第一栅电极; 在所述衬底上方的第二栅电极; 以及着陆垫，其包括与所述第二栅极重叠的一对凸缘端，其中所述第二栅极的结构与所述着陆焊盘的结构不连续。

8. 发明申请

WO0195382A3 DIAMOND AS A POLISH-STOP LAYER FOR CHEMICAL-MECHANICAL PLANARIZATION IN A DAMASCENE PROCESS FLOW 审中-公开
标题翻译：金刚石作为化学机械平面化在抛物线工艺流程中的抛物面层
公开(公告)号：WO0195382A3
公开(公告)日：2002-08-29
申请号：PCT/US0118539
申请日：2001-06-07
申请人： INFINEON TECHNOLOGIES CORP , IBM
发明人： CLEVENGER LAWRENCE A , HSU LOUIS , STEPHENS JEREMY K , WISE MICHAEL
IPC分类号： H01L21/76 , H01L21/285 , H01L21/304 , H01L21/306 , H01L21/308 , H01L21/3105 , H01L21/311 , H01L21/3205 , H01L21/321 , H01L21/762 , H01L21/768
CPC分类号： H01L21/31053 , H01L21/28525 , H01L21/3081 , H01L21/31144 , H01L21/3212 , H01L21/7684
摘要： A method of using diamond or a diamond-like carbon layer as a polish-stop for patterning a metal level into an inter-level dielectric substrate using a damascene process flow. The diamond or diamond-like carbon layer is deposited onto the surface of the substrate before patterning the metal level. A protective layer is then deposited over the diamond or diamond-like carbon polish-stop layer, wherein such protective layer may act as an additional polish-stop layer. Together, the diamond or diamond-like carbon polish-stop layer and the protective layer are used as a hard-mask for patterning the trenches that will become the metal features, wherein such protective layer protects the diamond or diamond-like carbon polish-stop layer during the patterning process. After deposition of a conductive metal layer, the dielectric substrate is polished to remove excess conductive material, as well as topography. In the polishing process, the diamond or diamond-like carbon polish-stop layer and any remaining protective layer are used as polish-stop layers. The diamond or diamond-like carbon polish-stop layer allows for an improved planar surface, thereby resulting in an sufficient decrease in topography at the surface of the inter-level dielectric.
摘要翻译：使用金刚石或类金刚石碳层作为抛光停止件的方法，其使用镶嵌工艺流程将金属层图案化成层间电介质基板。在图案化金属层之前，将金刚石或类金刚石碳层沉积在基板的表面上。然后将保护层沉积在金刚石或类金刚石碳抛光层上，其中这种保护层可以用作另外的抛光停止层。一起使用金刚石或类金刚石碳抛光层和保护层作为用于图案化将成为金属特征的沟槽的硬掩模，其中这种保护层保护金刚石或类金刚石碳抛光在图案化过程中。在沉积导电金属层之后，电介质基底被抛光以除去过量的导电材料以及形貌。在抛光过程中，将金刚石或类金刚石碳抛光层和任何剩余的保护层用作抛光 - 停止层。金刚石或类金刚石碳抛光层允许改进的平面表面，从而导致层间电介质表面的形貌的充分降低。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式