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1. 发明申请

WO2011133339A2 MONOLAYER DOPANT EMBEDDED STRESSOR FOR ADVANCED CMOS 审中-公开
标题翻译：用于高级CMOS的单层掺杂嵌入式压电器
公开(公告)号：WO2011133339A2
公开(公告)日：2011-10-27
申请号：PCT/US2011/031693
申请日：2011-04-08
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , CHAN, Kevin, K. , DUBE, Abhishek , HOLT, Judson, R. , LI, Jinghong , NEWBURY, Joseph, S. , ONTALUS, Viorel , PARK, Dae-Gyu , ZHU, Zhengmao
发明人： CHAN, Kevin, K. , DUBE, Abhishek , HOLT, Judson, R. , LI, Jinghong , NEWBURY, Joseph, S. , ONTALUS, Viorel , PARK, Dae-Gyu , ZHU, Zhengmao
IPC分类号： H01L29/78 , H01L21/336 , H01L27/092 , H01L21/8228
CPC分类号： H01L29/7848 , H01L21/823807 , H01L21/823814 , H01L29/165 , H01L29/6656 , H01L29/66636 , H01L29/7834
摘要： Semiconductor structures are disclosed that have embedded stressor elements therein. The disclosed structures include an FET gate stack 18 located on an upper surface of a semiconductor substrate 12. The FET gate stack includes source and drain extension regions 28 located within the semiconductor substrate at a footprint of the FET gate stack. A device channel 40 is also present between the source and drain extension regions and beneath the gate stack. The structure further includes embedded stressor elements 34 located on opposite sides of the FET gate stack and within the semiconductor substrate. Each of the embedded stressor elements includes a lower layer of a first epitaxy 36 doped semiconductor material having a lattice constant that is different from a lattice constant of the semiconductor substrate and imparts a strain in the device channel, and an upper layer of a second epitaxy 38 doped semiconductor material located atop the lower layer. The lower layer of the first epitaxy doped semiconductor material has a lower content of dopant as compared to the upper layer of the second epitaxy doped semiconductor material. The structure further includes a monolayer of dopant located within the upper layer of each of the embedded stressor elements. The monolayer of dopant is in direct contact with an edge of either the source extension region or the drain extension region.
摘要翻译：公开了在其中具有嵌入的应力元件的半导体结构。所公开的结构包括位于半导体衬底12的上表面上的FET栅极堆叠18. FET栅极堆叠包括在FET栅极堆叠的覆盖区处位于半导体衬底内的源极和漏极延伸区域28。器件沟道40也存在于源极延伸区域和漏极延伸区域之间以及栅极堆叠层下方。该结构还包括位于FET栅极堆叠的相对侧并且位于半导体衬底内的嵌入式应力元件34。每个嵌入的应力元件包括第一外延36掺杂半导体材料的下层，其具有不同于半导体衬底的晶格常数的晶格常数并且在器件沟道中施加应变，并且第二外延的上层 38掺杂的半导体材料位于下层的顶部。与第二外延掺杂半导体材料的上层相比，第一外延掺杂半导体材料的下层具有较低的掺杂剂含量。该结构还包括位于每个嵌入的应力元件的上层内的掺杂剂单层。掺杂剂的单层与源极延伸区域或漏极延伸区域的边缘直接接触。

2. 发明申请

WO2012099808A1 STRESSED CHANNEL FET WITH SOURCE/DRAIN BUFFERS 审中-公开
标题翻译：具有源/漏极缓冲器的应力通道FET
公开(公告)号：WO2012099808A1
公开(公告)日：2012-07-26
申请号：PCT/US2012/021407
申请日：2012-01-16
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , JOHNSON, Jeffrey, B. , MURALIDHAR, Ramachandran , OLDIGES, Phillip, J. , ONTALUS, Viorel, C. , XIU, Kai
发明人： JOHNSON, Jeffrey, B. , MURALIDHAR, Ramachandran , OLDIGES, Phillip, J. , ONTALUS, Viorel, C. , XIU, Kai
IPC分类号： H01L21/782 , H01L21/8238 , H01L27/12
CPC分类号： H01L29/7848 , H01L29/0847 , H01L29/165 , H01L29/66636 , H01L29/78
摘要： A method for forming a stressed channel field effect transistor (FET) with source/drain buffers (501) includes etching cavities (301) in a substrate (201) on either side of a gate stack located (202/203) on the substrate; depositing source/drain buffer material (401) in the cavities; etching the source/drain buffer material to form vertical source/drain buffers adjacent to a channel region (502) of the FET; and depositing source/drain stressor material (601) in the cavities adjacent to and over the vertical source/drain buffers.
摘要翻译：用于形成具有源极/漏极缓冲器（501）的应力通道场效应晶体管（FET）的方法包括位于基板上的栅极堆叠（202/203）的任一侧上的衬底（201）中的蚀刻腔（301）在空腔中沉积源极/漏极缓冲材料（401）; 蚀刻源极/漏极缓冲材料以形成与FET的沟道区域（502）相邻的垂直源极/漏极缓冲器; 以及将源极/漏极应力材料（601）沉积在与垂直源极/漏极缓冲器相邻并在其上方的空腔中。

3. 发明申请

WO2011133339A3 MONOLAYER DOPANT EMBEDDED STRESSOR FOR ADVANCED CMOS 审中-公开
标题翻译：用于高级CMOS的单层掺杂嵌入式压电器
公开(公告)号：WO2011133339A3
公开(公告)日：2012-03-08
申请号：PCT/US2011031693
申请日：2011-04-08
申请人： IBM , CHAN KEVIN K , DUBE ABHISHEK , HOLT JUDSON R , LI JINGHONG , NEWBURY JOSEPH S , ONTALUS VIOREL , PARK DAE-GYU , ZHU ZHENGMAO
发明人： CHAN KEVIN K , DUBE ABHISHEK , HOLT JUDSON R , LI JINGHONG , NEWBURY JOSEPH S , ONTALUS VIOREL , PARK DAE-GYU , ZHU ZHENGMAO
IPC分类号： H01L29/78 , H01L21/336 , H01L21/8228 , H01L27/092
CPC分类号： H01L29/7848 , H01L21/823807 , H01L21/823814 , H01L29/165 , H01L29/6656 , H01L29/66636 , H01L29/7834
摘要： Semiconductor structures are disclosed that have embedded stressor elements therein. The disclosed structures include an FET gate stack 18 located on an upper surface of a semiconductor substrate 12. The FET gate stack includes source and drain extension regions 28 located within the semiconductor substrate at a footprint of the FET gate stack. A device channel 40 is also present between the source and drain extension regions and beneath the gate stack. The structure further includes embedded stressor elements 34 located on opposite sides of the FET gate stack and within the semiconductor substrate. Each of the embedded stressor elements includes a lower layer of a first epitaxy 36 doped semiconductor material having a lattice constant that is different from a lattice constant of the semiconductor substrate and imparts a strain in the device channel, and an upper layer of a second epitaxy 38 doped semiconductor material located atop the lower layer. The lower layer of the first epitaxy doped semiconductor material has a lower content of dopant as compared to the upper layer of the second epitaxy doped semiconductor material. The structure further includes a monolayer of dopant located within the upper layer of each of the embedded stressor elements. The monolayer of dopant is in direct contact with an edge of either the source extension region or the drain extension region.
摘要翻译：公开了在其中具有嵌入的应力元件的半导体结构。所公开的结构包括位于半导体衬底12的上表面上的FET栅极堆叠18. FET栅极堆叠包括在FET栅极堆叠的覆盖区处位于半导体衬底内的源极和漏极延伸区域28。器件沟道40也存在于源极延伸区域和漏极延伸区域之间以及栅极堆叠层下方。该结构还包括位于FET栅极堆叠的相对侧并且位于半导体衬底内的嵌入式应力元件34。每个嵌入的应力元件包括第一外延36掺杂半导体材料的下层，其具有不同于半导体衬底的晶格常数的晶格常数并且在器件沟道中施加应变，并且第二外延的上层 38掺杂的半导体材料位于下层的顶部。与第二外延掺杂半导体材料的上层相比，第一外延掺杂半导体材料的下层具有较低的掺杂剂含量。该结构还包括位于每个嵌入的应力元件的上层内的掺杂剂单层。掺杂剂的单层与源极延伸区域或漏极延伸区域的边缘直接接触。

4. 发明申请

WO2012064912A3 BUTTED SOI JUNCTION ISOLATION STRUCTURES AND DEVICES AND METHOD OF FABRICATION 审中-公开
公开(公告)号：WO2012064912A3
公开(公告)日：2012-05-18
申请号：PCT/US2011/060084
申请日：2011-11-10
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , JOHNSON, Jeffrey, B. , NARASIMHA, Shreesh , NAYFEH, Hasan, M. , ONTALUS, Viorel, C. , ROBINSON, Robert, R.
发明人： JOHNSON, Jeffrey, B. , NARASIMHA, Shreesh , NAYFEH, Hasan, M. , ONTALUS, Viorel, C. , ROBINSON, Robert, R.
IPC分类号： H01L29/78 , H01L21/336
摘要： A structure, a FET, a method of making the structure and of making the FET. The structure including: a silicon layer (105; Fig. 5) on a buried oxide (BOX) layer (115) of a silicon-on-insulator substrate (100); a trench in the silicon layer extending from a top surface of the silicon layer into the silicon layer, the trench not extending to the BOX layer (160, 165, and 170), a doped region (155) in the silicon layer between and abutting the BOX layer and a bottom of the trench, the first doped region doped to a first dopant concentration; a first epitaxial layer (160), doped to a second dopant concentration, in a bottom of the trench; a second epitaxial layer (165), doped to a third dopant concentration, on the first epitaxial layer in the trench; and wherein the third dopant concentration is greater than the first and second dopant concentrations and the first dopant concentration is greater than the second dopant concentration.

5. 发明申请

WO2012064912A2 BUTTED SOI JUNCTION ISOLATION STRUCTURES AND DEVICES AND METHOD OF FABRICATION 审中-公开
标题翻译：所谓的SOI结隔离结构和装置以及制造方法
公开(公告)号：WO2012064912A2
公开(公告)日：2012-05-18
申请号：PCT/US2011060084
申请日：2011-11-10
申请人： IBM , JOHNSON JEFFREY B , NARASIMHA SHREESH , NAYFEH HASAN M , ONTALUS VIOREL C , ROBINSON ROBERT R
发明人： JOHNSON JEFFREY B , NARASIMHA SHREESH , NAYFEH HASAN M , ONTALUS VIOREL C , ROBINSON ROBERT R
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7824 , H01L21/76237 , H01L21/84 , H01L27/1203
摘要： A structure, a FET, a method of making the structure and of making the FET. The structure including: a silicon layer (105; Fig. 5) on a buried oxide (BOX) layer (115) of a silicon-on-insulator substrate (100); a trench in the silicon layer extending from a top surface of the silicon layer into the silicon layer, the trench not extending to the BOX layer (160, 165, and 170), a doped region (155) in the silicon layer between and abutting the BOX layer and a bottom of the trench, the first doped region doped to a first dopant concentration; a first epitaxial layer (160), doped to a second dopant concentration, in a bottom of the trench; a second epitaxial layer (165), doped to a third dopant concentration, on the first epitaxial layer in the trench; and wherein the third dopant concentration is greater than the first and second dopant concentrations and the first dopant concentration is greater than the second dopant concentration.
摘要翻译：一种结构，一种FET，一种制造该结构和制造该FET的方法。所述结构包括：在绝缘体上硅衬底（100）上的掩埋氧化物（BOX）层（115）上的硅层（105;图5）; 所述硅层中的沟槽从所述硅层的顶表面延伸到所述硅层中，所述沟槽不延伸到所述BOX层（160,165和170），所述硅层中的掺杂区域（155）和邻接 BOX层和沟槽的底部，掺杂到第一掺杂剂浓度的第一掺杂区; 在沟槽的底部掺杂到第二掺杂剂浓度的第一外延层（160）; 在沟槽中的第一外延层上掺杂到第三掺杂剂浓度的第二外延层（165）; 并且其中所述第三掺杂剂浓度大于所述第一和第二掺杂剂浓度，并且所述第一掺杂剂浓度大于所述第二掺杂剂浓度。

6. 发明申请

WO2011051109A1 BI-LAYER nFET EMBEDDED STRESSOR ELEMENT AND INTEGRATION TO ENHANCE DRIVE CURRENT 审中-公开
标题翻译：双层NFET嵌入式应力元件和集成以增强驱动电流
公开(公告)号：WO2011051109A1
公开(公告)日：2011-05-05
申请号：PCT/EP2010/065495
申请日：2010-10-15
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , IBM UNITED KINGDOM LIMITED , ONTALUS, Viorel , CHAN, Kevin , DUBE, Abhishek , LI, Jinghong , ZHU, Zhengmao
发明人： ONTALUS, Viorel , CHAN, Kevin , DUBE, Abhishek , LI, Jinghong , ZHU, Zhengmao
IPC分类号： H01L21/336 , H01L29/165 , H01L29/78
CPC分类号： H01L29/7848 , H01L29/165 , H01L29/66636 , H01L29/7834 , Y10S257/90 , Y10S257/902 , Y10S257/903
摘要： A semiconductor structure including a bi-layer nFET embedded stressor element is disclosed. The bi-layer nFET embedded stressor element can be integrated into any CMOS process flow. The bi-layer nFET embedded stressor element includes an implant damaged free first layer of a first epitaxy semiconductor material having a lattice constant that is different from a lattice constant of a semiconductor substrate and imparts a tensile strain in a device channel of an nFET gate stack. Typically, and when the semiconductor is composed of silicon, the first layer of the bi-layer nFET embedded stressor element is composed of Si:C. The bi-layer nFET embedded stressor element further includes a second layer of a second epitaxy semiconductor material that has a lower resistance to dopant diffusion than the first epitaxy semiconductor material. Typically, and when the semiconductor is composed of silicon, the second layer of the bi-layer nFET embedded stressor element is composed of silicon. Only the second layer of the bi-layer nFET embedded stressor element includes the implanted source/drain regions.
摘要翻译：公开了一种包括双层nFET嵌入式应力元件的半导体结构。双层nFET嵌入式应力元件可以集成到任何CMOS工艺流程中。双层nFET嵌入式应力元件包括具有不同于半导体衬底的晶格常数的晶格常数的第一外延半导体材料的自由第一层的植入物，并且在nFET栅极堆叠的器件沟道中施加拉伸应变。通常，当半导体由硅组成时，双层nFET嵌入的应力元件的第一层由Si：C组成。双层nFET嵌入式应力元件还包括具有比第一外延半导体材料更低的掺杂剂扩散阻力的第二外延半导体材料层。通常，当半导体由硅组成时，双层nFET嵌入的应力元件的第二层由硅组成。双层nFET嵌入式应力元件的第二层仅包括注入的源极/漏极区域。

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