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1. 发明申请

WO2012102734A1 METHODS, SYSTEMS AND APPARATUS FOR RESISTIVE MEMORY 审中-公开
标题翻译：电阻记忆体的方法，系统和装置
公开(公告)号：WO2012102734A1
公开(公告)日：2012-08-02
申请号：PCT/US2011/023041
申请日：2011-01-28
申请人： HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P. , NICKEL, Janice H. , RIBEIRO, Gilberto Medeiros , KUEKES, Philip J.
发明人： NICKEL, Janice H. , RIBEIRO, Gilberto Medeiros , KUEKES, Philip J.
IPC分类号： G11C13/00 , G11C16/06
CPC分类号： G11C13/0007 , G11C13/004 , G11C16/349 , G11C2013/0057 , G11C2013/0073
摘要： In one embodiment, a resistive memory system includes a resistive memory element array and a controller operatively coupled to the resistive memory element array. The resistive memory element array includes a plurality of word lines, a plurality of bit lines, and a plurality of resistive memory elements. Each resistive memory element from the plurality of resistive memory elements coupled to a word line from the plurality of word lines and a bit line from the plurality of bit lines. The controller is operatively coupled to the resistive memory element array at the plurality of word lines and the plurality of bit lines and provides read signals and reverse read signals to the resistive memory element array.
摘要翻译：在一个实施例中，电阻式存储器系统包括电阻式存储器元件阵列和可操作地耦合到电阻式存储器元件阵列的控制器。电阻性存储元件阵列包括多个字线，多个位线和多个电阻存储元件。来自所述多个电阻性存储器元件的每个电阻性存储器元件耦合到来自所述多个字线的字线和来自所述多个位线的位线。控制器可操作地耦合到多个字线和多个位线处的电阻存储器元件阵列，并向电阻存储器元件阵列提供读取信号和反向读取信号。

2. 发明申请

WO2014021833A1 NON-VOLATILE RESISTIVE MEMORY CELLS 审中-公开
标题翻译：非挥发性电阻记忆细胞
公开(公告)号：WO2014021833A1
公开(公告)日：2014-02-06
申请号：PCT/US2012/048941
申请日：2012-07-31
申请人： HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P. , CHO, Hans Se-young , NICKEL, Janice H. , WILLIAMS, R. Stanley , ROH, Jaesung , PARK, Jinwon , HYEJUNG, Choi , JOO, Moon Sig , MOON, Jiwon , LEE, Chang-goo , SOHN, Yong Sun , KIM, Jeong Tae
发明人： CHO, Hans Se-young , NICKEL, Janice H. , WILLIAMS, R. Stanley , ROH, Jaesung , PARK, Jinwon , HYEJUNG, Choi , JOO, Moon Sig , MOON, Jiwon , LEE, Chang-goo , SOHN, Yong Sun , KIM, Jeong Tae
IPC分类号： H01L27/115 , H01L21/8247
CPC分类号： H01L45/1233 , H01L27/101 , H01L27/2463 , H01L45/08 , H01L45/124 , H01L45/1253 , H01L45/146 , H01L45/1641 , H01L45/1675 , H01L45/1691
摘要： Examples of the present disclosure include non-volatile resistive memory cells and methods of forming the same. An example of a non-volatile resistive memory cell includes a first portion of the non-volatile resistive memory cell formed as a vertically-extending structure on a first electrode, where the first portion comprises at least one memristive material across a width of the vertically-extending structure. The non-volatile resistive memory cell also includes a second portion formed as a vertically-extending memristive material structure on at least one sidewall of the first portion.
摘要翻译：本公开的实例包括非易失性电阻存储器单元及其形成方法。非易失性电阻性存储单元的示例包括在第一电极上形成为垂直延伸结构的非易失性电阻性存储单元的第一部分，其中第一部分包括穿过垂直宽度的至少一个阻聚材料延伸结构。非易失性电阻性存储单元还包括在第一部分的至少一个侧壁上形成为垂直延伸的忆阻材料结构的第二部分。

3. 发明申请

WO2013055332A1 SELECT DEVICE FOR CROSS POINT MEMORY STRUCTURES 审中-公开
标题翻译：用于跨点存储器结构的选择器件
公开(公告)号：WO2013055332A1
公开(公告)日：2013-04-18
申请号：PCT/US2011/056006
申请日：2011-10-12
申请人： HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P. , RIBEIRO, Gilberto M. , NICKEL, Janice H.
发明人： RIBEIRO, Gilberto M. , NICKEL, Janice H.
IPC分类号： G11C13/00 , G11C7/00 , G11C5/02
CPC分类号： H01L27/2463 , G11C13/0004 , G11C13/0007 , G11C13/0011 , G11C13/003 , G11C13/004 , G11C13/0069 , G11C2013/0045 , G11C2213/33 , G11C2213/72 , H01L29/88 , H01L45/16
摘要： The present disclosure provides a memory cell that includes a resistive memory element disposed between a first conductor and a second conductor, the first conductor and the second conductor configured to activate the resistive memory element. The memory cell also includes a backward diode disposed in series with the memory element between the memory element and either the first conductor or the second conductor.
摘要翻译：本公开提供了一种存储单元，其包括设置在第一导体和第二导体之间的电阻性存储元件，第一导体和第二导体被配置为激活电阻式存储元件。存储单元还包括与存储元件串联设置在存储元件与第一导体或第二导体之间的后向二极管。

4. 发明申请

WO2015183291A1 MEMORY CONTROLLERS 审中-公开
标题翻译：内存控制器
公开(公告)号：WO2015183291A1
公开(公告)日：2015-12-03
申请号：PCT/US2014/040115
申请日：2014-05-30
申请人： HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
发明人： GE, Ning , YANG, Jianhua , PERNER, Frederick , NICKEL, Janice H.
IPC分类号： G11C13/00 , G11C7/10
CPC分类号： G11C13/004 , G11C13/0007 , G11C13/0023 , G11C2013/0045 , G11C2213/77
摘要： A memory controller includes a voltage control module that operates to isolate a target memristor of a memory crossbar array. The voltage control module applies a column voltage to a column line coupled to the target memristor, applies a first row voltage to all row lines not coupled to the target memristor and a second row voltage to a row line coupled to the target memristor, and senses a current through the target memristor to determine a state of the target memristor. The memory crossbar array includes a plurality of column lines, a plurality of row lines, a plurality of memristors, and a plurality of shorting switches. Each memristor is coupled between a unique combination of one column line and one row line. Each shorting switch has a high impedance resistor and a low impedance transistor, and each shorting switch is coupled to an end of a unique row line.
摘要翻译：存储器控制器包括电压控制模块，其操作以隔离存储器交叉开关阵列的目标忆阻器。电压控制模块对连接到目标忆阻器的列线施加列电压，对未耦合到目标忆阻器的所有行线施加第一行电压，将第二行电压施加到与目标忆阻器耦合的行线，并感测目前通过目标忆阻器确定目标忆阻器的状态。存储器横杆阵列包括多个列线，多条行线，多个忆阻器和多个短路开关。每个忆阻器耦合在一列和一行的独特组合之间。每个短路开关具有高阻抗电阻器和低阻抗晶体管，并且每个短路开关耦合到独特行线的端部。

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