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    • 1. 发明申请
    • TUNNELING-RESISTOR-JUNCTION-BASED MICROSCALE/NANOSCALE DEMULTIPLEXER ARRAYS
    • 基于隧穿 - 电阻 - 结点的微型/纳米级解复用器阵列
    • WO2007089802A2
    • 2007-08-09
    • PCT/US2007002577
    • 2007-01-30
    • HEWLETT PACKARD DEVELOPMENT COROBINETT WARRENSNIDER GREGORY SSTEWART DUNCANSTRAZNICKY JOSEPH
    • ROBINETT WARRENSNIDER GREGORY SSTEWART DUNCANSTRAZNICKY JOSEPH
    • G11C8/10G11C13/0023H03M13/51
    • Various embodiments of the present invention are directed to demultiplexers that include tunneling resistor nanowire junctions, and to nanowire addressing methods for reliably addressing nanowire signal lines in nanoscale and mixed-scale demultiplexers. In one embodimentof the present invention, an encoder-demulriplexer comprises a number of input signal lines and an encoder (1304) that generates an n-bit-constant-weight-code code-word internal address (1320, 1506, 1704) for each different input address (1318, 1702) received on the input signal lines. The encoder-demultiplexer also includes n microscale signal lines (1306-1311) on which an n-bit-constant-weight-code code word internal address is out put by the encoder and a number of encoder-demultiplexer-addressed nanowire signal lines interconnected with then microscale signal lines (1306-1311) via tunneling resistor junctions, the encoder-demultiplexer-addressed nanowire signal lines each associated with an n-bit-constant-weight-code code-word internal adress (1320, 1506, 1704).
    • 本发明的各种实施例涉及包括隧道电阻器纳米线结的解复用器,并且涉及用于在纳米级和混合尺度解复用器中可靠地寻址纳米线信号线的纳米线寻址方法。 在本发明的一个实施例中,编码器 - 解复用器包括多个输入信号线和编码器(1304),编码器(1304)为每个输入信号线生成n位恒定加权码字内部地址(1320,1506,1704) 在输入信号线上接收不同的输入地址(1318,1702)。 编码器 - 解复用器还包括n个微型信号线(1306-1311),编码器输出n位恒定加权码字内部地址,并且编码器 - 解复用器寻址的纳米线信号线互连 与经由隧道电阻器结的微米级信号线(1306-1311)相连,所述编码器 - 解复用器寻址的纳米线信号线均与n位恒定重量码码字内部地址(1320,1506,1704)相关联。
    • 2. 发明申请
    • COMPUTATIONAL NODES AND COMPUTATIONAL-NODE NETWORKS THAT INCLUDE DYNAMICAL-NANODEVICE CONNECTIONS
    • 包括动态 - 纳米设备连接的计算节点和计算节点网络
    • WO2008130645A3
    • 2008-12-11
    • PCT/US2008005048
    • 2008-04-18
    • HEWLETT PACKARD DEVELOPMENT COSNIDER GREGORY S
    • SNIDER GREGORY S
    • G06N3/02G06F15/18
    • G06N3/063
    • Embodiments of the present invention employ dynamical, nanoscale devices, including memristive connections (1102) between nanowires, for constructing parallel, distributed, dynamical computational networks and systems, including perceptron networks (Figure 9) and neural networks (Figure 8). In many embodiments of the present invention, neuron-like computational devices (2002) are constructed from silicon-based microscale and/or submicroscale components, and interconnected with one another by dynamical interconnections comprising nanowires (1104, 1106) and memristive connections (1102) between nanowires. In many massively parallel, distributed, dynamical computing systems, including the human brain, there may be a far greater number of interconnections than neuron-like computational nodes. Use of dynamical nanoscale devices for these connections results in enormous design, space, energy, and computational efficiencies.
    • 本发明的实施例采用动态纳米级器件,包括纳米线之间的忆阻连接(1102),用于构建并行,分布式,动态计算网络和包括感知器网络(图9)和神经网络(图8)的系统。 在本发明的许多实施例中,神经元样计算设备(2002)由硅基微尺度和/或亚微米部件构成,并且通过包括纳米线(1104,1106)和忆阻连接(1102)的动态互连彼此互连, 纳米线之间。 在许多大规模并行,分布式,动态计算系统(包括人类大脑)中,可能存在比神经元状计算节点更多的互连数。 对这些连接使用动态纳米级器件可以产生巨大的设计,空间,能量和计算效率。
    • 3. 发明申请
    • ACTIVE INTERCONNECTS AND CONTROL POINTS IN INTEGRATED CIRCUITS
    • 集成电路中的主动互连和控制点
    • WO2006115968A3
    • 2007-08-16
    • PCT/US2006014856
    • 2006-04-19
    • HEWLETT PACKARD DEVELOPMENT COWILLIAMS R STANLEYKUEKES PHILLIP JPERNER FREDERICK ASNIDER GREGORY SSTEWART DUNCAN
    • WILLIAMS R STANLEYKUEKES PHILLIP JPERNER FREDERICK ASNIDER GREGORY SSTEWART DUNCAN
    • H01L21/66
    • H05K7/1092H01L23/5228H01L2924/0002H01L2924/00
    • In various embodiments of the present invention, tunable resistors (1102) are introduced at the interconnect layer of the integrated circuits (102) in order to provide a means for adjusting internal voltage and/or current levels within the integrated circuit to repair defective components or to configure the integrated circuit following manufacture. For example, when certain internal components, such as transistors, do not have specified electronics characteristics due to manufacturing defects, adjustment of the variable resistances of the tunable resistors (1102) included in the interconnect layer of integrated circuits according to embodiments of the present invention can be used to adjust internal voltage and/or levels in order to ameliorate the defective components. In other cases, the tunable resistors may be used as switches to configure integrated circuit components, including individual transistors and logic gates as well as larger, hierarchically structured functional modules and domains. In some cases, components and modules may be turned off, while, in other cases, components and modules may be turned on.
    • 在本发明的各种实施例中,可调谐电阻器(1102)被引入集成电路(102)的互连层,以便提供用于调整集成电路内的内部电压和/或电流水平以修复有缺陷的部件或 配置后续制造的集成电路。 例如,当某些内部组件(例如晶体管)由于制造缺陷而没有指定的电子特性时,根据本发明的实施例调整包括在集成电路的互连层中的可调电阻器(1102)的可变电阻 可以用于调整内部电压和/或电平,以改善有缺陷的部件。 在其他情况下,可调谐电阻器可以用作开关以配置集成电路部件,包括单独的晶体管和逻辑门以及更大的分层结构的功能模块和域。 在某些情况下,可能会关闭组件和模块,而在其他情况下,可能会打开组件和模块。
    • 4. 发明申请
    • FPGA ARCHITECTURE AT CONVENTIONAL AND SUBMICRON SCALES
    • 常规和亚微米尺寸的FPGA架构
    • WO2007089914A2
    • 2007-08-09
    • PCT/US2007002805
    • 2007-01-30
    • HEWLETT PACKARD DEVELOPMENT COSNIDER GREGORY SKUEKES PHILIP J
    • SNIDER GREGORY SKUEKES PHILIP J
    • H03K19/177G11C13/02
    • H03K19/17748B82Y10/00B82Y30/00G11C8/10G11C13/0007G11C13/0014G11C2213/15G11C2213/34G11C2213/51G11C2213/77G11C2213/81H03K19/17728H03K19/1778
    • Reconfigurable logic devices (500) and methods of programming the devices are disclosed. The logic device includes a look-up table (600, 600') (LUT) and at least one storage element (570) configured for sampling LUT output signals (520). The LUT (600, 600') comprises a plurality of input signals (510), an array of programmable impedance devices (110) operably coupled to the input signals (510), and the LUT output signals (520). Each programmable impedance devices (110) in the array includes a first electrode (120) operably coupled to one of the input signals (520), a second electrode (130) disposed to form a junction (150) wherein the second electrode (130) at least partially overlaps the first electrode (120), and a programmable material (140) disposed between the first electrode (120) and the second electrode (130). The programmable material (140) operably couples the first electrode (120) and second electrode (130) such that each programmable impedance device (110) exhibits a non-volatile programmable impedance. The array may be configured as a one-dimensional array (700, 700') or two-dimensional array (610, 610').
    • 公开了可重新配置的逻辑设备(500)和对设备进行编程的方法。 逻辑器件包括被配置为对LUT输出信号(520)进行采样的查找表(600,600')(LUT)和至少一个存储元件(570)。 LUT(600,600')包括多个输入信号(510),可操作地耦合到输入信号(510)的可编程阻抗设备(110)阵列以及LUT输出信号(520)。 阵列中的每个可编程阻抗器件(110)包括可操作地耦合到输入信号(520)中的一个的第一电极(120),布置为形成结(150)的第二电极(130),其中第二电极 至少部分地与第一电极(120)重叠,以及设置在第一电极(120)和第二电极(130)之间的可编程材料(140)。 可编程材料(140)可操作地耦合第一电极(120)和第二电极(130),使得每个可编程阻抗设备(110)呈现非易失性可编程阻抗。 该阵列可以被配置为一维阵列(700,700')或二维阵列(610,610')。