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1. 发明申请

WO2008100687A1 MULTI-LAYER SOURCE/DRAIN STRESSOR 审中-公开
标题翻译：多层源/漏极压力源
公开(公告)号：WO2008100687A1
公开(公告)日：2008-08-21
申请号：PCT/US2008/051841
申请日：2008-01-24
申请人： FREESCALE SEMICONDUCTOR INC. , ZHANG, Da , DHANDAPANI, Veeraraghavan , GOEDEKE, Darren V. , HILDRETH, Jill C.
发明人： ZHANG, Da , DHANDAPANI, Veeraraghavan , GOEDEKE, Darren V. , HILDRETH, Jill C.
IPC分类号： H01L21/336
CPC分类号： H01L29/0847 , H01L29/165 , H01L29/66636 , H01L29/7834 , H01L29/7848
摘要： A method for forming a semiconductor device (10) includes forming a recess (26) in a source region and a recess (28) in a drain region of the semiconductor device. The method further includes forming a first semiconductor material layer (32) in the recess (26) in the source region and a second semiconductor material layer (34) in the recess (28) in the drain region, wherein each of the first semiconductor material layer (32) and the second semiconductor material layer (38) are formed using a stressor material having a first ratio of an atomic concentration of a first element and an atomic concentration of a second element, wherein the first element is silicon and a first level of concentration of a doping material. The method further includes forming additional semiconductor material layers (36, 38, 40, 42) overlying the first semiconductor material layer (32) and the second semiconductor material layer (34) that have a different ratio of the atomic concentration of the first element and the second element.
摘要翻译：用于形成半导体器件（10）的方法包括在半导体器件的源极区域和漏极区域中形成凹陷（26）和凹陷（28）。该方法还包括在源极区中的凹陷（26）中形成第一半导体材料层（32），并且在漏极区中形成凹陷（28）中的第二半导体材料层（34），其中第一半导体材料使用具有第一元素的原子浓度和第二元素的原子浓度的第一比率的应力源材料形成所述第一半导体层（32）和所述第二半导体材料层（38），其中所述第一元素是硅和第一水平浓度的掺杂材料。该方法还包括形成覆盖第一半导体材料层（32）和第二半导体材料层（34）的附加半导体材料层（36,38,40,42），所述附加半导体材料层具有不同的第一元素的原子浓度和第二个元素。

2. 发明申请

WO2007117775A2 SEMICONDUCTOR FABRICATION PROCESS USING ETCH STOP LAYER TO OPTIMIZE FORMATION OF SOURCE/DRAIN STRESSOR 审中-公开
标题翻译：使用蚀刻停止层的半导体制造工艺优化源/排水压力机的形成
公开(公告)号：WO2007117775A2
公开(公告)日：2007-10-18
申请号：PCT/US2007/062559
申请日：2007-02-22
申请人： FREESCALE SEMICONDUCTOR, INC. , ZHANG, Da , WHITE, Ted , NGUYEN, Bich, Yen
发明人： ZHANG, Da , WHITE, Ted , NGUYEN, Bich, Yen
IPC分类号： H01L21/336
CPC分类号： H01L29/7848 , H01L21/76254 , H01L21/76283 , H01L29/66772 , H01L29/78684
摘要： A semiconductor fabrication process includes forming an etch stop layer (ESL) (109) overlying a buried oxide (BOX) layer (102) and an active semiconductor layer (105) overlying the ESL. A gate electrode (112) is formed overlying the active semiconductor layer. Source/drain regions of the active semiconductor layer are etched to expose the ESL. Source/drain stressors (130) are formed on the ESL where the source/drain stressors strain the transistor channel (115). Forming the ESL may include epitaxially growing a silicon germanium ESL having a thickness of approximately 30 nm or less. Preferably a ratio of the active semiconductor layer etch rate to the ESL etch rate exceeds 10:1. A wet etch using a solution of NH4OH:H2O heated to a temperature of approximately 75° C may be used to etch the source/drain regions. The ESL may be silicon germanium having a first percentage of germanium. The source/drain stressors may be silicon germanium having a second percentage of germanium for P-type transistors, and they may be silicon carbon for N-type transistors.
摘要翻译：半导体制造工艺包括形成覆盖掩埋氧化物（BOX）层（102）和覆盖ESL的有源半导体层（105）的蚀刻停止层（ESL）（109）。形成覆盖有源半导体层的栅极（112）。蚀刻有源半导体层的源极/漏极区域以露出ESL。源极/漏极应力源（130）形成在源极/漏极应力源应变晶体管沟道（115）的ESL上。形成ESL可以包括外延生长厚度为约30nm或更小的硅锗ESL。优选地，有源半导体层蚀刻速率与ESL蚀刻速率的比率超过10:1。使用加热至约75℃温度的NH 4 OH:H 2溶液进行湿蚀刻可以用于蚀刻源/漏区。 ESL可以是具有第一百分比的锗的硅锗。源极/漏极应力源可以是对于P型晶体管具有第二百分比的锗的硅锗，并且它们可以是N型晶体管的硅碳。

3. 发明申请

WO2007092653A2 METHOD OF FORMING A SEMICONDUCTOR DEVICE 审中-公开
标题翻译：形成半导体器件的方法
公开(公告)号：WO2007092653A2
公开(公告)日：2007-08-16
申请号：PCT/US2007/060145
申请日：2007-01-05
申请人： FREESCALE SEMICONDUCTOR INC. , ZHANG, Da , NGUYEN, Bich-yen
发明人： ZHANG, Da , NGUYEN, Bich-yen
CPC分类号： H01L21/823842 , H01L21/823814 , H01L29/7848
摘要： A method for forming a semiconductor device includes providing a semiconductor substrate (12) having a first doped region and a second doped region, providing a dielectric (14) over the first doped region and the second doped region, and forming a first gate stack (26) over the dielectric over at least a portion of the first doped region. The first gate stack includes a metal portion (18) over the dielectric, a first in situ doped semiconductor portion (22) over the metal portion, and a first blocking cap (23) over the in situ doped semiconductor portion. The method further includes performing an implant to form source/drain regions adjacent the first gate stack, where the first blocking cap has a thickness sufficient to substantially block dopants from the implant from entering the first in situ doped semiconductor portion.
摘要翻译：一种用于形成半导体器件的方法包括提供具有第一掺杂区域和第二掺杂区域的半导体衬底（12），在第一掺杂区域和第二掺杂区域上提供电介质（14），并形成第一栅叠层 26）在第一掺杂区域的至少一部分上方的电介质上。第一栅极堆叠包括电介质上的金属部分（18），金属部分上的第一原位掺杂半导体部分（22）和位于原位掺杂半导体部分上的第一阻挡盖（23）。该方法还包括执行植入物以形成邻近第一栅极叠层的源极/漏极区域，其中第一阻挡盖具有足以基本上阻挡来自植入物的掺杂剂进入第一原位掺杂半导体部分的厚度。

4. 发明申请

WO2007053339A3 METHOD FOR FORMING A SEMICONDUCTOR STRUCTURE AND STRUCTURE THEREOF 审中-公开
公开(公告)号：WO2007053339A3
公开(公告)日：2007-05-10
申请号：PCT/US2006/041146
申请日：2006-10-20
申请人： FREESCALE SEMICONDUCTOR INC. , THEAN, Voon-Yew , CHEN, Jian , NGUYEN, Bich-Yen , SADAKA, Mariam G. , ZHANG, Da
发明人： THEAN, Voon-Yew , CHEN, Jian , NGUYEN, Bich-Yen , SADAKA, Mariam G. , ZHANG, Da
IPC分类号： H01L31/00
摘要： Forming a semiconductor structure includes providing a substrate (10) having a strained semiconductor layer (14) overlying an insulating layer (12), providing a first device region (18) for forming a first plurality of devices having a first conductivity type, providing a second device region (20) for forming a second plurality of devices having a second conductivity type, and thickening the strained semiconductor layer in the second device region so that the strained semiconductor layer in the second device region has less strain that the strained semiconductor layer in the first device region. Alternatively, forming a semiconductor structure includes providing a first region (18) having a first conductivity type, forming an insulating layer (34) overlying at least an active area (32) of the first region, anisotropically etching the insulating layer, and after anisotropically etching the insulating layer, deposing a gate electrode material (46) overlying at least a portion of the insulating layer.

5. 发明申请

WO2009011997A1 TRANSISTOR WITH DIFFERENTLY DOPED STRAINED CURRENT ELECTRODE REGION 审中-公开
标题翻译：具有不同掺杂应变电流电极区域的晶体管
公开(公告)号：WO2009011997A1
公开(公告)日：2009-01-22
申请号：PCT/US2008/066669
申请日：2008-06-12
申请人： FREESCALE SEMICONDUCTOR INC. , ZHANG, Da , FOISY, Mark C.
发明人： ZHANG, Da , FOISY, Mark C.
IPC分类号： H01L21/265
CPC分类号： H01L29/41783 , H01L29/165 , H01L29/665 , H01L29/66628 , H01L29/66636 , H01L29/7834 , H01L29/7848
摘要： A transistor is formed by providing a semiconductor layer (103) and forming a control electrode (105) overlying the semiconductor layer. A portion of the semiconductor layer is removed lateral to the control electrode to form a first recess (201) and a second recess (203) on opposing sides of the control electrode. A first stressor (301) is formed within the first recess and has a first doping profile. A second stressor (303) is formed within the second recess and has the first doping profile. A third stressor (401) is formed overlying the first stressor. The third stressor has a second doping profile that has a higher electrode current doping concentration than the first profile. A fourth stressor (403) overlying the second stressor is formed and has the second doping profile. A first current electrode and a second current electrode of the transistor include at least a portion of the third stressor and the fourth stressor, respectively.
摘要翻译：通过提供半导体层（103）并形成覆盖半导体层的控制电极（105）形成晶体管。半导体层的一部分被去除控制电极的侧面，以在控制电极的相对侧上形成第一凹部（201）和第二凹部（203）。第一应力器（301）形成在第一凹槽内并具有第一掺杂分布。第二应力器（303）形成在第二凹槽内并且具有第一掺杂分布。第三应力器（401）形成在第一应激源上方。第三应力源具有比第一轮廓具有更高的电极电流掺杂浓度的第二掺杂分布。形成覆盖第二应力源的第四应力器（403）并具有第二掺杂分布。晶体管的第一电流电极和第二电流电极分别包括第三应力源和第四应力源的至少一部分。

6. 发明申请

WO2006039037A1 DOUBLE GATE DEVICE HAVING A STRAINED CHANNEL 审中-公开
标题翻译：具有应变通道的双门设备
公开(公告)号：WO2006039037A1
公开(公告)日：2006-04-13
申请号：PCT/US2005/031000
申请日：2005-08-31
申请人： FREESCALE SEMICONDUCTOR, INC. , THEAN, Voon-Yew , SADAKA, Mariam, G. , WHITE, Ted, R. , BARR, Alexander, L. , KOLAGUNTA, Venkat, R. , NGUYEN, Bich-Yen , VARTANIAN, Victor, H. , ZHANG, Da
发明人： THEAN, Voon-Yew , SADAKA, Mariam, G. , WHITE, Ted, R. , BARR, Alexander, L. , KOLAGUNTA, Venkat, R. , NGUYEN, Bich-Yen , VARTANIAN, Victor, H. , ZHANG, Da
IPC分类号： H01L29/94
CPC分类号： H01L29/785 , H01L29/42392 , H01L29/66628 , H01L29/66742 , H01L29/7842 , H01L29/78621 , H01L29/78648 , H01L29/78687
摘要： A semiconductor device (10) is formed by positioning a gate (22) overlying a semiconductor layer (16) of preferably silicon. A semiconductor material (26) of, for example only, SiGe or Ge, is formed adjacent the gate over the semiconductor layer and over source/drain regions. A thermal process diffuses the stressor material into the semiconductor layer. Lateral diffusion occurs to cause the formation of a strained channel (17) in which a stressor material layer (30) is immediately adjacent the strained channel. Extension implants create source and drain implants from a first portion of the stressor material layer. A second portion of the stressor material layer remains in the channel between the strained channel and the source and drain implants. A heterojunction is therefore formed in the strained channel. In another form, oxidation of the stressor material occurs rather than extension implants to form the strained channel.
摘要翻译：半导体器件（10）通过将覆盖在优选硅的半导体层（16）上的栅极（22）定位而形成。例如仅SiGe或Ge的半导体材料（26）形成在半导体层上方的栅极和源极/漏极区域附近。热处理将应力源材料扩散到半导体层。发生横向扩散以形成应变通道（17），其中应力材料层（30）紧邻应变通道。延伸植入物从应力源材料层的第一部分产生源和漏植入物。应力源材料层的第二部分保留在应变通道和源极和漏极植入物之间的通道中。因此，在应变通道中形成异质结。在另一种形式中，发生应力源材料的氧化而不是延伸植入物以形成应变通道。

7. 发明申请

WO2007103609A2 SEMICONDUCTOR PROCESS INTEGRATING SOURCE/DRAIN STRESSORS AND INTERLEVEL DIELECTRIC LAYER STRESSORS 审中-公开
标题翻译：半导体工艺整合源/排水压力机和交互式电介质层压机
公开(公告)号：WO2007103609A2
公开(公告)日：2007-09-13
申请号：PCT/US2007/061841
申请日：2007-02-08
申请人： FREESCALE SEMICONDUCTOR INC. , ZHANG, Da , ADAMS, Vance H. , NGUYEN, Bich-Yen , GRUDOWSKI, Paul A.
发明人： ZHANG, Da , ADAMS, Vance H. , NGUYEN, Bich-Yen , GRUDOWSKI, Paul A.
IPC分类号： H01L21/336
CPC分类号： H01L29/7846 , H01L29/165 , H01L29/66636 , H01L29/66772 , H01L29/7843 , H01L29/7848 , H01L29/78654
摘要： A semiconductor fabrication process includes forming isolation structures (106) on either side of a transistor region, forming a gate structure (110) overlying the transistor region, removing source/drain regions (107) to form source/drain recesses (120), removing portions of the isolation structures to form recessed isolation structures (126), and filling the source/drain recesses with a source/drain stressor such as an epitaxially formed semiconductor. A lower surface of the source/drain recess is preferably deeper than an upper surface of the recessed isolation structure by approximately 10 to 30 nm. Filling the source/drain recesses may precede or follow forming the recessed isolation structures. An ILD stressor (140) is then deposited over the transistor region such that the ILD stressor is adjacent to sidewalls of the source/drain structure thereby coupling the ILD stressor to the source/drain stressor. The ILD stressor is preferably compressive or tensile silicon nitride and the source/drain structure is preferably silicon germanium or silicon carbon.
摘要翻译：半导体制造工艺包括在晶体管区域的任一侧上形成隔离结构（106），形成覆盖晶体管区域的栅极结构（110），去除源极/漏极区域（107）以形成源极/漏极凹部（120），去除隔离结构的部分以形成凹陷的隔离结构（126），并且用诸如外延形成的半导体的源极/漏极应力源填充源/漏极凹部。源极/漏极凹部的下表面优选比凹陷隔离结构的上表面深大约10至30nm。填充源极/漏极凹部可以在形成凹入的隔离结构之前或之后。然后将ILD应激源（140）沉积在晶体管区域上，使得ILD应力源与源极/漏极结构的侧壁相邻，从而将ILD应力源耦合到源极/漏极应力源。 ILD应力器优选为压缩或拉伸氮化硅，并且源极/漏极结构优选为硅锗或硅碳。

8. 发明申请

WO2006039038A2 METHOD FOR FORMING A SEMICONDUCTOR DEVICE HAVING A STRAINED CHANNEL AND A HETEROJUNCTION SOURCE/DRAIN 审中-公开
标题翻译：形成具有应变通道和异常源/漏极的半导体器件的方法
公开(公告)号：WO2006039038A2
公开(公告)日：2006-04-13
申请号：PCT/US2005/031001
申请日：2005-08-31
申请人： FREESCALE SEMICONDUCTOR, INC. , THEAN, Voon-Yew , SADAKA, Mariam G. , WHITE, Ted R. , BARR, Alexander L. , KOLAGUNTA, Venkat R. , NGUYEN, Bich-Yen , VARTANIAN, Victor H. , ZHANG, Da
发明人： THEAN, Voon-Yew , SADAKA, Mariam G. , WHITE, Ted R. , BARR, Alexander L. , KOLAGUNTA, Venkat R. , NGUYEN, Bich-Yen , VARTANIAN, Victor H. , ZHANG, Da
IPC分类号： H01L21/336
CPC分类号： H01L21/2254 , H01L29/665 , H01L29/66787 , H01L29/7848 , H01L29/785 , H01L29/78648
摘要： A semiconductor device (10) is formed by positioning a gate (22) overlying a semiconductor layer (16) of preferably silicon. A semiconductor material (26) of, for example only, SiGe or Ge, is formed adjacent the gate over the semiconductor layer and over source/drain regions. A thermal process diffuses the stressor material into the semiconductor layer. Lateral diffusion occurs to cause the formation of a strained channel (17) in which a stressor material layer (30) is immediately adjacent the strained channel. Extension implants create source and drain implants from a first portion of the stressor material layer. A second portion of the stressor material layer remains in the channel between the strained channel and the source and drain implants. A heterojunction is therefore formed in the strained channel. In another form, oxidation of the stressor material occurs rather than extension implants to form the strained channel.
摘要翻译：半导体器件（10）通过将覆盖在优选硅的半导体层（16）上的栅极（22）定位而形成。例如仅SiGe或Ge的半导体材料（26）形成在半导体层上方的栅极和源极/漏极区域附近。热处理将应力源材料扩散到半导体层。发生横向扩散以形成应变通道（17），其中应力材料层（30）紧邻应变通道。延伸植入物从应力源材料层的第一部分产生源和漏植入物。应力源材料层的第二部分保留在应变通道和源极和漏极植入物之间的通道中。因此，在应变通道中形成异质结。在另一种形式中，发生应力源材料的氧化而不是延伸植入物以形成应变通道。

9. 发明申请

WO2006020282A1 STRAINED SEMICONDUCTOR DEVICES AND METHOD FOR FORMING AT LEAST A PORTION THEREOF 审中-公开
标题翻译：应变半导体器件和形成至少一个部分的方法
公开(公告)号：WO2006020282A1
公开(公告)日：2006-02-23
申请号：PCT/US2005/025536
申请日：2005-07-15
申请人： FREESCALE SEMICONDUCTOR, INC. , ZHANG, Da , GOOLSBY, Brian, J. , LUCKOWSKI, Eric,D. , NGUYEN, Bich-Yen , SADAKA, Mariam, G. , THEAN, Voon-Yew , WHITE, Ted, R.
发明人： ZHANG, Da , GOOLSBY, Brian, J. , LUCKOWSKI, Eric,D. , NGUYEN, Bich-Yen , SADAKA, Mariam, G. , THEAN, Voon-Yew , WHITE, Ted, R.
IPC分类号： H01L21/336
CPC分类号： H01L29/7842 , H01L29/165 , H01L29/665 , H01L29/66628 , H01L29/66636 , H01L29/66651 , H01L29/66742 , H01L29/7834 , H01L29/7848 , H01L29/78687
摘要： A method for forming at least a portion of a semiconductor device (10, 50) includes providing a substrate (12) and epitaxially forming an etch stop layer (14) over the substrate. A first layer (16) is provided over the etch stop layer, wherein the first layer is selectively etchable with regard to the etch stop layer. A structure (20) is provided over a region of the first layer, wherein the region is not all of the first layer. In addition, the method includes etching at least a portion (28, 52) of the first layer that is outside of the region, wherein the etch stop layer is used an as etch stop. A strained layer (36, 54) is epitaxially grown in the etch-recessed region.
摘要翻译：用于形成半导体器件（10,50）的至少一部分的方法包括提供衬底（12）并在衬底上外延形成蚀刻停止层（14）。第一层（16）设置在蚀刻停止层上方，其中第一层相对于蚀刻停止层可选择性地蚀刻。在第一层的区域上提供结构（20），其中该区域不是全部第一层。此外，该方法包括蚀刻在区域外部的第一层的至少一部分（28,52），其中蚀刻停止层用作蚀刻停止。在蚀刻凹陷区域中外延生长应变层（36,54）。

10. 发明申请

WO2009123788A1 METHOD OF FORMING A SEMICONDUCTOR DEVICE USING STRESS MEMORIZATION 审中-公开
标题翻译：使用应力记忆形成半导体器件的方法
公开(公告)号：WO2009123788A1
公开(公告)日：2009-10-08
申请号：PCT/US2009/033187
申请日：2009-02-05
申请人： FREESCALE SEMICONDUCTOR INC. , ZHANG, Da , HOBBS, Christopher C. , SAMAVEDAM, Srikanth B.
发明人： ZHANG, Da , HOBBS, Christopher C. , SAMAVEDAM, Srikanth B.
IPC分类号： H01L21/336 , H01L29/78
CPC分类号： H01L21/324 , H01L21/823412 , H01L29/045 , H01L29/6659 , H01L29/7833 , H01L29/7847
摘要： A stress memorization technique (SMT) film (44) is deposited over a semiconductor device (14). The SMT film is annealed with a low thermal budget anneal that is sufficient to create and transfer the stress of the SMT film to the semiconductor device. The SMT film is then removed. After the SMT film is removed, a second anneal is applied to the semiconductor device sufficiently long and at a sufficiently high temperature to activate dopants implanted for forming device source/drains (28, 30). The result of this approach is that there is minimal gate dielectric (22) growth in the channel along the border of the channel.
摘要翻译：应力记忆技术（SMT）膜（44）沉积在半导体器件（14）上。 SMT薄膜通过低热预算退火进行退火，该退火足以产生并将SMT薄膜的应力转移到半导体器件。然后去除SMT膜。在去除SMT膜之后，对半导体器件进行足够长的时间并在足够高的温度下进行第二退火以激活植入用于形成器件源极/漏极（28,30）的掺杂剂。这种方法的结果是沿着通道边界的通道中存在最小的栅极电介质（22）生长。

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