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1. 发明申请

WO2007130151A2 SOI ACTIVE LAYER WITH DIFFERENT SURFACE ORIENTATION 审中-公开
标题翻译：具有不同表面方位的SOI主动层
公开(公告)号：WO2007130151A2
公开(公告)日：2007-11-15
申请号：PCT/US2006/061274
申请日：2006-11-28
申请人： FREESCALE SEMICONDUCTOR INC. , ADETUTU, Olubunmi O. , JONES, Robert E. , WHITE, Ted R.
发明人： ADETUTU, Olubunmi O. , JONES, Robert E. , WHITE, Ted R.
IPC分类号： H01L21/00
CPC分类号： H01L21/76254 , H01L21/02002
摘要： A wafer having an SOI configuration and active regions having different surface orientations for different channel type transistors. In one example, semiconductor structures (201, 203, 205) having a first surface orientation are formed on a donor wafer (101). Semiconductor structures (401, 403, 405) having a second surface orientation are formed on a second wafer (301). Receptor openings are formed on the second wafer (301). The semiconductor structures having the first surface orientation are located in the receptor openings and transferred to the second wafer. The resultant wafer has semiconductor regions having a first surface orientation for a first channel type of transistor and semiconductor regions having a second surface orientation for a second channel type transistor.
摘要翻译：具有SOI配置的晶片和对不同沟道型晶体管具有不同表面取向的有源区。在一个示例中，在施主晶片（101）上形成具有第一表面取向的半导体结构（201,203,205）。具有第二表面取向的半导体结构（401,403,405）形成在第二晶片（301）上。受体开口形成在第二晶片（301）上。具有第一表面取向的半导体结构位于接收器开口中并被转移到第二晶片。所得到的晶片具有用于第一沟道型晶体管的具有第一表面取向的半导体区域和具有用于第二沟道型晶体管的第二表面取向的半导体区域。

2. 发明申请

WO2006107419A3 METHOD OF MAKING A DUAL STRAINED CHANNEL SEMICONDUCTOR DEVICE 审中-公开
公开(公告)号：WO2006107419A3
公开(公告)日：2006-10-12
申请号：PCT/US2006/005471
申请日：2006-02-16
申请人： FREESCALE SEMICONDUCTOR, INC. , SADAKA, Mariam G. , BARR, Alexander L. , JOVANOVIC, Dejan , NGUYEN, Bich-Yen , THEAN, Voon-Yew , THOMAS, Shawn G. , WHITE, Ted R.
发明人： SADAKA, Mariam G. , BARR, Alexander L. , JOVANOVIC, Dejan , NGUYEN, Bich-Yen , THEAN, Voon-Yew , THOMAS, Shawn G. , WHITE, Ted R.
IPC分类号： H01L21/8238
摘要： According to the embodiments to the present disclosure, the process of making a dual strained channel semiconductor device (10) includes integrating strained Si (16) and compressed SiGe (28) with trench isolation (24) for achieving a simultaneous NMOS and PMOS performance enhancement. As described herein, the integration of NMOS and PMOS can be implemented in several ways to achieve NMOS and PMOS channels compatible with shallow trench isolation.

3. 发明申请

WO2006107419A2 METHOD OF MAKING A DUAL STRAINED CHANNEL SEMICONDUCTOR DEVICE 审中-公开
标题翻译：制造双应变通道半导体器件的方法
公开(公告)号：WO2006107419A2
公开(公告)日：2006-10-12
申请号：PCT/US2006005471
申请日：2006-02-16
申请人： FREESCALE SEMICONDUCTOR INC , SADAKA MARIAM G , BARR ALEXANDER L , JOVANOVIC DEJAN , NGUYEN BICH-YEN , THEAN VOON-YEW , THOMAS SHAWN G , WHITE TED R
发明人： SADAKA MARIAM G , BARR ALEXANDER L , JOVANOVIC DEJAN , NGUYEN BICH-YEN , THEAN VOON-YEW , THOMAS SHAWN G , WHITE TED R
IPC分类号： H01L21/8238
CPC分类号： H01L29/1054 , H01L21/823807 , H01L21/823878 , H01L21/84 , H01L27/1203
摘要： According to the embodiments to the present disclosure, the process of making a dual strained channel semiconductor device (10) includes integrating strained Si (16) and compressed SiGe (28) with trench isolation (24) for achieving a simultaneous NMOS and PMOS performance enhancement. As described herein, the integration of NMOS and PMOS can be implemented in several ways to achieve NMOS and PMOS channels compatible with shallow trench isolation.
摘要翻译：根据本公开的实施例，制造双应变通道半导体器件（10）的过程包括将应变Si（16）和压缩SiGe（28）与沟槽隔离（24）集成，以实现同时的NMOS和PMOS性能增强。如本文所述，NMOS和PMOS的集成可以以几种方式实现，以实现与浅沟槽隔离兼容的NMOS和PMOS沟道。

4. 发明申请

WO2006104549A1 DUAL METAL GATE ELECTRODE SEMICONDUCTOR FABRICATION PROCESS AND STRUCTURE THEREOF 审中-公开
标题翻译：双金属电极电极半导体制造工艺及其结构
公开(公告)号：WO2006104549A1
公开(公告)日：2006-10-05
申请号：PCT/US2006/002648
申请日：2006-01-25
申请人： FREESCALE SEMICONDUCTOR, INC. , WHITE, Ted R. , ADETUTU, Olubunmi O. , JONES, Robert E.
发明人： WHITE, Ted R. , ADETUTU, Olubunmi O. , JONES, Robert E.
IPC分类号： H01L21/302 , H01L21/336 , H01L21/461 , H01L21/8238 , H01L27/01 , H01L27/12 , H01L29/76 , H01L29/94 , H01L31/062 , H01L31/119 , H01L31/0392 , H01L31/113
CPC分类号： H01L21/823842
摘要： A semiconductor fabrication process includes patterning a first gate electrode layer (112) overlying a gate dielectric (110). A second gate electrode layer (120) is formed overlying the first gate electrode layer and the gate dielectric. Portions of the second gate electrode layer overlying the first gate electrode layer are removed until the first and second gate electrode layers have the same thickness. A third gate electrode layer (130) may be formed overlying the first and second gate electrode layers. The first gate electrode layer (112) may comprise TiN and reside primarily overlying PMOS regions while the second gate electrode layer (120) may comprise TaC or TaSiN and primarily overlie NMOS regions. Removing portions of the second gate electrode layer (120) may include performing a chemical mechanical process (CMP) without masking the second gate electrode layer or forming a resist mask and etching exposed portions of the second gate electrode layer (120).
摘要翻译：半导体制造工艺包括图案化覆盖在栅极电介质（110）上的第一栅电极层（112）。第二栅极电极层（120）形成在第一栅极电极层和栅极电介质上。去除覆盖在第一栅极电极层上的第二栅极电极层的部分，直到第一和第二栅电极层具有相同的厚度。可以形成第三栅极电极层（130），覆盖第一和第二栅电极层。第一栅极电极层（112）可以包括TiN并且主要驻留在PMOS区域上，而第二栅电极层（120）可以包括TaC或TaSiN，并且主要覆盖NMOS区域。去除第二栅极电极层（120）的部分可以包括在不掩蔽第二栅电极层或形成抗蚀剂掩模并蚀刻第二栅电极层（120）的暴露部分的情况下执行化学机械处理（CMP）。

5. 发明申请

WO2006039037A1 DOUBLE GATE DEVICE HAVING A STRAINED CHANNEL 审中-公开
标题翻译：具有应变通道的双门设备
公开(公告)号：WO2006039037A1
公开(公告)日：2006-04-13
申请号：PCT/US2005/031000
申请日：2005-08-31
申请人： FREESCALE SEMICONDUCTOR, INC. , THEAN, Voon-Yew , SADAKA, Mariam, G. , WHITE, Ted, R. , BARR, Alexander, L. , KOLAGUNTA, Venkat, R. , NGUYEN, Bich-Yen , VARTANIAN, Victor, H. , ZHANG, Da
发明人： THEAN, Voon-Yew , SADAKA, Mariam, G. , WHITE, Ted, R. , BARR, Alexander, L. , KOLAGUNTA, Venkat, R. , NGUYEN, Bich-Yen , VARTANIAN, Victor, H. , ZHANG, Da
IPC分类号： H01L29/94
CPC分类号： H01L29/785 , H01L29/42392 , H01L29/66628 , H01L29/66742 , H01L29/7842 , H01L29/78621 , H01L29/78648 , H01L29/78687
摘要： A semiconductor device (10) is formed by positioning a gate (22) overlying a semiconductor layer (16) of preferably silicon. A semiconductor material (26) of, for example only, SiGe or Ge, is formed adjacent the gate over the semiconductor layer and over source/drain regions. A thermal process diffuses the stressor material into the semiconductor layer. Lateral diffusion occurs to cause the formation of a strained channel (17) in which a stressor material layer (30) is immediately adjacent the strained channel. Extension implants create source and drain implants from a first portion of the stressor material layer. A second portion of the stressor material layer remains in the channel between the strained channel and the source and drain implants. A heterojunction is therefore formed in the strained channel. In another form, oxidation of the stressor material occurs rather than extension implants to form the strained channel.
摘要翻译：半导体器件（10）通过将覆盖在优选硅的半导体层（16）上的栅极（22）定位而形成。例如仅SiGe或Ge的半导体材料（26）形成在半导体层上方的栅极和源极/漏极区域附近。热处理将应力源材料扩散到半导体层。发生横向扩散以形成应变通道（17），其中应力材料层（30）紧邻应变通道。延伸植入物从应力源材料层的第一部分产生源和漏植入物。应力源材料层的第二部分保留在应变通道和源极和漏极植入物之间的通道中。因此，在应变通道中形成异质结。在另一种形式中，发生应力源材料的氧化而不是延伸植入物以形成应变通道。

6. 发明申请

WO2005034230A1 SEMICONDUCTOR STRUCTURE WITH DIFFERENT LATTICE CONSTANT MATERIALS AND METHOD FOR FORMING THE SAME 审中-公开
标题翻译：具有不同厚度常数材料的半导体结构及其形成方法
公开(公告)号：WO2005034230A1
公开(公告)日：2005-04-14
申请号：PCT/US2004/031516
申请日：2004-09-27
申请人： FREESCALE SEMICONDUCTOR, INC. , LIU, Chun-Li , BARR, Alexander, L. , GRANT, John, M. , NGUYEN, Bich-Yen , ORLOWSKI, Marius, K. , STEPHENS, Tab, A. , WHITE, Ted, R. , THOMAS, Shawn, G.
发明人： LIU, Chun-Li , BARR, Alexander, L. , GRANT, John, M. , NGUYEN, Bich-Yen , ORLOWSKI, Marius, K. , STEPHENS, Tab, A. , WHITE, Ted, R. , THOMAS, Shawn, G.
IPC分类号： H01L21/335
CPC分类号： H01L29/1054 , H01L21/0237 , H01L21/02381 , H01L21/0245 , H01L21/02507 , H01L21/02532 , H01L21/02639 , H01L21/02647 , H01L29/04 , H01L29/665 , H01L29/7833
摘要： A semiconductor structure (10) includes a substrate comprising a first relaxed semiconductor material with a first lattice constant. A semiconductor device layer (34) overlies the substrate, wherein the semiconductor device layer includes a second relaxed semiconductor material (22) with a second lattice constant different from the first lattice constant. In addition, a dielectric layer is interposed between the substrate and the semiconductor device layer, wherein the dielectric layer is interposed between the substrate and the semiconductor device layer, wherein the dielectric layer includes a programmed transition zone disposed within the dielectric layer for transitioning between the first lattice constant and the second lattice constant. The programmed transition zone includes a plurality of layers, adjoining ones of the plurality of layers having different lattice constants with one of the adjoining ones having a first thickness exceeding a first critical thickness required to form defects and another of the adjoining ones having a second thickness not exceeding a second critical thickness. Each adjoining layer of the plurality of layers forms an interface for promoting defects in the transition zone to migrate to and terminate on an edge of the programmed transition zone. A method of making the same is also enclosed.
摘要翻译：半导体结构（10）包括具有第一晶格常数的第一松弛半导体材料的衬底。半导体器件层（34）覆盖在衬底上，其中半导体器件层包括具有不同于第一晶格常数的第二晶格常数的第二松弛半导体材料（22）。另外，在基板和半导体器件层之间插入电介质层，其中介电层介于基板和半导体器件层之间，其中介电层包括布置在电介质层内的过渡区，用于在第一晶格常数和第二晶格常数。编程的过渡区域包括多个层，多个层中相邻的层具有不同的晶格常数，其中相邻的层之一具有超过形成缺陷所需的第一临界厚度的第一厚度，而另一层具有第二厚度不超过第二临界厚度。多个层中的每个相邻层形成用于促进过渡区中的缺陷迁移到并终止于编程的过渡区的边缘的界面。也包括制作该方法的方法。

7. 发明申请

WO0067522A3 REFLEXION-TYPE LOUDSPEAKER SYSTEM 审中-公开
标题翻译： REFLEXION型扬声器系统
公开(公告)号：WO0067522A3
公开(公告)日：2001-06-28
申请号：PCT/CA0000466
申请日：2000-05-01
申请人： BRAND MARKETING & COMM GROUP I , WHITE TED E , YAP RAYMOND A , VANIER CHRIS , DOELL MIKE H , CASTALDI JOSEPH A , BRYANT WILLIAM
发明人： WHITE TED E , YAP RAYMOND A , VANIER CHRIS , DOELL MIKE H , CASTALDI JOSEPH A , BRYANT WILLIAM
IPC分类号： H04R1/34 , H04R1/32
CPC分类号： H04R1/345
摘要： A reflection speaker assembly (10) includes a cylindrical body (12) having an aperture (18), a reflector (21), a tweeter type speaker (25) for higher frequencies and a midrange type speaker (11) for middle frequencies. The tweeter (25) is located on the wall (13) of the cylindrical body. The midrange (11) is mounted inside the body. The aperture (18) is located between a base (16) containing the reflector (21) and a housing (14) containing the midrange speaker. In one embodiment, the reflector is positioned opposite the midrange speaker in the body and comprises a flat surface set at an angle relative to the midrange speaker. In a second embodiment, the reflector is positioned opposite the midrange speaker in the body and is roughly conical. Sound waves radiated from the midrange speaker are reflected by the reflector, and are dissipated to the outside through the aperture.
摘要翻译：反射扬声器组件（10）包括具有孔（18），反射器（21），用于更高频率的高音扬声器（25）和用于中频的中音扬声器（11）的圆柱体（12）。高音单元（25）位于圆柱体的壁（13）上。中档（11）安装在身体内。孔（18）位于包含反射器（21）的基座（16）和容纳中音扬声器的壳体（14）之间。在一个实施例中，反射器与主体中的中音扬声器相对定位并且包括相对于中音扬声器以一定角度设置的平坦表面。在第二实施例中，反射器与身体中的中音扬声器相对定位，并且大致呈锥形。从中音扬声器辐射的声波被反射器反射，并通过光圈消散到外部。

8. 发明申请

WO2007130151A3 SOI ACTIVE LAYER WITH DIFFERENT SURFACE ORIENTATION 审中-公开
标题翻译：具有不同表面方位的SOI主动层
公开(公告)号：WO2007130151A3
公开(公告)日：2008-03-27
申请号：PCT/US2006061274
申请日：2006-11-28
申请人： FREESCALE SEMICONDUCTOR INC , ADETUTU OLUBUNMI O , JONES ROBERT E , WHITE TED R
发明人： ADETUTU OLUBUNMI O , JONES ROBERT E , WHITE TED R
IPC分类号： H01L21/00
CPC分类号： H01L21/76254 , H01L21/02002
摘要： A wafer having an SOI configuration and active regions having different surface orientations for different channel type transistors. In one example, semiconductor structures (201, 203, 205) having a first surface orientation are formed on a donor wafer (101). Semiconductor structures (401, 403, 405) having a second surface orientation are formed on a second wafer (301). Receptor openings are formed on the second wafer (301). The semiconductor structures having the first surface orientation are located in the receptor openings and transferred to the second wafer. The resultant wafer has semiconductor regions having a first surface orientation for a first channel type of transistor and semiconductor regions having a second surface orientation for a second channel type transistor.
摘要翻译：具有SOI配置的晶片和对不同沟道型晶体管具有不同表面取向的有源区。在一个示例中，在施主晶片（101）上形成具有第一表面取向的半导体结构（201,203,205）。具有第二表面取向的半导体结构（401,403,405）形成在第二晶片（301）上。受体开口形成在第二晶片（301）上。具有第一表面取向的半导体结构位于接收器开口中并被转移到第二晶片。所得到的晶片具有用于第一沟道型晶体管的具有第一表面取向的半导体区域和具有用于第二沟道型晶体管的第二表面取向的半导体区域。

9. 发明申请

WO2006103066A1 A SEMICONDUCTOR DEVICE FEATURING AN ARCHED STRUCTURE STRAINED SEMICONDUCTOR LAYER 审中-公开
标题翻译：具有结构构造应变半导体层的半导体器件
公开(公告)号：WO2006103066A1
公开(公告)日：2006-10-05
申请号：PCT/EP2006/002893
申请日：2006-03-30
申请人： PAUL SCHERRER INSTITUT , GARCHING INNOVATIONS GMBH , NGUYEN, Bich-Yen , THOMAS, Shawn, G. , CERGEL, Lubomir , SADAKA, Mariam, G. , THEAN, Voon-Yew , WENNEKERS, Peter , WHITE, Ted, R. , WILD, Andreas, A. , GRUETZMACHER, Detlev , SCHMIDT, Oliver, G.
发明人： NGUYEN, Bich-Yen , THOMAS, Shawn, G. , CERGEL, Lubomir , SADAKA, Mariam, G. , THEAN, Voon-Yew , WENNEKERS, Peter , WHITE, Ted, R. , WILD, Andreas, A. , GRUETZMACHER, Detlev , SCHMIDT, Oliver, G.
CPC分类号： H01L29/78696 , H01L29/0649 , H01L29/42392 , H01L29/66772 , H01L29/7842 , H01L29/78648 , H01L29/78687
摘要： A semiconductor device includes a mechanically strained channel, wherein the channel comprises of a single crystalline structure of a strained semiconductor layer having a non-linear geometry, the non-linear geometry including a portion of an arch shape. The semiconductor device further includes a dielectric layer, wherein a first portion of the channel is disposed overlying a point location within the dielectric layer and a second portion of the channel is disposed overlying a portion of the dielectric layer proximate to and outside of the point location. Ih addition, a gate is disposed proximate to the channel for controlling current flow through the channel between first and second current handling electrodes that are coupled to the channel.
摘要翻译：半导体器件包括机械应变通道，其中所述通道包括具有非线性几何形状的应变半导体层的单晶结构，所述非线性几何形状包括拱形形状的一部分。所述半导体器件还包括介电层，其中所述沟道的第一部分设置在所述电介质层内的点位置上方，并且所述沟道的第二部分设置在所述电介质层的靠近所述点位置和外侧的部分上方。此外，栅极靠近通道设置，用于控制电流通过耦合到通道的第一和第二电流处理电极之间的通道。

10. 发明申请

WO2006023492A1 GRADED SEMICONDUCTOR LAYER 审中-公开
标题翻译：分级半导体层
公开(公告)号：WO2006023492A1
公开(公告)日：2006-03-02
申请号：PCT/US2005/029113
申请日：2005-08-08
申请人： FREESCALE SEMICONDUCTOR, INC. , SADAKA, Mariam G. , THOMAS, Shawn G. , WHITE, Ted R. , LIU, Chun-Li , BARR, Alexander L. , NGUYEN, Bich-Yen , THEAN, Voon-Yew
发明人： SADAKA, Mariam G. , THOMAS, Shawn G. , WHITE, Ted R. , LIU, Chun-Li , BARR, Alexander L. , NGUYEN, Bich-Yen , THEAN, Voon-Yew
IPC分类号： H01L21/84
CPC分类号： H01L29/78687 , H01L29/1054 , H01L29/6659 , H01L29/66742
摘要： A process for forming a semiconductor device. The process includes forming a template layer (207) for forming a layer (305) of strained silicon. In one example a layer (107) of graded silicon germanium is formed where the germanium is at a higher concentration at the lower portion and at a lower concentration at a top portion. When subject to a condensation process, the germanium of the top portion of the layer diffuses to a remaining portion of the silicon germanium layer. Because the silicon germanium layer has a higher concentration of germanium at lower portions, germanium pile up after condensation may be reduced at the upper portion of the remaining portion of the silicon germanium layer.
摘要翻译：一种形成半导体器件的方法。该方法包括形成用于形成应变硅层（305）的模板层（207）。在一个示例中，形成梯度硅锗的层（107），其中锗在下部具有较高的浓度，在顶部处的浓度较低。当进行冷凝处理时，层的顶部的锗扩散到硅锗层的剩余部分。由于硅锗层在下部具有较高的锗浓度，所以在硅锗层的剩余部分的上部可以减少在冷凝后堆积的锗。

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