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1. 发明申请

WO2012069881A1 METHOD AND APPARATUS FOR MANAGING POWER IN A MULTI-CORE PROCESSOR 审中-公开
标题翻译：用于在多核处理器中管理功率的方法和装置
公开(公告)号：WO2012069881A1
公开(公告)日：2012-05-31
申请号：PCT/IB2010/055416
申请日：2010-11-25
申请人： FREESCALE SEMICONDUCTOR, INC. , PRIEL, Michael , ROZEN, Anton , SMOLYANSKY, Leonid
发明人： PRIEL, Michael , ROZEN, Anton , SMOLYANSKY, Leonid
IPC分类号： G06F1/28 , G06F1/30 , G06F9/28 , G06F1/04
CPC分类号： G06F1/26 , G06F1/324 , G06F1/3296 , G06F9/5094 , Y02D10/126 , Y02D10/172 , Y02D10/22
摘要： There is provided a method of managing power in a multi-core data processing system having two or more processing cores, comprising determining usage characteristics for the two or more processing cores within the multi-core processing unit, and dependent on the determined usage characteristics, adapting a frequency or voltage supplied to each of the two or more processing cores, and/or adapting enablement signals provided to each of the two or more processing cores. There is also provided an apparatus for carrying out the disclosed method.
摘要翻译：提供了一种在具有两个或多个处理核心的多核数据处理系统中管理电力的方法，包括确定多核处理单元内的两个或多个处理核心的使用特性，并且取决于确定的使用特性，适应提供给两个或多个处理核心中的每一个的频率或电压，和/或调整提供给两个或多个处理核心中的每一个的启用信号。还提供了一种用于实施所公开的方法的装置。

2. 发明申请

WO2007148159A1 A METHOD AND DEVICE FOR POWER MANAGEMENT 审中-公开
标题翻译：一种用于电力管理的方法和装置
公开(公告)号：WO2007148159A1
公开(公告)日：2007-12-27
申请号：PCT/IB2006/052033
申请日：2006-06-22
申请人： FREESCALE SEMICONDUCTOR, INC. , ROZEN, Anton , PRIEL, Michael , SMOLYANSKY, Leonid
发明人： ROZEN, Anton , PRIEL, Michael , SMOLYANSKY, Leonid
IPC分类号： G06F1/32
CPC分类号： G06F1/3203 , G06F1/3215 , G06F1/3228 , G06F1/324 , G06F1/3296 , Y02D10/126 , Y02D10/172
摘要： A device and method for power management. The method includes receiving an indication about a load of a circuit (610), determining (620) at least one long-term activation parameter in view of a circuit load pattern during at least one long period; determining (630) at least one short-term activation parameter in response to an expected short period load change of the circuit; and providing (640) at least one clock signal and at least one supply voltage in response to the long-term activation parameter and in response to the short-term supply parameter.
摘要翻译：一种用于电源管理的设备和方法。该方法包括接收关于电路的负载的指示（610），在至少一个长周期期间考虑到电路负载模式来确定（620）至少一个长期激活参数; 响应于所述电路的预期短周期负载变化来确定（630）至少一个短期激活参数; 以及响应于所述长期激活参数并响应于所述短期供应参数而提供（640）至少一个时钟信号和至少一个电源电压。

3. 发明申请

WO2006120507A1 METHOD FOR POWER REDUCTION AND A DEVICE HAVING POWER REDUCTION CAPABILITIES 审中-公开
标题翻译：降低功率的方法和具有降低功率的装置
公开(公告)号：WO2006120507A1
公开(公告)日：2006-11-16
申请号：PCT/IB2005/051539
申请日：2005-05-11
申请人： FREESCALE SEMICONDUCTOR, INC. , PRIEL, Michael , KUZMIN, Dan , ROZEN, Anton , SMOLYANSKY, Leonid
发明人： PRIEL, Michael , KUZMIN, Dan , ROZEN, Anton , SMOLYANSKY, Leonid
IPC分类号： G06F1/32
CPC分类号： G06F1/3225 , G06F1/3275 , G06F1/3287 , G06F12/0804 , G06F12/0864 , G06F2212/1028 , Y02D10/13 , Y02D10/14 , Y02D10/171 , Y02D50/20
摘要： A method (100) for power reduction, the method includes determining (140) whether to power down the at least portion of the component in response to a relationship between an estimated power gain and an estimated power loss resulting from powering down the at least portion of the component during the low power mode, and selectively (150) providing power to at least a portion of a component of an integrated circuit during a low power mode. A device (10) having power reduction capabilities, the device includes power switching circuitry (30) adapted to selectively provide power to at least a portion (22, 24, 26, 28) of a component (20) of the device during a low power mode, and a power management circuitry (40) adapted to determine whether to power down at least the portion (22, 24, 26, 28) of the component during a low power mode in response to a relationship between an estimated power gain and an estimated power loss resulting from powering down the at least portion (22, 24, 26, 28) of the component (20) during the low power.
摘要翻译：一种用于功率降低的方法（100），所述方法包括确定（140）响应于所估计的功率增益与由所述至少部分断电而产生的估计功率损耗之间的关系来确定（140）所述部件的至少部分的掉电在低功率模式期间选择性地（150）向集成电路的部件的至少一部分提供电力。一种具有功率降低能力的设备（10），该设备包括功率切换电路（30），其适于在低电平期间选择性地向设备的部件（20）的一部分（22,24,26,28）提供功率功率模式和功率管理电路（40），其适于在低功率模式期间响应于估计的功率增益和功率模式之间的关系来确定是否在低功率模式期间对组件的至少部分（22,24,26,28）在低功率期间由部件（20）的至少部分（22,24,26,28）断电导致的估计的功率损耗。

4. 发明申请

WO2014080244A1 PROCESSOR CORE ARRANGEMENT, COMPUTING SYSTEM AND METHODS FOR DESIGNING AND OPERATING A PROCESSOR CORE ARRANGEMENT 审中-公开
标题翻译：处理器核心安排，计算系统和设计和操作处理器核心安排的方法
公开(公告)号：WO2014080244A1
公开(公告)日：2014-05-30
申请号：PCT/IB2012/056630
申请日：2012-11-22
申请人： FREESCALE SEMICONDUCTOR, INC. , ROZEN, Anton , PRIEL, Michael , SMOLYANSKY, Leonid , SOFER, Sergey
发明人： ROZEN, Anton , PRIEL, Michael , SMOLYANSKY, Leonid , SOFER, Sergey
IPC分类号： G06F9/46 , G06F9/455
CPC分类号： G06F9/30189 , G06F1/324 , G06F9/28 , G06F9/48 , G06F17/5045 , G06F2217/68 , G06F2217/78 , Y02D10/126
摘要： The invention relates to a method of designing a processor core arrangement (10) which comprises a first processor core (12) for operation at a first operation frequency and having an associated first leakage and a second processor core (12) for operation at a second operation frequency lower than the first operation frequency and having an associated second leakage lower than the first leakage. The processor core arrangement (10) is capable of switching from the first processor core (12) to the second processor core (14) and vice versa. The method comprises: simulating said processor core arrangement to determine a reference leakage of said first processor core and said second processor core, said first processor core having an SRPG feature in said simulation; and setting said second operation frequency such that the sum of said first leakage and said second leakage is substantially equal to said reference leakage. The method further comprises providing said first processor core (12) and said second processor core (14) but not providing said SRPG feature.
摘要翻译：本发明涉及一种设计处理器核心布置（10）的方法，该处理器核心布置（10）包括用于以第一操作频率操作并具有相关联的第一泄漏的第一处理器核心（12）和用于在第二操作频率下操作的第二处理器核心操作频率低于第一操作频率，并且具有低于第一泄漏的相关联的第二泄漏。处理器核心布置（10）能够从第一处理器核心（12）切换到第二处理器核心（14），反之亦然。该方法包括：模拟所述处理器核心布置以确定所述第一处理器核心和所述第二处理器核心的参考泄漏，所述第一处理器核心在所述模拟中具有SRPG特征; 以及设定所述第二操作频率，使得所述第一泄漏和所述第二泄漏的总和基本上等于所述参考泄漏。该方法还包括提供所述第一处理器核心（12）和所述第二处理器核心（14），但不提供所述SRPG特征。

5. 发明申请

WO2013079988A1 INTEGRATED CIRCUIT DEVICE, ASYMMETRIC MULTI-CORE PROCESSING MODULE, ELECTRONIC DEVICE AND METHOD OF MANAGING EXECUTION OF COMPUTER PROGRAM CODE THEREFOR 审中-公开
标题翻译：集成电路设备，不对称多核处理模块，电子设备及其计算机程序代码的执行方法
公开(公告)号：WO2013079988A1
公开(公告)日：2013-06-06
申请号：PCT/IB2011/055326
申请日：2011-11-28
申请人： FREESCALE SEMICONDUCTOR, INC. , ROZEN, Anton , KUZMIN, Dan , PRIEL, Michael , SMOLYANSKY, Leonid
发明人： ROZEN, Anton , KUZMIN, Dan , PRIEL, Michael , SMOLYANSKY, Leonid
IPC分类号： G06F9/46
CPC分类号： G06F15/76 , G06F9/5083 , G06F9/5094 , G06F2015/765 , Y02D10/22
摘要： An asymmetric multi-core processing module is described. The asymmetric multi-core processing module comprises at least one processing core of a first type, at least one processing core of at least one further type, and at least one core identifier configuration component. The at least one core identifier configuration component is arranged to enable dynamic configuration of a value of a core identifier of at least one of the processing cores of the first and at least one further types.
摘要翻译：描述了一种非对称多核处理模块。非对称多核处理模块包括至少一个第一类型的处理核心，至少一个另外类型的至少一个处理核心和至少一个核心标识符配置组件。所述至少一个核心标识符配置组件被布置成使得能够动态地配置第一和至少一个其他类型的至少一个处理核心的核心标识符的值。

6. 发明申请

WO2011154776A1 INFORMATION PROCESSING DEVICE AND METHOD 审中-公开
标题翻译：信息处理装置和方法
公开(公告)号：WO2011154776A1
公开(公告)日：2011-12-15
申请号：PCT/IB2010/052599
申请日：2010-06-11
申请人： FREESCALE SEMICONDUCTOR, INC. , PRIEL, Michael , ROZEN, Anton , SMOLYANSKY, Leonid
发明人： PRIEL, Michael , ROZEN, Anton , SMOLYANSKY, Leonid
IPC分类号： G06F9/06 , G06F1/32
CPC分类号： G06F1/3275 , G01R31/318536 , G01R31/318558 , G06F1/3203 , G06F1/3287 , G06F11/1402 , Y02D10/14 , Y02D10/171
摘要： An information processing device (10) comprises a first memory (12), a second memory (14), data transfer circuitry (22), power gating circuitry (18), and a controller (20). The first memory comprises at least two volatile memory units (16). The controller (20) receives or generates a request for setting the information processing device (10) into a reduced power mode; in response to the request, it selects specific memory units (24) among the memory units (16); controls the data transfer circuitry (22) to transfer data from the selected memory units (24) to the second memory (14); and controls the power gating circuitry (18) to power down the selected memory units (24).
摘要翻译：信息处理设备（10）包括第一存储器（12），第二存储器（14），数据传输电路（22），电源门控电路（18）和控制器（20）。第一存储器包括至少两个易失性存储器单元（16）。控制器（20）接收或产生将信息处理设备（10）设置为降低功率模式的请求; 响应于该请求，它选择存储单元（16）中的特定存储单元（24）; 控制数据传输电路（22）将数据从所选择的存储器单元（24）传送到第二存储器（14）; 并且控制电源门控电路（18）以使所选择的存储器单元（24）断电。

7. 发明申请

WO2005050425A1 METHOD AND DEVICE FOR REGULATING A VOLTAGE SUPPLY TO A SEMICONDUCTOR DEVICE 审中-公开
标题翻译：用于调节半导体器件的电压供应的方法和装置
公开(公告)号：WO2005050425A1
公开(公告)日：2005-06-02
申请号：PCT/IB2004/003939
申请日：2004-11-18
申请人： FREESCALE SEMICONDUCTOR, INC. , ROZEN, Anton , PRIEL, Michael , SMOLYANSKY, Leonid , BOBROV, Boris
发明人： ROZEN, Anton , PRIEL, Michael , SMOLYANSKY, Leonid , BOBROV, Boris
IPC分类号： G06F1/32
CPC分类号： G06F1/324 , G06F1/26 , G06F1/3203 , G06F1/3296 , Y02D10/126 , Y02D10/172
摘要： A device for regulating a voltage supply to a semiconductor device, the device comprising memory for storing a plurality of performance ranges, wherein the respective performance ranges are associated with a respective supply voltage; means for measuring the performance of the semiconductor device; and a regulator for modifying the supply voltage to the semiconductor device if the measured performance of the semiconductor device is not within a predetermined portion of the performance range associated with the voltage supplied to the semiconductor device.
摘要翻译：一种用于调节对半导体器件的电压供应的器件，所述器件包括用于存储多个性能范围的存储器，其中所述各个性能范围与相应的电源电压相关联; 用于测量半导体器件的性能的装置; 以及调节器，如果所测量的半导体器件的性能不在与供应给半导体器件的电压相关联的性能范围的预定部分内，则用于修改供应给半导体器件的电源电压。

8. 发明申请

WO2012014015A3 APPARATUS AND METHOD FOR REDUCING PROCESSOR LATENCY 审中-公开
公开(公告)号：WO2012014015A3
公开(公告)日：2012-02-02
申请号：PCT/IB2010/053410
申请日：2010-07-27
申请人： FREESCALE SEMICONDUCTOR, INC. , PRIEL, Michael , KUZMIN, Dan , ROZEN, Anton , SMOLYANSKY, Leonid
发明人： PRIEL, Michael , KUZMIN, Dan , ROZEN, Anton , SMOLYANSKY, Leonid
IPC分类号： G06F13/14 , G06F13/16
摘要： There is provided a data processing system comprising a central processing unit (110), a processor cache memory (1 13) operably coupled to the central processing unit (110) and an external connection (121 ) operably coupled to the central processing unit (110) and processor cache memory (113)in which a portion of the data processing system is arranged to load data directly from the external connection (121 ) into the processor cache memory (113) and modify a source address of said directly loaded data. There is also provided a method of improving latency in a data processing system having a central processing unit (110) operably coupled to a processor cache memory (113) and an external connection (121 ) operably coupled to the central processing unit (110) and processor cache memory (113), comprising loading data directly from the external connection (121 ) into the processor cache memory (113) and modifying a source address for said data to become indicative of a location other than from the external connection (121 ).

9. 发明申请

WO2014006450A1 METHOD AND APPARATUS FOR MANAGING A THERMAL BUDGET OF AT LEAST A PART OF A PROCESSING SYSTEM 审中-公开
标题翻译：用于管理至少一个处理系统的一部分的热预算的方法和装置
公开(公告)号：WO2014006450A1
公开(公告)日：2014-01-09
申请号：PCT/IB2012/053385
申请日：2012-07-03
申请人： FREESCALE SEMICONDUCTOR, INC. , ROZEN, Anton , DRUKER, Roy , SMOLYANSKY, Leonid
发明人： ROZEN, Anton , DRUKER, Roy , SMOLYANSKY, Leonid
IPC分类号： G06F1/00 , G06F9/44
CPC分类号： G06F1/28 , G06F1/3206 , G06F9/466
摘要： A method of managing a thermal budget, for at least a part of a processing system, is described. The method comprises, upon detection of a use case event, determining a thermal budget violation time window for a current use case scenario of the at least part of the processing system, and managing the thermal budget for the at least part of the processing system based at least partly on the determined thermal budget violation time window.
摘要翻译：描述了对于处理系统的至少一部分来管理热预算的方法。该方法包括：在检测到用例事件之后，确定处理系统的至少一部分的当前用例场景的热预算违反时间窗口，以及基于处理系统的至少部分的热预算管理至少部分地基于确定的热预算违规时间窗口。

10. 发明申请

WO2007034265A1 SYSTEM AND METHOD FOR STORING STATE INFORMATION 审中-公开
标题翻译：用于存储状态信息的系统和方法
公开(公告)号：WO2007034265A1
公开(公告)日：2007-03-29
申请号：PCT/IB2005/053108
申请日：2005-09-21
申请人： FREESCALE SEMICONDUCTOR, INC. , PRIEL, Michael , KUZMIN, Dan , SMOLYANSKY, Leonid
发明人： PRIEL, Michael , KUZMIN, Dan , SMOLYANSKY, Leonid
IPC分类号： G06F1/32 , G06F9/46
CPC分类号： G06F9/462
摘要： A method (300, 400) for storing state information, the method includes storing (364),at a first circuit, state information representative of a state of a second circuit while the second circuit enters a low power mode; characterized by receiving (352) an indication that a task switching from a first task to a second task should occur; storing (354) a state information representative of a state of the second circuit, at the first circuit; receiving (356) an indication that the first task should be resumed; and writing (358) the stored state information from the first circuit to the second circuit. A system (100) includes a first circuit (110, 110') and a second circuit (120, 120'), whereas the first circuit is connected to the second circuit and is adapted to store state information representative of a state of a second circuit; characterized by including a controller (150) adapted to control a storage of the state information if at least a portion of the second circuit is powered down or if the second circuit is associated with a task switching operation.
摘要翻译：一种用于存储状态信息的方法（300,400），所述方法包括在第一电路处存储（364）表示第二电路进入低功率模式的第二电路的状态的状态信息; 其特征在于，接收（352）从第一任务切换到第二任务的任务的指示; 在第一电路处存储（354）表示第二电路的状态的状态信息; 接收（356）应该恢复第一个任务的指示; 以及将所存储的状态信息从所述第一电路写入（358）到所述第二电路。系统（100）包括第一电路（110,110'）和第二电路（120,120'），而第一电路连接到第二电路，并且适于存储表示第二电路电路; 其特征在于包括：控制器（150），适于在所述第二电路的至少一部分断电时或者所述第二电路与任务切换操作相关联时控制所述状态信息的存储。

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