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1. 发明申请

WO2007034265A1 SYSTEM AND METHOD FOR STORING STATE INFORMATION 审中-公开
标题翻译：用于存储状态信息的系统和方法
公开(公告)号：WO2007034265A1
公开(公告)日：2007-03-29
申请号：PCT/IB2005/053108
申请日：2005-09-21
申请人： FREESCALE SEMICONDUCTOR, INC. , PRIEL, Michael , KUZMIN, Dan , SMOLYANSKY, Leonid
发明人： PRIEL, Michael , KUZMIN, Dan , SMOLYANSKY, Leonid
IPC分类号： G06F1/32 , G06F9/46
CPC分类号： G06F9/462
摘要： A method (300, 400) for storing state information, the method includes storing (364),at a first circuit, state information representative of a state of a second circuit while the second circuit enters a low power mode; characterized by receiving (352) an indication that a task switching from a first task to a second task should occur; storing (354) a state information representative of a state of the second circuit, at the first circuit; receiving (356) an indication that the first task should be resumed; and writing (358) the stored state information from the first circuit to the second circuit. A system (100) includes a first circuit (110, 110') and a second circuit (120, 120'), whereas the first circuit is connected to the second circuit and is adapted to store state information representative of a state of a second circuit; characterized by including a controller (150) adapted to control a storage of the state information if at least a portion of the second circuit is powered down or if the second circuit is associated with a task switching operation.
摘要翻译：一种用于存储状态信息的方法（300,400），所述方法包括在第一电路处存储（364）表示第二电路进入低功率模式的第二电路的状态的状态信息; 其特征在于，接收（352）从第一任务切换到第二任务的任务的指示; 在第一电路处存储（354）表示第二电路的状态的状态信息; 接收（356）应该恢复第一个任务的指示; 以及将所存储的状态信息从所述第一电路写入（358）到所述第二电路。系统（100）包括第一电路（110,110'）和第二电路（120,120'），而第一电路连接到第二电路，并且适于存储表示第二电路电路; 其特征在于包括：控制器（150），适于在所述第二电路的至少一部分断电时或者所述第二电路与任务切换操作相关联时控制所述状态信息的存储。

2. 发明申请

WO2006120507A1 METHOD FOR POWER REDUCTION AND A DEVICE HAVING POWER REDUCTION CAPABILITIES 审中-公开
标题翻译：降低功率的方法和具有降低功率的装置
公开(公告)号：WO2006120507A1
公开(公告)日：2006-11-16
申请号：PCT/IB2005/051539
申请日：2005-05-11
申请人： FREESCALE SEMICONDUCTOR, INC. , PRIEL, Michael , KUZMIN, Dan , ROZEN, Anton , SMOLYANSKY, Leonid
发明人： PRIEL, Michael , KUZMIN, Dan , ROZEN, Anton , SMOLYANSKY, Leonid
IPC分类号： G06F1/32
CPC分类号： G06F1/3225 , G06F1/3275 , G06F1/3287 , G06F12/0804 , G06F12/0864 , G06F2212/1028 , Y02D10/13 , Y02D10/14 , Y02D10/171 , Y02D50/20
摘要： A method (100) for power reduction, the method includes determining (140) whether to power down the at least portion of the component in response to a relationship between an estimated power gain and an estimated power loss resulting from powering down the at least portion of the component during the low power mode, and selectively (150) providing power to at least a portion of a component of an integrated circuit during a low power mode. A device (10) having power reduction capabilities, the device includes power switching circuitry (30) adapted to selectively provide power to at least a portion (22, 24, 26, 28) of a component (20) of the device during a low power mode, and a power management circuitry (40) adapted to determine whether to power down at least the portion (22, 24, 26, 28) of the component during a low power mode in response to a relationship between an estimated power gain and an estimated power loss resulting from powering down the at least portion (22, 24, 26, 28) of the component (20) during the low power.
摘要翻译：一种用于功率降低的方法（100），所述方法包括确定（140）响应于所估计的功率增益与由所述至少部分断电而产生的估计功率损耗之间的关系来确定（140）所述部件的至少部分的掉电在低功率模式期间选择性地（150）向集成电路的部件的至少一部分提供电力。一种具有功率降低能力的设备（10），该设备包括功率切换电路（30），其适于在低电平期间选择性地向设备的部件（20）的一部分（22,24,26,28）提供功率功率模式和功率管理电路（40），其适于在低功率模式期间响应于估计的功率增益和功率模式之间的关系来确定是否在低功率模式期间对组件的至少部分（22,24,26,28）在低功率期间由部件（20）的至少部分（22,24,26,28）断电导致的估计的功率损耗。

3. 发明申请

WO2013079988A1 INTEGRATED CIRCUIT DEVICE, ASYMMETRIC MULTI-CORE PROCESSING MODULE, ELECTRONIC DEVICE AND METHOD OF MANAGING EXECUTION OF COMPUTER PROGRAM CODE THEREFOR 审中-公开
标题翻译：集成电路设备，不对称多核处理模块，电子设备及其计算机程序代码的执行方法
公开(公告)号：WO2013079988A1
公开(公告)日：2013-06-06
申请号：PCT/IB2011/055326
申请日：2011-11-28
申请人： FREESCALE SEMICONDUCTOR, INC. , ROZEN, Anton , KUZMIN, Dan , PRIEL, Michael , SMOLYANSKY, Leonid
发明人： ROZEN, Anton , KUZMIN, Dan , PRIEL, Michael , SMOLYANSKY, Leonid
IPC分类号： G06F9/46
CPC分类号： G06F15/76 , G06F9/5083 , G06F9/5094 , G06F2015/765 , Y02D10/22
摘要： An asymmetric multi-core processing module is described. The asymmetric multi-core processing module comprises at least one processing core of a first type, at least one processing core of at least one further type, and at least one core identifier configuration component. The at least one core identifier configuration component is arranged to enable dynamic configuration of a value of a core identifier of at least one of the processing cores of the first and at least one further types.
摘要翻译：描述了一种非对称多核处理模块。非对称多核处理模块包括至少一个第一类型的处理核心，至少一个另外类型的至少一个处理核心和至少一个核心标识符配置组件。所述至少一个核心标识符配置组件被布置成使得能够动态地配置第一和至少一个其他类型的至少一个处理核心的核心标识符的值。

4. 发明申请

WO2012014015A3 APPARATUS AND METHOD FOR REDUCING PROCESSOR LATENCY 审中-公开
公开(公告)号：WO2012014015A3
公开(公告)日：2012-02-02
申请号：PCT/IB2010/053410
申请日：2010-07-27
申请人： FREESCALE SEMICONDUCTOR, INC. , PRIEL, Michael , KUZMIN, Dan , ROZEN, Anton , SMOLYANSKY, Leonid
发明人： PRIEL, Michael , KUZMIN, Dan , ROZEN, Anton , SMOLYANSKY, Leonid
IPC分类号： G06F13/14 , G06F13/16
摘要： There is provided a data processing system comprising a central processing unit (110), a processor cache memory (1 13) operably coupled to the central processing unit (110) and an external connection (121 ) operably coupled to the central processing unit (110) and processor cache memory (113)in which a portion of the data processing system is arranged to load data directly from the external connection (121 ) into the processor cache memory (113) and modify a source address of said directly loaded data. There is also provided a method of improving latency in a data processing system having a central processing unit (110) operably coupled to a processor cache memory (113) and an external connection (121 ) operably coupled to the central processing unit (110) and processor cache memory (113), comprising loading data directly from the external connection (121 ) into the processor cache memory (113) and modifying a source address for said data to become indicative of a location other than from the external connection (121 ).

5. 发明申请

WO2011107828A1 INTEGRATED CIRCUIT DEVICE COMPRISING CLOCK GATING CIRCUITRY, ELECTRONIC DEVICE AND METHOD FOR DYNAMICALLY CONFIGURING CLOCK GATING 审中-公开
标题翻译：包含时钟提升电路的集成电路装置，电子装置和用于动态配置时钟增益的方法
公开(公告)号：WO2011107828A1
公开(公告)日：2011-09-09
申请号：PCT/IB2010/050915
申请日：2010-03-03
申请人： FREESCALE SEMICONDUCTOR, INC. , PRIEL, Michael , KAPILUSHNIK, Ilan , KUZMIN, Dan
发明人： PRIEL, Michael , KAPILUSHNIK, Ilan , KUZMIN, Dan
IPC分类号： H03K19/096 , H03K3/037
CPC分类号： H03K19/0016 , G06F1/3237 , Y02D10/128
摘要： An integrated circuit (100) comprises clock gating circuitry (140) comprising at least one gating component (210, 220) located within a clock distribution network (120) and arranged to enable at least one part of the clock distribution network (120) to be gated, and gating control circuitry (230, 240) arranged to cause the at least one gating component (210, 220) to disable the at least one part of the clock distribution network (120) upon certain conditions being fulfilled. The clock gating circuitry (140) further comprises clock gating disabling circuitry (250, 260) configurable to enable the gating of the at least one part of the clock distribution network (120) to be disabled.
摘要翻译：集成电路（100）包括时钟选通电路（140），其包括位于时钟分配网络（120）内的至少一个选通组件（210,220），并且被布置成使得时钟分配网络（120）的至少一部分能够以及选通控制电路（230,240），其被布置成在满足某些条件时使所述至少一个选通部件（210,220）禁用所述时钟分配网络（120）的所述至少一部分。时钟选通电路（140）还包括时钟选通禁止电路（250,260），可配置为使得能够禁止时钟分配网络（120）的至少一部分的选通。

6. 发明申请

WO2011058393A1 INTEGRATED CIRCUIT AND METHOD FOR REDUCTION OF SUPPLY VOLTAGE CHANGES 审中-公开
标题翻译：集成电路和降低电源电压变化的方法
公开(公告)号：WO2011058393A1
公开(公告)日：2011-05-19
申请号：PCT/IB2009/055040
申请日：2009-11-12
申请人： FREESCALE SEMICONDUCTOR, INC. , ROZEN, Anton , KUZMIN, Dan , PRIEL, Michael
发明人： ROZEN, Anton , KUZMIN, Dan , PRIEL, Michael
IPC分类号： G11C5/14 , G11C7/10
CPC分类号： H03K19/00346 , G06F1/26 , G06F1/28 , G06F1/305
摘要： An integrated circuit and a method. The integrated circuit includes an internal component having an output for providing a driven input signal; an output driver, connected to the internal component, for converting said driven input signal in an output signal; an output pad for outputting said output signal to a component outside the integrated circuit; a power grid configured to supply a supply voltage to the output driver; a controllable current consuming component connected to the power grid, said connectable current consuming component being controllable to consume current in accordance with a supply voltage change reduction pattern; a change detector connected to the internal component and the controllable current consuming component, for detecting a change in said driven input signal prior to said change resulting in a change in said output signal and to control said current consuming component to consume current in response to said detecting.
摘要翻译：一种集成电路和方法。集成电路包括具有用于提供驱动输入信号的输出的内部部件; 连接到内部组件的输出驱动器，用于在输出信号中转换所述驱动输入信号; 输出焊盘，用于将所述输出信号输出到集成电路外的部件; 配置为向输出驱动器提供电源电压的电网; 连接到电网的可控电流消耗部件，所述可连接电流消耗部件可控制以根据电源电压变化减小模式消耗电流; 连接到内部组件和可控电流消耗部件的变化检测器，用于在所述变化之前检测所述驱动输入信号的变化，导致所述输出信号的变化，并且响应于所述输入信号控制所述电流消耗部件消耗电流检测。

7. 发明申请

WO2010011378A1 SYSTEM AND METHOD FOR POWER MANAGEMENT 审中-公开
标题翻译：电力管理系统与方法
公开(公告)号：WO2010011378A1
公开(公告)日：2010-01-28
申请号：PCT/US2009/041079
申请日：2009-04-20
申请人： FREESCALE SEMICONDUCTOR INC. , ROZEN, Anton , KUZMIN, Dan , PRIEL, Michael
发明人： ROZEN, Anton , KUZMIN, Dan , PRIEL, Michael
IPC分类号： G06F1/26 , G06F1/32 , G06F1/28
CPC分类号： G06F1/3203
摘要： A system, that includes: a memory unit adapted to store state duration statistics indicative of possible low power state durations and probabilities associates with the possible state durations; and a power controller, adapted to: receive a request to cause a circuit to enter a next state, and assist in causing the circuit to enter the next state if during a delay period that follows a reception of the request the power controller does not receive a request to cause the circuit to exit the next state; wherein the delay period is determined in response to: (i) the next state duration statistics, (ii) power saving gained from entering the next state; and (iii) power penalty associated with entering the next state and exiting the next state.
摘要翻译：一种系统，包括：存储器单元，适于存储指示与可能的状态持续时间相关联的可能的低功率状态持续时间和概率的状态持续时间统计; 以及功率控制器，适于：接收使电路进入下一状态的请求，并且如果在所述功率控制器未接收到的请求的接收之后的延迟时段期间，则辅助使所述电路进入下一状态使电路退出下一状态的请求; 其中所述延迟周期是响应于：（i）下一状态持续时间统计，（ii）从进入下一状态获得的功率节省; 和（iii）与进入下一状态并退出下一状态相关联的功率损失。

8. 发明申请

WO2008050180A1 POWER SUPPLY MONITORING METHOD AND SYSTEM 审中-公开
标题翻译：电力监控方法与系统
公开(公告)号：WO2008050180A1
公开(公告)日：2008-05-02
申请号：PCT/IB2006/053968
申请日：2006-10-27
申请人： FREESCALE SEMICONDUCTOR, INC. , PRIEL, Michael , ASHKENAZI, Asaf , KUZMIN, Dan
发明人： PRIEL, Michael , ASHKENAZI, Asaf , KUZMIN, Dan
IPC分类号： G06F21/00 , G06F21/02
CPC分类号： G06F21/81 , G06F21/554
摘要： A device (10) having a power supply monitoring capabilities, the device (10) includes: a power supply unit (60); at least one real time clock generator counter (150) adapted to receive a supply voltage from the power supply unit (60); a fixed value storage circuit (20) that is un-accessible to software executed by a processor (130); wherein the fixed value storage circuit (20) stores a fixed value; wherein the fixed value includes multiple bits; a volatile storage unit (30), being accessible to the processor (130); wherein the volatile storage unit (30) is adapted to: (i) store a reset value after being reset; (ii) receive the fixed value during an initialization state; and (iii) store the fixed value until being reset; wherein the volatile storage unit (30) is designed such that there is a low probability that the reset value equals the fixed value; and a comparator (40) adapted to provide a tamper indication if the fixed value stored at the fixed value storage circuit differs from a value stored at the volatile storage unit (30).
摘要翻译：一种具有电源监控能力的设备（10），所述设备（10）包括：电源单元（60）; 至少一个实时时钟发生器计数器（150），适于从所述电源单元（60）接收电源电压; 对由处理器执行的软件不可访问的固定值存储电路（20）; 其中，所述固定值存储电路（20）存储固定值; 其中所述固定值包括多个比特; 易失性存储单元（30），可由处理器（130）访问; 其中所述易失性存储单元（30）适于：（i）在复位之后存储复位值; （ii）在初始化状态期间接收固定值; 和（iii）存储固定值直到复位为止; 其中所述易失性存储单元（30）被设计为使得所述复位值等于所述固定值的概率很低; 以及如果存储在固定值存储电路上的固定值与存储在易失性存储单元（30）中的值不同，则适于提供篡改指示的比较器（40）。

9. 发明申请

WO2007138387A1 DEVICE AND METHOD FOR TESTING INTEGRATED CIRCUITS 审中-公开
标题翻译：用于测试集成电路的装置和方法
公开(公告)号：WO2007138387A1
公开(公告)日：2007-12-06
申请号：PCT/IB2006/051700
申请日：2006-05-29
申请人： FREESCALE SEMICONDUCTOR, INC. , BARUCH, Ezra , PRIEL, Michael , KUZMIN, Dan
发明人： BARUCH, Ezra , PRIEL, Michael , KUZMIN, Dan
IPC分类号： G01R31/28
CPC分类号： G01R31/31703 , G01R31/2836 , G01R31/318525
摘要： A method and device for testing an integrated circuit. The method (200) includes selecting (220) between a shadow latch data retention mode and a shadow latch test mode; performing (230) a first test of an integrated circuit; storing (260), at the shadow latch if the shadow latch test mode is selected, information representative of a first test-imposed state; performing (280) a second test of the integrated circuit; and generating (290) a test equipment detectable signal if the first test-imposed state differs from a second test- imposed state of the tested latch.
摘要翻译：一种用于测试集成电路的方法和装置。方法（200）包括在阴影锁存数据保持模式和阴影锁存测试模式之间选择（220）执行（230）集成电路的第一测试; 如果选择了阴影锁存测试模式，则在阴影锁存器处存储（260），表示第一测试状态的信息; 执行（280）集成电路的第二测试; 以及如果所述第一测试施加状态与所测试的锁存器的第二测试状态不同，则生成（290）测试设备可检测信号。

10. 发明申请

WO2007077497A1 METHOD FOR SYNCHRONIZING A TRANSMISSION OF INFORMATION AND A DEVICE HAVING SYNCHRONIZING CAPABILITIES 审中-公开
标题翻译：同步传输信息的方法和具有同步能力的设备
公开(公告)号：WO2007077497A1
公开(公告)日：2007-07-12
申请号：PCT/IB2006/050047
申请日：2006-01-05
申请人： FREESCALE SEMICONDUCTOR, INC. , PRIEL, Michael , KUZMIN, Dan , ZALTZMAN, Amir
发明人： PRIEL, Michael , KUZMIN, Dan , ZALTZMAN, Amir
IPC分类号： H04L7/00
CPC分类号： H04J3/0685 , H04L7/0008
摘要： Device having synchronization capabilities includes: a bus with multiple bus lines , a bus transmitter connected between an information source and the bus, a bus receiver connected between the bus and an information target ; the information source and the information target are mutually asynchronous; the device includes a bus receiver control circuit that controls the bus receiver circuit and a bus transmitter control circuit that controls the bus transmitter circuit ; the bus transmitter control circuit enables to transmit information from the information source to the bus in response to a change in a value of a feedback signal sent from the bus receiver control circuit and the bus receiver control circuit enables to provide information from the bus to the information target in response to a change in a value of a delayed strobe signal provided by a delay unit connected between the bus receiver control circuit and the bus transmitter control circuit .
摘要翻译：具有同步功能的设备包括：具有多条总线的总线，连接在信息源与总线之间的总线发送器，连接在总线和信息目标之间的总线接收器; 信息源和信息目标是相互异步的; 该装置包括控制总线接收器电路的总线接收器控制电路和控制总线发送器电路的总线发送器控制电路; 总线发送器控制电路能够响应于从总线接收器控制电路发送的反馈信号的值的变化而将信息从信息源传送到总线，并且总线接收器控制电路使得能够从总线向响应于连接在总线接收器控制电路和总线发送器控制电路之间的延迟单元提供的延迟选通信号的值的变化的信息目标。

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